JP2555156B2 - Dynamic RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (relates to) the present invention, dynamic RAM (R andom A ccess M e
mory), and more particularly to a dynamic RAM characterized by a sense amplifier driving circuit.

(Prior Art) A large-capacity dynamic RAM in which memory cells are integrated at high density is one of the important parts for achieving high functionality and miniaturization of electronic devices. But this kind of dynamic
In order to obtain a desired characteristic in a RAM (hereinafter sometimes abbreviated as DRAM), it is necessary to develop various technologies. This also conveys a technique for speeding up the operation of the sense amplifier, and accordingly various DRAMs with devised sense amplifiers have been proposed.

FIG. 5 is a diagram schematically showing the configuration of one column of a conventional DRAM including a typical conventional sensor amplifier circuit.

One column indicated by 10 in FIG. 5 has a memory cell array 11
, Sense amplifier array 21, and column decode array 31
It is equipped with. The memory cell array 11, the sense amplifier array 21, and the column decode array 31 are
And two bit lines, that is, a pair of bit lines shown by ▲ ▼.

In the memory cell array 11 in one column, a large number of word lines are orthogonal to the bit lines BL and ▲ ▼, and memory cells are connected to their intersections. In addition, in FIG. 5, two word lines WL _N , W
Only L _{N + 1} and two memory cells MC _N and MC _{N + 1} are shown.

The sense amplifier array 21 includes an N-channel sense amplifier 23 composed of _two N-channel transistors T ₁ and T ₂ and a P-channel sense amplifier 25 composed of two P-channel transistors T ₃ and T _4. It is equipped with Both source electrodes of the transistors T ₁ and T ₂ are connected to the GND line via the NMOS transistor 27, and
Both source electrodes of ₃ and T ₄ are connected to the power supply line V _CC via the PMOS transistor 29.

Further, the column decode array 31 is provided between the data bus pair indicated by DB and ▲ ▼ and the bit line pair BL and ▲ ▼, and is a T ₅ for opening and closing the bit line and the data bus.
And T ₆ and a control signal COLM for opening and closing the gate electrodes of these transistors T ₅ and T _6.
And a column decoder (Y-decoder) 33 for outputting

Next, the operation of the DRAM shown in FIG. 5 will be described. FIGS. 6 (A) to 6 (F) are operation waveform diagrams used for the description.

It is assumed that the word line WL _N is selected at time t ₀ (FIG. 6 (A)). Information about the memory cells MC _N connected to the word line WL _N is transmitted to the bit line ▲ ▼, and the bit line ▲ ▼ corresponding to the precharge voltage V _P is transmitted accordingly.
Potential changes by the amount of information stored in the memory cell MC _N.

Then, as shown in FIG. 6C, the sense amplifier drive signal φ _S supplied to the N-channel sense amplifier 23
At t ₁ , the sense amplifier drive signal φ _P , which changes from V _P to the GND level and is supplied to the P-channel sense amplifier 25 as shown in FIG. 6 (B), changes from V _P to V at time t ₁ .
_When it changes to _CC level and each sense amplifier is activated,
By the sense amplification operation of the sense amplifier, one potential of the bit line pair is raised to V _CC and the other potential is raised to the GND level.

Next, at time t ₂ , one of the many lines of the column decoder 31 enters the selected state. For example CO
It is assumed that the line selection state for outputting LM is entered and this line is in the high level state. Transistor accordingly
T ₅ and T ₆ are turned on. Here, since the precharge potential of the data line is V _D (where V _D is 0 <V _D <V _CC ), the charge amount in the data bus and the charge amount in the bit line are redistributed and one bit is The potential of the line approaches V _D level from V _CC level (discharged), and the potential of the other bit line approaches V _D level from GND level (charge), and as a result, the potentials of both bit lines rapidly approach each other. (See the time t ₂ portion in FIG. 6 (E)).

After this, at time t ₃ , the potential of both bit lines is V
_The other of _CC is restored to the GND level. Further, a potential difference between both bit lines is also generated on the data bus, and as a result, the bit line information is transmitted to the data bus.

(Problems to be Solved by the Invention) However, when the configuration of the conventional DRAM shown in FIG. 5 is applied to a large capacity memory, the bit line capacity is large at time t ₁ when the sense amplifier is activated. Due to the sensing operation, the charging / discharging time from the sense amplifier to the bit line becomes long. Further, when the capacitance of the data bus is larger than the capacitance of the bit line pair selected by the column decoder, the potential difference between the bit line pair becomes small when the column line is selected and the data bus DB / ▲ There is a problem that the data transmission time to ▼ becomes long. Therefore, DR that can be driven with high-speed access time
AM cannot be realized.

The present invention has been made in view of such points,
Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a DRAM that can be driven in a fast access time.

(Means for Solving the Problem) In order to achieve this object, according to the present invention, a gate for receiving a first control signal, a drain connected to one of a pair of bit lines, and one of a pair of sense amplifier nodes are provided. A first field effect transistor having a source connected to, a gate receiving the first control signal, a drain connected to the other of the bit line pair, and a source connected to the other of the sense amplifier node pair. A second field effect transistor having the first field effect transistor, and first transistor coupling means for selectively bringing the bit line pair and the sense amplifier node pair into a conductive state or a non-conductive state, and coupling between the sense amplifier node pair. Coupled between the first sense means for discharging one of the sense amplifier node pair in response to a second control signal, and the sense amplifier node pair. Is, and the dynamic RAM which comprises a second sensing means responsive to charge the other of said sense amplifier node pair to the third control signal
In the first transistor coupling means, the potential of each gate of the first and second field effect transistors is V _th or more (V _P +
V _th ) or less, and when the sense amplifier node and the bit line are turned from the non-conducting state to the conducting state after the sensing operation is completed, the potential of each gate is set to V _CC. (Where V _P is the precharge voltage of the bit line, V _th is the threshold voltage of the first transistor coupling means, and V _CC is the high level of the sense node).

Further, in implementing the present invention, it is preferable to provide the DRAM with a signal generating circuit for generating the first control signal. Further, the DRAM is coupled between the data bus pair and the data bus pair and the aforementioned sense amplifier node pair, and selectively connects between the aforementioned data bus pair and the aforementioned sense amplifier node pair in response to a column selection signal. It is preferable to provide a second transistor coupling means that conducts to.
Then, such a second transistor coupling means has a gate for receiving the above-mentioned column selection signal, a drain connected to the one sense amplifier node described above, and a source connected to one of the data bus pair described above. A third field effect transistor, a fourth field effect transistor having a gate for receiving the column selection signal, a drain connected to the other sense amplifier node described above, and a source connected to the other of the data bus pair described above. It is preferable to configure with.

(Operation) According to such a configuration, the following operation can be obtained.

"1" during the sense operation of the sense amplifier
Since the bit line on the level side and the sense amplifier node on the "1" level side are non-conductive, the sensing operation is performed with the bit line capacitance removed.

At the time of sensing, the potential of the sense amplifier node on the “1” level side easily reaches the full level.

Further, during the amplification operation of the sense amplifier, the bit line on the “0” level side of the bit line pair and the sense amplifier node on the “0” level side of the sense amplifier node pair are in a conductive state, and Since the gate potential of the field effect transistor of the sense amplifier pair which discharges the sense node on the "0" level side has reached "1" full level, the discharge time of the bit line is shortened as compared with the conventional case.

In addition, when the sense amplifier node pair and the data bus pair are coupled by the second transistor coupling means for transmitting information to the data bus DB / ▲ ▼ and for full-level rewriting to the memory cell, In order to suppress the potential drop of the bit line when the level of one control signal (φ _L described later) is raised to V _CC + V _th + α, the bit line on the “1” side is charged so that it is not conducting. The potential change of the gate when the sense amplifier node and the bit line are brought into conduction is a slight change from a predetermined value of (V _P + V _th ) or less to V _CC. The bit line on the "1" level side can be charged from the V _P level to V _CC -V _th in a state in which the level of the sense amplifier node is almost maintained.

Further, after this, the second transistor coupling means couples between the sense amplifier node pair and the data bus pair,
Since the bit line on the "1" side and the sense amplifier node on the "1" side are in a high impedance state, the drop of the bit line is smaller than that of the sense amplifier node, and the potential of the bit line and the sense amplifier node is recovered. Because of the high speed, information is transmitted from the bit line to the data bus at high speed.

(Embodiment) A dynamic RAM of the present invention will be described below with reference to the drawings.
(Hereinafter, it may be abbreviated as DRAM.) An embodiment will be described. It should be understood that the drawings used for the description are only schematically shown so that the present invention can be understood, and therefore the present invention is not limited to the illustrated examples.

Description of DRAM Configuration First, the configuration of the DRAM of the embodiment will be described with reference to FIG. Note that FIG. 1 is a diagram schematically showing the configuration of one column of the DRAM of the embodiment.

In FIG. 1, 50 indicates one column. In this case, one column includes a memory cell array 61, a sense amplifier array 71,
The first transistor coupling means 91 provided between the column decode array 81 and the bit line pair consisting of two bit lines BL and ▲ ▼ of the memory cell array 61 and NA of the sense amplifier array 71 and the node pair indicated by ▲ ▼. And a second transistor coupling means 101 provided between the sense amplifier node pair NA, and the data bus pair DB, and controlled by the column decoder 83 of the column decode array 81.

Here, in the memory cell array 61, a large number of word lines are orthogonal to the respective bit lines BL and ▲ ▼, and the respective memory cells are connected to their intersections. Incidentally, FIG. 1 shows only two word lines WL _N and WL _{N + 1} and two memory cells MC _N and MC _{N + 1} .

The sense amplifier array 71 includes an N-channel sense amplifier 73 composed of _two N-channel field effect transistors T ₁ and T ₂ and a P-channel composed of two P-channel field effect transistors T ₃ and T _4. It has a channel amplifier 75. In response to the control signal φ _S , the T-channel sense amplifier 73 discharges the bit line on the “0” side and the sense amplifier node on the “0” side from, for example, the potential V _P to the ground potential.
In response to the control signal φ _P , the P-channel sense amplifier 75 changes the sense amplifier node on the “1” side to, for example, the potential V _P.
To the power supply potential V _CC . Both source electrodes of the transistors T ₁ and T ₂ are NMOS field effect transistors 77.
The via Yes connected to the GND line, the transistors T ₃ and T
₄ Both source electrodes are P-type as the fifth field effect transistor.
It is connected via a MOS field effect transistor 79 to a power supply line V _CC which also serves as a potential source for charging.

Further, the first transistor coupling means 91 makes one sense amplifier node and one bit line conductive while the sense amplifiers 73 and 75 perform a sensing operation, and makes the other sense amplifier node and the other bit line non-conductive. State,
After that, the other sense amplifier node and the other bit line are brought from the non-conducting state to the conducting state. In the case of this embodiment, the first transistor coupling means 91 is supplied with a common control signal φ _{L at} its gates, has its drain connected to the bit line BL and its source connected to the sense amplifier node NA. Channel field transistor T
₅ and an N-channel transistor T ₆ whose drain is connected to the bit line ▲ ▼ and whose source is connected to the sense amplifier node ▲ ▼. In this structure, the impedance of the transistors T ₅ and T ₆ is changed by changing the level of the φ _L signal in a predetermined manner, whereby the bit line and the sense amplifier node can be brought into a desired connection state. Note that the above φ _L
In the case of this embodiment, the signal is supposed to be output from the φ _L signal generating circuit 200 in FIG. The description of the φ _L signal generating circuit 200 will be given in the section “Description of φ _L signal generating circuit” described later.

Further, the second transistor coupling means 101 couples the sense amplifier node pair and the data bus pair when the sense amplifier node and the bit line which are in the non-conducting state during the amplifying operation of the sense amplifier are brought into the conductive state. To do. In the case of this embodiment, this second transistor coupling
Reference numeral 101 denotes an N-channel field effect transistor T ₇ having its gate connected in common to the column selection means 83, its drain connected to the sense amplifier node NA and its source connected to the data bus DB, and its drain connected to the sense amplifier node ▲.
And an N-channel field effect transistor T ₈ connected to the data source and connected to the data bus. In this configuration, the High level signal from the column selection means to the gates of the transistors T _7, T ₈ is output, the coupling state between the sense amplifier node pair and the data bus pair.

Description of DRAM Operation Next, the read operation of the DRAM of the above-described embodiment will be described. 2 (A) to (J) are operation waveform diagrams used for the description.

It is assumed that the word line WL _N is selected at time t ₀ (FIG. 2 (A)). The information of the memory cell MC _N connected to the word line W _{N L} is transmitted to the bit line ▲ ▼, and accordingly, the bit line ▲ ▼ which was at the precharge potential V _P.
Potential changes by the amount of information stored in the memory cell MC _N. At this time, since the level of the φ _L signal is V _CC + V _th + α and the transistors T ₅ and T ₆ are in the conductive state, the information generated on the bit line is transmitted to the sense amplifier node.

Next, at time t ₁ , the level of the signal φ _A supplied to the transistor 77 and the level of the signal ∘ supplied to the transistor 79 are changed as shown in FIGS. 2 (E) and (F), respectively. In response to this, the level of the sense amplifier drive signal φ _S supplied to the N-channel sense amplifier 73 changes from V _P to GND as shown in FIG. 2 (C) and is supplied to the P-channel sense amplifier 75. The level of the sense amplifier drive signal φ _P is changed as shown in FIG. 2 (D), so that each sense amplifier is activated. Further, at time t ₁ , the level of φ _L signal is changed to V _CC + V
_th + α (however, V _th is the threshold value of T ₅ and T ₆ , and α>
0). ) To V _P + V _th or less (indicated by V _P + V _th −β).
When β> 0), the level is changed to V _th or higher. Then
The transistor T _{5 of} the first transistor coupling means 91 connected between the sense amplifier node NA or ▲ ▼ on the "1" side (high potential side) and the bit line BL or ▲ ▼ on the "1" side or T ₆ goes into a non-conducting state. Since the N-channel MOS transistor T ₅ or T ₆ between the bit line on the “1” side and the sense amplifier node on the “1” side electrically isolates the parasitic capacitances C _B and C _NA , the P-channel sense amplifier. The 75 can quickly charge a reduced load. Therefore, the sense amplifier rapidly terminates the sensing operation / amplifying operation, and the potential of the sense amplifier node NA / ▲ ▼ reaches the “1” / “0” level. On the other hand, since the transistor T ₅ or T ₆ between the bit line on the “0” side and the sense amplifier node on the “0” side is in the ON state, the gate potential of the charge on this bit line and the sense node is “ It is discharged through the N-channel transistor in the N-channel sense amplifier 73 which is 1 ”full level. In this case, N channel MO in the sense amplifier 73
Since the gate of the S-transistor T ₅ or T ₆ rapidly rises to a high potential, the electric charge of the bit line on the “0” side is discharged in a short time.

Then, at time t ₂ , the level of the φ _L signal, which is a value at which a sufficient potential difference has occurred between the bit line pair BL, ▲ ▼, is raised to V _CC . As a result, the bit line on the "1" side and the sense amplifier node on the "1" side are brought into conduction, so that the potential of the bit line on the "1" side finally becomes V _CC -V _th (however, V _th Becomes the level indicated by the threshold value of T ₅ or T ₆ .

After the level of the φ _L signal is raised to V _CC , the output (COLM) of the column decoder 83 is set to High level, and the transistors T ₇ and T ₈ of the second transistor coupling means 101 are selected (ON). Since the precharge potential of the data bus is V _D (0 <V _D <V _CC ), the bit line and the sense amplifier node having a higher potential are discharged to the V _D level side, and the bit line having a lower potential is discharged. And the sense amplifier node
Charged to the V _D level side. However, at this time, since the gate potential of the transistor (T ₅ or T ₆ ) between the bit line on the “1” side and the sense amplifier node on the “1” side is V _CC , the gate potential of the transistor is V _CC. Compared to the case of + V _th + α, the connection state between the bit line and the sense amplifier node has a high impedance, and the drop in the potential of the bit line is significantly smaller than that of the sense amplifier node. The potential can be recovered quickly. Furthermore, since the sense amplifier node pair NA, ▲ ▼ and the data bus pair DB, ▲ ▼ are connected by the second transistor coupling means 101, the information of the sense amplifier node is transmitted on the data bus. .

Next, at time t ₃ , the level of the φ _L signal is changed from V _CC to V _CC +
Return to V _T + α. At this time, sense amplifier node NA / ▲
The potential of ▼ is at V _CC / GND level, and the potential of the bit line on the “1” side is at V _CC −V _T , so that the potential of bit line BL or ▲ ▼ reaches V _CC in a short time. Therefore, time t
_{At 3} , full-level writing to the memory cell becomes possible.

At time t ₄ , the potential of the bit line BL, ▲ ▼ is maintained at the V _CC / GND level, so the write back to the memory cell is completed. Therefore, the word line WL _N of the memory cell array 61 is set to G
It is lowered to the ND level, and a series of operations of reading information from the memory cell and rewriting information to the memory cell is completed.

Description of phi _L signal generating circuit will now be described first phi _L signal generating circuit for outputting a phi _L signal to the gate of the transistor coupling means 91 of the embodiment. FIG. 3 is a circuit diagram for explaining the φ _L signal generating circuit 200 of the embodiment, and FIGS. 4 (A) to (I) are operation waveform diagrams of the φ _L signal generating circuit 200.

The φ _L signal generation circuit 20 of the embodiment is controlled by the φ _A signal which controls the sense amplifier 73, and is an N-channel field effect transistor T as a sixth field effect transistor for connecting the φ _P signal run-in and the φ _L signal line.
₁₀ , an N-channel field effect transistor T ₁₁ as a seventh field effect transistor for precharging the φ _L signal line to the V _CC level controlled by the φ _B signal, and φ _C
V _CC + V _th + α on the φ _L signal line controlled by the signal (where V _th is the threshold value of the N-channel transistor, α ≧
An N-channel field effect transistor T ₁₂ of the level eighth field effect transistor for connecting the nodes N ₁ and phi _L signal line for supplying a 0), φ _B signals by controlled node N ₁ to V _CC level N-channel field-effect transistor T ₁₃ as a ninth field-effect transistor for precharging to node N, _one terminal connected to node N ₁ and the other terminal connected to φ _D signal supply terminal, φ _D It has a capacitance C _G for bootstrapping the potential of the node N ₁ to the V _CC + V _th + α level by signal control.

This φ _L signal generation circuit 200 operates as described below. The time t _1, t ₂ and t ₃ in the following discussion are intended respectively corresponding to time t _1, t ₂ and t ₃ during Operation of DRAM embodiment.

At time t ₁ , the φ _L signal is changed from V _CC + V _th + α level to V _P
In order to change the level to + V _th or less, the φ _C signal and the φ _D signal are respectively lowered and V _CC + V _th + α of the φ _L signal
The node N ₁ which is a level supply source and the φ _L signal line are brought out of conduction.

Next, at approximately the same time as time t ₁ , the φ _A signal rises and φ _L rises.
Conduction between the signal line and the φ _P signal line, and φ _P
Charge redistribution between the charges charged in the signal line and the charges charged in the φ _L signal line is performed. As a result, the potential of the φ _L signal line becomes a level below V _P + V _th .

Next, at time t ₂ , since the potentials of the φ _L signal line and the node N ₁ are precharged to the V _CC level, φ _B
Raise the signal to V _CC + V _th + α level.

At time t ₃ , the φ _B signal is dropped and the φ _C signal is changed to V _CC.
+ 2V _th + α, φ When the _D signal rises to the V _CC level, φ
The potential of the _L signal line changes to the level of V _CC + V _th + α.

Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made.

In the embodiment, the first and second transistor coupling means are each constituted by two N-channel field effect transistors, but the constitution of these means may be other suitable ones. For example, the field effect transistor provided in each transistor coupling means may be a PMOS transistor, and the polarity of the signal supplied to each coupling means may be opposite to that of the embodiment.

Further, the configuration of the φ _L signal generation circuit is not limited to the example shown in FIG. 3 and may be any other suitable configuration.

(Effect of the invention) As is apparent from the above description, the DRAM of the present invention
According to the above, in the sensing operation (time t _{1 in the} embodiment), since one bit line and one sense amplifier node become non-conductive, the sensing operation is performed without being affected by the bit line capacitance. Can be done. Therefore, high speed sensing operation is possible.

In addition, when the sense amplifier node pair and the data bus pair are coupled by the second transistor coupling means for transmitting information to the data bus DB / ▲ ▼, and φ is used for full-level rewriting to the memory cell. _{Set the L} signal level to V
_When the sense amplifier node and the bit line, which have been in the non-conductive state, are brought into a conductive state for the purpose of suppressing a drop in the potential of the bit line at the time of rising to _CC + V _th + α (in the embodiment, the time t ₂ ), The potential change of the gate is a slight change from a predetermined value of (V _P + V _th ) or less to V _CC ,
The bit line on the "1" level side is changed from V _P level while the level of the sense amplifier node on the "1" level side is almost maintained.
Can be charged up to V _CC -V _th .

Further, after this, the second transistor coupling means couples between the sense amplifier node pair and the data bus pair,
Since the bit line on the "1" side and the sense amplifier node on the "1" side are in a high impedance state, the drop of the bit line is smaller than that of the sense amplifier node, and the potential of the bit line and the sense amplifier node is recovered. The high speed enables high speed information transmission and high speed access.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing the structure of a DRAM of an embodiment of the present invention, FIGS. 2A to 2J are diagrams for explaining the operation of the DRAM of the embodiment, and FIG. FIG. 4 is a block diagram showing a φ _L signal generation circuit of a preferred embodiment applied to the invention, and FIGS. 4 (A) to 4 (I) are diagrams for explaining the operation of the φ _L signal generation circuit shown in FIG. FIG. 5 is a diagram schematically showing the structure of a conventional DRAM, and FIGS. 6A to 6F are diagrams for explaining the operation of the conventional DRAM shown in FIG. 50 ... 1 column of DRAM, 61 ... memory cell array 71 ... sense amplifier array 73 ... N channel sense amplifier 75 ... P channel sense amplifier 77 ... N channel field effect transistor 79 ... P channel field effect transistor 81 …… Column decode array 83 …… Column decoder 91 …… First transistor coupling means 101 …… Second transistor coupling means 20 …… φ _L signal generation circuit BL, ▲ ▼ …… Bit line pair NA, ▲ ▼… … Sense amplifier node pair DB, ▲ ▼ …… Data bus pair.

Claims (8)

(57) [Claims] 1. A first field effect transistor having a gate for receiving a first control signal, a drain connected to one of a bit line pair and a source connected to one of a sense amplifier node pair, and the first field effect transistor. A gate that receives a control signal,
A second field effect transistor having a drain connected to the other of the bit line pair and a source connected to the other of the sense amplifier node pair, and selectively between the bit line pair and the sense amplifier node pair. A first transistor coupling means for making a conductive state or a non-conductive state, and a first sense coupled between the sense amplifier node pair and discharging one of the sense amplifier node pair in response to a second control signal. And a second sense means coupled between the pair of sense amplifier nodes and charging the other of the pair of sense amplifier nodes in response to a third control signal. In the transistor coupling means, the potential of each gate of the first and second field effect transistors is V _th or more (V _P +
V _th ) or less, and when the sense amplifier node and the bit line are turned from the non-conducting state to the conducting state after the sensing operation is finished, the potential of each gate is set to V _CC. Characteristic dynamic RAM (where V _P is the precharge voltage of the bit line, V _th is the threshold voltage of the first transistor coupling means, and V _CC is the high level of the sense node). 2. The dynamic RAM according to claim 1, wherein the first sense means is an N-channel sense amplifier, and the second sense means is a P-channel sense amplifier. 3. When the information read to the bit line pair is transmitted to the sense amplifier node pair at the start of the sensing operation, the gate potentials of the first transistor coupling means are (V _CC + V _th). ) The above is the dynamic RAM according to claim 1. 4. The dynamic RAM according to claim 1, further comprising a signal generation circuit that generates the first control signal. 5. A data bus pair, coupled between the data bus pair and the sense amplifier node pair, and selectively conducting between the data bus pair and the sense amplifier node pair in response to a column selection signal. The dynamic RAM according to claim 1, further comprising: a second transistor coupling means. 6. The second transistor coupling means has a gate for receiving the column selection signal, a drain connected to one of the pair of sense amplifier nodes, and a source connected to one of the pair of data buses. Three field effect transistors, a fourth field effect transistor having a gate for receiving the column selection signal, a drain connected to the other of the sense amplifier node pair and a source connected to the other of the data bus pair. The dynamic RAM according to claim 5, characterized in that 7. The second sense means is connected to a potential source for charging through a fifth field effect transistor whose conduction / non-conduction is controlled in response to the third control signal. The dynamic RA according to claim 1, characterized in that
M. 8. The signal generating circuit comprises a gate for receiving the second control signal, a drain connected to an output terminal, and a source connected to a potential source for charging via the fifth field effect transistor. A sixth field-effect transistor having a gate for receiving the fourth control signal, a seventh field-effect transistor having a drain connected to the output terminal and a source connected to the potential source, and a fifth control signal. An eighth field effect transistor having a gate for receiving, a drain and a source connected to an output terminal, a gate for receiving the fourth control signal, a drain connected to a source of the eighth field effect transistor, and the potential source A ninth field effect transistor having a source connected to, and one electrode connected to the source of the eighth field effect transistor, Dynamic RAM according to claim 4, wherein the square of the electrode is one having a capacitor for receiving a sixth control signal.