JPH029084A - Dynamic ram - Google Patents

Abstract

PURPOSE:To increase the access speed by selectively making a pair of bit lines and a pair of sense amplifier nodes conductive or non-conductive in response of a control signal. CONSTITUTION:Transistors TRs T5 and T6 of a TR gate 91 set one sense amplifier node and the pair of bit lines to the conductive state and set the other to the conductive state after setting it to the non-conductive state in response to a signal phiL at the time of sense operation of sense amplifiers 73 and 75. A TR gate 101 couples the pair of sense amplifiers and a pair of data busses when sense amplifier nodes and bit lines are switched from the non- conductive state to the conductive state at the time of amplifying operation of sense amplifiers. By this constitution, the sensing operation is performed without being affected by the bit line capacity, and the discharging time is shortened in the amplifying operation to increase the access speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a dynamic RAM (βandamAcc
It relates to dynamic RAM (ess Memory), which has a special feature in the sense amplifier drive circuit.
This is related to this.

(Prior Art) A large-capacity dynamic RAM in which memory cells are highly integrated is one of the important components for achieving higher functionality and miniaturization of electronic snowmaking. However, in order to make this type of dynamic RAM (hereinafter sometimes abbreviated as DRAM) have desired characteristics, it is necessary to develop various technologies. This also applies to techniques for speeding up the operation of sense amplifiers, and therefore various DRAMs with improved sense amplifiers have been proposed.

FIG. 5 is a diagram schematically showing the configuration of one column of a conventional 08AM equipped with a typical conventional sense amplifier circuit.

One column indicated by 10 in FIG. 5 includes a memory cell array 1.
1, a sense amplifier array 21, and a column decode array 31. And memory cell array 1
1, the sense amplifier array 21, and the column decode array 31 are connected by two bit lines 8L and 8L, that is, a bit line pair.

In the memory cell array 11 in one column, a large number of word lines are orthogonal to each bit line BL, 8L, and memory cells are connected to each of these intersections. In addition, in FIG. 5, two words SiwtN
, WL□, and two memory cells MCH, MCm++
Only shown.

The sense amplifier array 21 also includes an N-channel sense amplifier 23 configured with two N-channel transistors T1 and T2''C: and two P-channel transistors 3.
and (1) a P channel sense amplifier 25 consisting of 4. Both source electrodes of the transistors (1) and (2) are connected to the GND line via the NMO5 transistor 27, and both source electrodes of the transistors (3) and (4) are connected to the power supply line (vcc) via the PMOS transistor 29. ing.

The column decode array 31 is provided between a data bus pair indicated by DB and DB, a bit line pair BL, and a port, and has two terminals indicated by Ts and Ts for opening and closing between the bit lines and the data bus. A control signal COLM! for opening and closing is applied to the gate electrodes of the transistors and transistors (5) and (6). Output column decoder (Y-decoder) 3
3.

Next, the operation of the DRAM shown in FIG. 5 will be explained.

FIGS. 6(A) to 6(F) are operational waveform diagrams for explaining the same.

Assume that word line WLN is selected at time to (FIG. 6(A)). Word line WL#l (The information of the connected memory cell MCN is transmitted to bit M8L, and accordingly, the potential of bit line BL, which was the precharge potential Vp, was stored in memory cell MC. The information changes.

Next, as shown in FIG. 6(C), the sense amplifier drive signal supplied to the N-channel sense amplifier 23 changes from Vp to the GNO level by one at time t, and
As shown in FIG. 6(B), the sense amplifier drive signal φ2 supplied to the P-channel sense amplifier 25 changes from Vp to Vcc level at time t, and each sense amplifier is activated. Due to the amplification operation,
The potential of one of the bit line pairs is raised to Vcc, and the potential of the other is raised to GNO level.

Next, at time t2, it is assumed that one of the many lines of the column decoder 31 enters the selected state. For example, a line outputting 0, COLMV, enters the selected state and this line becomes the old 9h level state. Correspondingly, transistors (1) and T8 are turned on. here,
The precharge potential of the data line is Vo'J (however, v
o is O<Vo< Vccte. ), the amount of charge on the data bus and the amount of charge on the bit line are redistributed, the potential of one bit line approaches (is discharged) from the Vcc level to the v0 level, and the potential of the other hint line approaches the V0 level from the GND level. As a result, the potentials of the bit lines approach each other rapidly (Fig. 6(E)).
(See the time t2 portion of ).

Then, at time t3, the potential of both bit lines is V.
cc, the other one recovers to GND level. Also,
A potential difference between both bit lines also occurs on the data bus, and as a result, bit line information is transmitted to the data bus.

(Problem to be Solved by the Invention) However, when the conventional 08AM configuration shown in FIG. 5 is applied to a large capacity memory, the bit line capacitance is large at time t1 when the sense amplifier is activated, so sensing Therefore, there is a problem that the charging/discharging time from the sense amplifier to the bit line becomes longer. Roughly speaking, if the capacitance of the data bus is larger than the capacitance of the bit line pair selected by the column decoder, the potential difference between the bit line pair becomes smaller when the column line is selected, and the data bus 08/ There is a problem that it takes a long time to transmit data to the DB. Therefore, a DRAM that can be driven with high speed access time cannot be realized.

The present invention has been made in view of the above points, and therefore, an object of the present invention is to solve the above-mentioned problems and provide a DRAM that can be driven with high speed access time.

(Means for solving the problem) In order to achieve this purpose, the dynamic R of this invention
According to the AM, a bit line pair and a sense amplifier node pair are coupled to each other, and the bit line pair and the sense amplifier node pair are selectively made conductive or non-conductive in response to a first control signal. a first transistor coupling means for discharging one of the aforementioned pair of sense amplifier nodes in response to a second control signal and coupled between the aforementioned pair of sense amplifier nodes; and a second sense means coupled between the pair of sense amplifier nodes and charging the other of the pair of sense amplifier nodes in response to a third control signal.

In implementing the present invention, the first transistor coupling means described above is connected to the gate receiving the first control signal, the drain connected to the one bit line described above, and the one sense amplifier node described above. a first field effect transistor having a source connected, a gate receiving said first control signal, a drain connected to said other bit line, and a source connected to said other sense amplifier node; It is preferable that the second field effect transistor is configured with a second field effect transistor having a second field effect transistor. Roughly speaking, when the first transistor coupling means is configured in this way, the potential of each gate of the above-mentioned negative and second field effect transistors is set to be above Vth and below (Vp+Vt, l) during sensing operation of the sense amplifier, and when the above-mentioned other When the sense amplifier node and the other bit line are changed from non-conductive to conductive, Vcc
(where Vp is the precharge voltage of the bit line, Vth is the threshold voltage of the first transistor coupling means, and Vcc is the old 9h level of the sense node).

Further, in implementing the present invention, it is preferable that this DRAM is provided with a signal generating circuit for generating the above-mentioned first control signal. Further, the DRAM is coupled to a data bus pair and between the data bus pair and the aforementioned sense amplifier node pair, and is selectively connected between the aforementioned data bus pair and the aforementioned sense amplifier node pair in response to a column selection signal. Preferably, a second transistor coupling means is provided which is electrically conductive to the second transistor. The second transistor coupling means has a gate for receiving the column selection signal, a drain connected to one of the sense amplifier nodes, and a source connected to one of the pair of data buses. a fourth field effect transistor; a fourth field effect transistor having a gate for receiving said column selection signal, a drain connected to said other sense amplifier node, and a source connected to the other of said data bus pair; It is preferable to configure the following.

(Function) According to such a configuration, the following effects can be obtained.

During sensing operation of the sense amplifier, there is no conduction between the bit line on the "1" level side and the sense amplifier node on the "1" level side, so when bit line customer 1 is removed, A sensing operation is performed.

During sensing, the potential of the sense amplifier node on the "1" level side easily reaches the full level.

Furthermore, during the amplification operation of the sense amplifier, the bit line on the "0" level side of the bit line pair and the sense amplifier node on the "0" level side of the sense amplifier node pair are in a conductive state, and, Since the gate potential of the field effect transistor of the sense amplifier pair that discharges the sense note on the rQJ level side has reached the "1" full level, the discharge time of the bit line is shortened compared to the conventional case.

Further, when the sense amplifier node pair and the data bus pair are coupled by the second transistor coupling means for information transmission to the data bus DB/DB, and when the first transistor coupling means is used for full level rewriting to the memory cell. control signal (φ
L) level to V. In order to suppress the drop in bit line potential when C+vtl is raised to 10, the non-conducting sense amplifier node and bit line are made conductive in order to charge the bit line on the "1" side. The potential change at the gate when
. Since it is a slight change up to C, the level of the sense amplifier node on the "]" level side is almost maintained and "1" is changed.
” level example bit line from ■2 level to vcc Vt
It can be charged up to h.

Furthermore, after this, the second transistor coupling means couples between the sense amplifier node pair and the data bus pair.
Since the bit line on the "1" side and the sense amplifier node on the "1" side are in a high impedance state, the drop in the bit line is smaller than that at the sense amplifier node, and the potential recovery of the bit line and sense amplifier node information is transmitted from the bit line to the data bus at high speed.

(Example) Hereinafter, with reference to the drawings, a dynamic RAM (
Hereinafter, it may be abbreviated as DRAM. ) will be explained below. It should be noted that the drawings used in the explanation are merely schematic illustrations to the extent that the present invention can be understood, and therefore, it should be understood that the present invention is not limited to only the illustrated examples.

DRAM Tongue 8 First, the configuration of the DRAM of the embodiment will be explained with reference to FIG. Note that FIG. 1 is a diagram schematically showing the configuration of one column of the DRAM of the embodiment.

50 in FIG. 1 indicates one column. In this case, one column includes a memory cell array 61 and a sense amplifier array 71.
, column decode array 81 , and memory cell array 6
Two bits of 1 S! A bit line pair consisting of BL and BL and NA of the sense amplifier array 71, a first transistor coupling means 91 provided between the node pair indicated by NA,
Sense amplifier node pair N^, NA and data bus pair DB
, a first transistor coupling means 101 provided in the DOM and controlled by a column decoder 83 of a column decode array 81.

Here, in the memory cell array 61, a large number of word lines are orthogonal to each bit line.
Each memory cell is connected to each of these intersection points.

In addition, in FIG. 1, two word lines WLN and WLN
+1 and two memory cells MC, MC, . . . are only shown.

The sense amplifier array 71 also includes an N-channel sense amplifier 73 configured with two N-channel field effect transistors TI and T2, and a P-channel sense amplifier 75 configured with two P-channel field effect transistors T3 and T4. It is equipped with. N channel sense amplifier 73
discharges the bit line on the "0" side and the sense amplifier node on the rQJ side from, for example, the potential Vp to the ground potential in response to the control signal φ. P-channel sense amplifier 75 charges the "1" side sense amplifier note from, for example, potential Vp to power supply potential Vcc in response to control signal φP. Note that both source electrodes of transistors T+ and T2 are connected to the GND line via an NMO3 field effect transistor 77, and both source electrodes of transistors 3 and 4 are connected to the power supply line via a PMOS field effect transistor 79. It is connected to Vcc.

Further, the first transistor coupling means 91 makes conductive between one sense amplifier node and one bit line and non-conductive between the other sense amplifier node and the other bit line during sensing operation of the sense amplifiers 73 and 75. After that, the connection between the other sense amplifier note and the other bit line is changed from a non-conducting state to a conducting state. In this embodiment, this first transistor coupling means 91
A common control signal φ is supplied to each gate, the drain is connected to the bit line, and the source is connected to the sense amplifier node NA, and the drain is connected to the bit line BL. and an N-channel transistor T6 whose source is connected to the sense amplifier node NA. In this configuration, the impedances of the transistors 5 and 6 can be changed by changing the signal level φ and the double signal in a predetermined manner, thereby making it possible to establish a desired connection state between the bit line and the sense amplifier node. It is assumed that the above-mentioned φ and double signal is outputted from the signal generating circuit 200 in FIG. 1 in the case of this embodiment. This φ1
The single generation circuit 200 will be described later [φ.

This will be explained in the "Description of Signal Generation Circuit" section.

Further, the second transistor coupling means 101 couples the sense amplifier node pair and the data bus pair when the sense amplifier node and the bit line, which were in a non-conductive state during the amplification operation of the sense amplifier, are brought into a conductive state. It is something to do. In this embodiment, the second transistor coupling 101 is an N-channel electric field whose gates are commonly connected to the column selection means 83, whose drains are connected to the sense amplifier node NA, and whose sources are connected to the data bus OB. It consists of an effect transistor (7) and an N-channel field effect transistor T8 whose drain is connected to the sense amplifier note NA and whose source is connected to the data bus surface. In this configuration, each transistor ■7,
When a Hic+h level signal is output from the column selection means to the gate of T8, the pair of sense amplifier nodes and the pair of data buses become coupled.

Resembles a mansion”l! Next, the read operation of the DRAM of the above-mentioned embodiment will be explained. FIGS. 2(A) to 2(J) are operational waveform diagrams for explaining this.

Assume that word line WLN is selected at time to (FIG. 2(A)). Word line WLN It: Information of the connected memory cell MC is transmitted to the bit line MC,
Accordingly, the bit line 8 which was at the precharge potential ■
The potential of L changes by the amount of information that has been stored in the memory cell MCN. At this time, φ, the double signal level is Vcc”Vth
Since the voltage is ten α and the transistors T5 and T6 are in a conductive state, the information generated on the bit line is transmitted to the sense amplifier note.

Next, at time t1, the level of the signal φ4 supplied to the transistor 77 and the level of the signal φ supplied to the transistor 79 are changed as shown in FIGS. 2(E) and 2(F), respectively.

Correspondingly, the level of the sense amplifier drive signal φ supplied to the N-channel sense amplifier 73 is as shown in FIG. 2(C).
As shown in FIG. activated. Furthermore, at time t1, φ.

Signal level 1FrVcc +Vth+α (however, vL
h is the threshold of ■5 and ■8, and α>0).
The level is changed from l/, +vtr+ or lower (denoted by Vp"Vth B.β>0) to a level higher than Vth. Then, the sense amplifier node N on the "1" side (higher potential side)
The transistor 5 or T6 of the first transistor coupling means 91 connected between A or NA and the bit line 8L or BL on the "1" side becomes non-conductive.

N-channel MO3)-transistor between the bit line on the “1” side and the sense amplifier node on the “1” side, or ■8
Since jl electrically isolates the parasitic capacitances Cs and CNA, the P-channel sense amplifier 75 can quickly charge the reduced load. Therefore, the sense amplifier quickly finishes sensing/amplifying operation and the sense amplifier node N
The potential of A/NA reaches the "1"/"0" level. On the other hand, since the dark transistor (5) or (8) between the bit line on the "0" side and the sense amplifier node on the "0" side is in the on state, the charge on this bit line and sense node is caused by the gate potential being " ]” is discharged through the N-channel transistor in the N-channel sense amplifier 73 which is at full level. In this case, the gate of the N-channel MOS transistor T5 or 6 in the sense amplifier 73 rapidly rises to a high potential, so that the charge on the "0" side bit line is discharged in a short time.

Next, at time t2, when a sufficient potential difference is generated between the bit line pair 8L and the 81st cycle, the φ and double signal level is raised to Vcc. As a result, the bit line on the “1” side and
” side sense amplifier nodes become conductive, so “
The potential of the bit line on the 1'' side is finally ■. c-Vth
(However, Vth is at the level shown by (1)5 or T8 threshold).

φ, after raising the double signal level to 'aVcc, set the output (COLM) of the column decoder 83 to High level,
The transistors 7 and T of the second transistor coupling means 101 are turned on. Here, since the precharge potential of the data bus is Vo (0<v.<Vcc), the bit line and sense amplifier note whose potential is higher than this discharges to the v0 level side, and the bit line and sense amplifier whose potential is lower than Vo (0<v.<Vcc). The node is V. Charged to the level side.

However, at this time, the gate potential of the transistor (Ts or 6) between the bit line on the "1" side and the sense amplifier node on the "1" side is Vcc, so the gate potential of the transistor is Vcc + Vth + α. Compared to the case
The connection state between the bit line and the sense amplifier node is high impedance, and the drop in the potential of the bit line and the sense amplifier node is significantly smaller than that of the sense amplifier node, so that the potential of the bit line and the sense amplifier node can be recovered quickly. Roughly, sense amplifier note vs. NA, NA and data bus vs. D
B and DB are connected to each other by the second transistor coupling means 101, so information of the sense amplifier node is transmitted on the data bus.

Next, at time t3, φ, from double signal level %Vcc to V
At this time, the potential of the sense amplifier node NA/NA is at the Vcc/GND level, and the potential of the bit line on the rlJ side is roughly at VccVT, so the potential of the bit line BL or 8L is shorted to Vcc. reached in time. Therefore, full level writing to the memory cell becomes possible at time t3.

At time t4, the potential of bit lines BL and 8L is vcc/GND.
Since the level has been secured, writing back to the memory cell has been completed. Therefore, the word a WLN of the memory cell array 61 is lowered to the GND level, and a series of operations of reading information from the memory cell and rewriting information to the memory cell are completed.

Next, the signal generating circuit for outputting the ψ1 signal to the gate of the first transistor coupling means 91 of the embodiment will be explained. Fig. 3 shows the φ and signal generating circuit of the embodiment. 4(A) to 4(1) are operational waveform diagrams of the signal generating circuit 200. FIG.

The small signal generation circuit 200 of the embodiment includes a sense amplifier 73
an N-channel field effect transistor T, for connecting the φ, signal line and φ, the signal line, controlled by the φ1 signal controlling the φ1 signal; , an N-channel field effect transistor T11 controlled by the φ8 signal for precharging the φ signal line to the vcc level, and an N-channel field effect transistor T11 controlled by the φ0 signal to supply the φ signal line to the vcc + Vth level.
+α (where Vth is the threshold value of the N-channel traffic disk, α≧O), the node
, an N-channel field effect transistor TI2 for connecting the signal line, and a node N controlled by the φ8 signal.

ヲ■. N-channel field effect transistor TI3 for precharging to 0 level, one terminal or node N,
and the other terminal is φ. Connected to the signal supply terminal φ. The potential of node N1 is set to V by signal control. c.
It has a capacitor Ca for bootstrapping to +Vth+α level.

This small signal generation circuit 200 operates as described below. Note that times t1, T2, and T3 in the following explanation
correspond to times t0, T2, and T3 in the explanation of the operation of the DRAM of the embodiment, respectively.

At time tl, φ, the double signal V. In order to change from c+Vth+α level to V level below Vtl+,
φ. signal and φ. When the signal falls, the node N1 and φ, which are the supply sources of the double signal vcc+v+α level, and the double signal line are brought into a non-conducting state.

Next, at almost the same time as time 1+, the φ1 signal is brought down and φ is
Make the signal line and φ2 signal line conductive, and φP
Charge redistribution is performed between the charge charged in the signal line and the charge charged in the signal line. This result φ.

The potential of the signal line becomes Vt below VP+Vth.

Next, at time t2, the φL signal line and node N.

In order to precharge each potential to the 8Vcc level, the φ8 signal is raised to the Vcc+Vth+α level.

Also, at time t3, the φ8 signal falls, and the φC signal %Vc
c + 2 Vth+α, φ. Signal': When raised to Vcc level, the potential of the φ signal line becomes Vcc+Vth
Changes to +α level.

However, this invention is not limited to the above-mentioned embodiments. Various modifications can be made.

In an embodiment, the first and second transistor coupling means include:
Although each of these means is composed of two N-channel field effect transistors, the structure of these means may be any other suitable structure.For example, the field effect transistor provided in each transistor coupling means may be a PMOS transistor and supplied to each coupling means. The polarity of the signal may be reversed from that of the embodiment.

Further, the configuration of the φ1 signal generation circuit is not limited to the example shown in FIG. 3, but may be any other suitable configuration.

(Effect of the invention) As is clear from the above explanation, the DRA of this invention
According to M, during sensing operation (time 1+ in the example), one bit line and one sense amplifier node are in a non-conducting state, so sensing is performed without the bit line capacitance being increased. Can perform movements. Therefore, high speed sensing operation is possible.

Also, when the sense amplifier node pair and the data bus pair are coupled by the second transistor coupling means for information transmission to the data bus DB/DB, and for full level rewriting to the memory cell, φ, Double signal level wo vcc
For the purpose of suppressing the drop in the potential of the bit line when the potential of the bit line rises to +V+α, when the sense amplifier node and the bit line, which have been in a non-conductive state, are brought into a conductive state (time t2 in the example). Since the potential change of the gate is a slight change from a predetermined value below (VP+V) to Vcc,
While the level of the sense amplifier node on the "1" level side is substantially maintained, the bit line on the "1" level side can be charged from the voltage level to vccVth.

Roughly speaking, after this, the second transistor coupling means couples the sense amplifier node pair and the data bus pair.
Since the bit line on the "1" side and the sense amplifier node on the "1" side are in a high impedance state, the drop in the bit line is smaller than that at the sense amplifier node, and the potential recovery of the bit line and sense amplifier node is fast, allowing for high-speed information transmission and high-speed access.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the configuration of a DRAM according to an embodiment of the present invention. FIGS. 2(A) to (J) are diagrams for explaining the operation of the DRAM according to an embodiment. FIG. FIGS. 4(A) to (I) are block diagrams showing the φ and signal generation circuits of preferred embodiments of the invention. FIGS. FIG. 5 is a diagram schematically showing the configuration of a conventional DRAM. FIGS.
FIG. 3 is a diagram for explaining the operation of M. 71...Sense amplifier array 73...N channel sense amplifier 75...P channel sense amplifier 77...N channel field effect transistor 79...
P-channel field effect transistor 81...Column decode array 83...Column decoder 91...First transistor coupling means 101...Second transistor coupling means 200...φ, signal generation circuits BL, BL ...Bit line pair NA, NA...Sense amplifier node pair DB, DB・
...data bus pair.

Claims (6)

[Claims] (1) A first circuit coupled between a bit line pair and a sense amplifier node pair, and selectively rendering conductive or non-conductive between the bit line pair and the sense amplifier node pair in response to a first control signal. a first sense means coupled between the pair of sense amplifier nodes and configured to discharge one of the pair of sense amplifier nodes in response to a second control signal; a second sensing means coupled thereto and charging the other of the pair of sense amplifier nodes in response to a third control signal. (2) The first transistor coupling means includes a first electric field having a gate for receiving the first control signal, a drain connected to the one bit line, and a source connected to the one sense amplifier node. effect transistor,
2. A second field effect transistor comprising a gate for receiving the first control signal, a drain connected to the other bit line, and a source connected to the other sense amplifier node. Dynamic RAM. (3) The potential of each gate of the first transistor coupling means is V_t_h or more (
3. The dynamic RAM according to claim 2, wherein V_p is equal to or less than V_p+V_t_h), and V_c_c is used to change the connection between the other sense amplifier node and the other bit line from a non-conductive state to a conductive state. The charge voltage, V_t_h, is the threshold voltage of the first transistor coupling means, and V_c_c is the High voltage of the sense node.
Indicates level. ). (4) The dynamic RAM according to claim 1, further comprising a signal generation circuit that generates the first control signal. (5) a pair of data buses; and a second second bus coupled between the pair of data buses and the pair of sense amplifier nodes and selectively conducting between the pair of data buses and the pair of sense amplifier nodes in response to a column selection signal. The dynamic RAM according to claim 1, further comprising transistor coupling means. (6) The second transistor coupling means has a gate for receiving the column selection signal, a drain connected to the one sense amplifier node, and a third field effect transistor coupling means having a source connected to one of the pair of data buses. and a fourth field effect transistor having a gate for receiving the column selection signal, a drain connected to the other sense amplifier node, and a source connected to the other of the data bus pair. Dynamic RAM described in .