JPS615496A - Dynamic ram - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a dynamic type RAM by bringing a MOSFET switch connected to one complementary data line where a dummy cell is provided into the off state at the required timing. CONSTITUTION:Common timing signals phi1 and phi2 are supplied to a gate of switch MOSFETs Q11 and Q13 and that of switch MOSFETs Q12 and Q14, both of which are provided in a space between a sensor amplifier SA and complementary data line DL and in that between the sensor amplifier SA and anti DL. After the level in accordance with a piece of information of a memory cell MC of the line DL and a dummy cell DC of the anti DL is transmitted to an input of the amplifier SA, either signal phi1 or phi2 goes to ''L'', and the FETs Q11- Q14 at the side of the cell DC are off. Thus, the line DL or anti DL at the cell DC side is separated, and the occurrence of a useless current for discharging the line DL or anti DL can be prevented. Accordingly a peak current value when all sensor amplifiers act simultaneously is reduced, and the power consumption of a dynamic RAM can be reduced.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a dynamic RAM (Random Access Memory). It's about technology.

[Background technology]

A memory cell MC in a dynamic RAM is composed of a storage capacitor Cs for storing information in the form of charges and a MOS FETQm for address selection. Then, the information of the logic "1", 10" is stored in the form of whether the capacitor Cs has a charge or not. To read the information, MOSFETQm is turned on and the capacitor Cs is connected to the common data line DL. Data cotton D
This is done by sensing how the potential of L changes depending on the amount of charge stored in the capacitor Cs. Since the memory cells MC are formed small and many memory cells are connected to a common data line DL to form a highly integrated and large capacity memory matrix, the capacitor Cs and the floating capacitance 1ico of the common data line DL are The relationship is such that the ratio of Cs/C,o becomes a very small value. Therefore, the change in the potential of the data line DL due to the amount of charge multiplied by M in the capacitor Cs becomes a very small signal. A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC
is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is half that of the capacitor C3 of the memory cell MC. In this way, since the capacitor Cd is set to have a capacitance value that is approximately half that of the capacitor Cs, it forms a reference voltage that is equal to half the read signal from the memory cell MC.

That is, the number of memory cells coupled to the pair of complementary data lines DL, DL is made equal to increase detection accuracy;
One dummy cell is coupled to each of complementary data lines 1)L and DL. In addressing the memory array, a pair of dummy word lines DWL are connected so that when a memory cell MC coupled to one of the complementary data lines DL, DL is selected, a dummy cell DC is always coupled to the other data line. , DWL is selected.

The sense amplifier amplifies the level difference between the two data lines and lowers the low level data line to the ground potential of the circuit. The inventor of the present invention has discovered that such sense amplifier operation generates wasteful current consumption. That is, the selected memory cell receives and accepts the high level or low level of the data line formed by the amplification operation of the sense amplifier, thereby recovering the stored information that has been destroyed by the addressing. It is. On the other hand, it is meaningless for the dummy cell side to receive or receive such an amplified data line level. This is because the capacitor of a dummy cell is always reset prior to its addressing.
-209397).

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM with low power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, after the reference voltage formed by the dummy cell is transmitted to the input terminal of the sense amplifier, the data line to which the dummy cell is connected is disconnected from the sense amplifier, thereby preventing the generation of wasteful current.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a dynamic RAM'.

In the example circuit shown in the figure, an N-channel MOSFE
I G F E T (1n5ulat
edGate Field Effect Tra
nslstor) will be explained as an example.

A 1-bit memory cell MC is represented by an information storage capacitor Cs and an address selection M
OSFETQm, and information of logic "1" and "0" is stored in the form of whether or not there is a charge in the capacitor CB.

To read information, MOSFET Qm is turned on and the capacitor Cs is connected to the common data line DI, so that the potential of the data III D L changes to the capacitor C! This is done by sensing what changes occur depending on the amount of charge accumulated in +.

Memory cells MC are formed small and a common data line D is formed.
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the capacitor Cs and
Regarding the relationship with the stray capacitance Go (not shown) of the common data line DL, the ratio of Cs/Co becomes a very small value. Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs is a very small signal.

A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC is
Except that the capacitance value of the capacitor Cd is y1 of the capacitor Cs of the memory cell MC,
It is made under the same manufacturing conditions and with the same design constants. Capacitor Cd is connected to the MOSFET prior to addressing.
It is reset by Qd'.

As described above, since the capacitor Cd is set to have a capacitance value that is approximately half that of the capacitor Cs, it forms a reference voltage that is equal to half the value of the read signal from the memory cell MC.

In the figure, SA is a sense amplifier that expands the difference in potential change caused by the addressing into a sensing period determined by a timing signal (sense amplifier control signal) φpaLφpa2 (its operation will be described later).

The sense amplifier SA of this embodiment is a switch MOSFET.
TQI 1. Its input/output nodes are coupled via Ql 2 to a pair of parallel complementary data lines DL, DL.

The number of memory cells coupled to complementary data lines L and DL are made equal to increase i output accuracy, and DL.

One dummy cell is coupled to each DL. Further, each memory cell MC is coupled between one word line W and one of the auspicious data lines. Since each word line WL crosses both data line pairs, word o
Even if the noise component generated in twt is transferred to the data line due to capacitive coupling, the noise component will be transferred to both data line pairs DL and DL.
appears equal to , and is canceled by the differential sense amplifier SA.

In the above 71 Lusosing, the complementary data line pair DL, D
When the memory cell MC coupled to the - side of L is selected, one of the pair of dummy word lines DWL and DWL is selected so that the dummy cell 1)C is always coupled to the other data line. .

The sense amplifier SA includes a pair of cross-wired MO5
FE, TQl, Q2 (Q9.QIO), and due to their positive feedback action, complementary data lines DL5. Differentially amplify minute signals appearing on the DL.

(The W feedback operation of MO3FIE 'I
' It starts at the same time that Q1 starts to conduct due to the relatively early timing signal φpal, and the higher data line potential is changed at a slow speed based on the potential difference applied to the complementary data lines DL and DL during addressing G. The lower one descends at a faster rate, with the difference widening. At this time, at the timing when the voltage difference becomes large to a certain extent, the MOSF has a relatively large conductance characteristic.
Since ETQB is made conductive by the timing signal φpa2, the lower data line potential rapidly decreases. By performing the operation of the sense amplifier SA in two stages in this way, the drop in the higher potential is prevented. In this way, when the lower potential drops below the threshold voltage of the cross-coupled M6SFET, the positive feedback operation ends, and the higher potential decreases and remains at a potential lower than the power supply voltage VCC and higher than the threshold voltage. f), the lower potential is ultimately the ground potential (OV)? , Niji J reaches.

During the above addressing, the memory axis of the memory cell MC, which is about to be destroyed, is recovered by receiving approximately 4% of the obtained high level or low level as is by each sensing operation. However, as mentioned above, the high level is the power supply voltage Vc
For c, if it falls more than a certain value, the reading of the part will be 0.
, while resharpening is repeated, a malfunction that is read as a logic "O" occurs. An active restore circuit is provided to prevent this malfunction (
(not shown). This active restore circuit has the ability to selectively bootstrap only high-level signals to the potential of power supply voltage Vcc.

In the same figure, the amplified output of the sense amplifier SA is connected to a common complementary data line pair CDL and δL via MOSFETs Q3 and Q4 forming a blank switch CW. Regarding the output signal of the sense amplifier SA shown as another representative, the similar MO data line pair CDL, CDL has the following:
It is connected to an input terminal of a data output buffer DOB including an output amplifier and an output terminal of a data input buffer sofa DIB.

Row decoder and column decoder R-D'CR and C-
DCI? receives an internal complementary address signal formed by address buffer ADB, forms one word line, dummy word line, and column switch selection signal to address memory cells and dummy cells. That is, in synchronization with the timing signal φar generated by the row address strobe signal RAS, external address signals AXO to AXi are taken into the address buffer ADB and transmitted to the row decoder R-DCH, and a predetermined word is selected by the word line selection timing signal φX. line and dummy word line selection operations. Then, a timing signal φac generated by a column address strobe signal CAS
←Synchronize with the external address signals AYO to AYt to the address buffer ADH and send them to the column decoders C, -D C
At the same time, the data line selection timing signal φy
The data line selection operation is performed by.

The timing control circuit TC receives address strobes (I', RAS, CAS, and write enable %WE) supplied from the outside, and outputs the address strobes (I') as shown in FIG.
Forms various timing signals in addition to timing signals.

These switch MOSFETs Q11 and Ql2 are provided between the sense amplifier SA and the complementary data lines DL and DI.
and Ql3. The gates of C^14 are supplied with a common timing (No. 8 φ1, φ2, and this timing No. 48 φ1 and φ2 are not particularly limited, but as will be described later, they become high level at the same time as the word line selection timing. , complementary data lines DL, D1... have a level according to the information of the memory cell NIC and dummy cell DC.
Since it is transmitted to the input of A, one of the timing signals φ1 or φ2 becomes low level and turns off the switch M O'SFET on the dummy cell side C side.

This prevents wasteful current consumption.

Hereinafter, the read operation of the memory cell MC will be explained according to the timing diagram shown in Figure @2.

Row address strobe signal RAS becomes low level.
z'c, the address signal AXO-AXl is taken into the address buffer yADB, and the row address decoder R-
This will be communicated to DCH. Then, in synchronization with the rise of the word line selection timing signal φX, the word line and the dummy word line are brought to a selected state of high L/bell. As a result, complementary data lines Dr, , DL are connected to memory cells M
A minute read level appears between the high level H or low level I of the memory cell MC according to the amount of charge between C and dummy cell DC and the h reference voltage (not shown by a broken line) formed by the dummy cell DC. This minute reading level is 1-word 13! The timing signal φ1. which becomes high level at vrJ time period with the selection timing. The switch MOSFETQI is turned on due to the high level of φ2.
It is transmitted to the sense amplifier SA via 1-Ql4.

Now, when the memory cell MC is connected to the data #IIDL side and the dummy cell DC is connected to the data line DL side by the word line selection operation, when the timing signal φpal becomes high level and the sense amplifier SA starts operating. ,
When the timing signal φ2 becomes low level, the switch MOSFET QI provided on the complementary data line DL to which the dummy cell DC is connected 2. Turn Ql 4 off. As a result, for example, the selected memory cell M
Even if the EtllJt signal of C is at a high level, the data line DL, which is at a low level, remains at the reference voltage despite the operation of the sense amplifier SA.

This makes it possible to prevent wasteful current consumption due to discharging the data line on the dummy cell side.

It should be noted that an active restore circuit (not shown) operates in response to the timing signal φrs and restores the dropped high level.

〔effect〕

(1) In the amplification operation of the frequency amplifier, by disconnecting the data line to which the dummy cell is connected, it is possible to prevent the occurrence of false tS that causes the data line to be discharged, thereby reducing power consumption. This has the effect of being able to.

(2) The CLL mentioned above can reduce the peak current value when the sense amplifiers operate all at once.
The noise generated in the electric power supply line is reduced.

This provides the effect of improving the operating margin.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, switch MO
The sense amplifier may be used for a pair of memory arrays by connecting the sense amplifier and the complementary data line through the SFET. That is, in FIG. 1, a similar memory array MARY is arranged on the right side with the sense amplifier SA in the center, and the sense amplifier SA is used for the two memory arrays MARY (even if they are shared, the upper and lower By doing this, in a dynamic RAM consisting of an appropriate number of memory arrays MARY, the number of sense amplifiers SA can be halved, and together with the effect described in (1), It is possible to significantly reduce power consumption per power.Furthermore, each circuit constituting the dynamic RAM can take various embodiments.

[Application field]

The present invention can be widely used in dynamic RAMs that store information in the form of charges.

Drawing 1! ? Brief explanation: Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 shows a block bar showing one embodiment of the present invention, and shows how the memory cells protrude! , 7 is a timing diagram for explaining the operation.

MC...Memory cell, DC...Dummy cell, CW...Column switch, SA...Sense amplifier, R-DCR...
Row decoder, C-DCR...column decoder, ADB
・・Address buffer, DOB・・Data signal buffer, DIB・・Data driver, TC・・Timing control circuit Fig. 1 A YO~Af/uottt
Dm Figure 2

Claims (1)

[Scope of Claims] 1. A pair of complementary data lines includes a pair of switch MOSFETs respectively provided on the complementary data lines, and a sense amplifier connected to the complementary data lines via the switch MOSFETs; The switch MOSFET provided on one data line where the dummy cell is selected is turned off at the timing when the reference voltage for identifying the storage information of the memory cell provided on the other data line is transmitted to the input terminal of the sense amplifier. A dynamic RAM that is characterized by a 2. The sense amplifier is characterized by comprising a pair of amplifying MOSFETs whose gates and drains are cross-connected, and a power switch MOSFET provided between the common source and the ground potential of the circuit. A dynamic RAM according to claim 1. 3. The dynamic RAM according to claim 1 or 2, wherein the operation start timing of the switch MOSFET is performed in synchronization with a word line selection operation. 4. The above sense amplifier has two memory arrays MARY
3. The dynamic RAM according to claim 1, wherein the dynamic RAM is selectively used for the following.