JPH0520833B2 - - Google Patents

Description

BACKGROUND OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to MOS type random access dynamic read/write memory.

Dynamic MOS memories have traditionally used bistable differential sense amplifiers whose inputs are connected to bit lines (column lines) divided into two halves. A dummy cell provides a reference voltage on the unselected half of the bit lines. This type of sense amplifier is known from U.S. Pat. No. 4,239,993 issued to Alexander White, Rao, U.S. Pat.
No. 3940747. All of these have been transferred to Texas Instruments.

Previously used differential sense amplifiers required a period of time during the cycle to equalize each half of the bit lines while precharging. This period is, for example, 50 nanoseconds, and this pressure equalization period is becoming an important factor when aiming at manufacturing high-speed devices.

A primary object of the present invention is to provide an improved sense amplifier for high speed random access read/write memories, particularly one transistor cell arrays. Another object is to provide a sense amplifier for use in a dynamic memory array that has short cycle times because the precharge time is shortened.

SUMMARY OF THE INVENTION In accordance with one embodiment of the present invention, a semiconductor memory device having an array of rows and columns of dynamic single transistor memory cells connects each column line rather than connecting to two halves of the column lines. A single-ended differential amplifier is used. A bistable circuit with cross-coupled drive transistors is connected on one side to the column line by a first coupling transistor. This coupling transistor turns off when the row line goes high, leaving a fixed reference voltage. Now,
The other side of the circuit is connected to the column line by a second coupling transistor. This coupling transistor turns on after the column line is stable. This column line voltage is related to whether a 1 or a 0 is being stored. The time required to precharge the column line is short. This is shortened because the two halves of the column lines do not need to be precharged from different levels, and therefore the memory cycle time is also shortened. The device is also less sensitive to alpha particle errors since changes in bit line voltage affect both sense amplifier inputs equally.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS Referring to FIG. 1, a single-ended sense amplifier circuit for a dynamic memory according to the present invention is illustrated. This memory device is of the type described in U.S. Pat. No. 4,239,993, except that the bit line is not divided into two halves. One transistor dynamic memory cell 1
The array of zeros is formed on a semiconductor chip, for example in a 256K or 1 megabit configuration. each cell 1
0 has a storage capacitor element 11 and an access transistor 12. all transistors 1 in a row
2 is connected to the row line 13 and the drains of all transistors in the column are connected to the column line 14. A 256K device typically has 512 row lines 13 and
It has 512 column lines 14, and the device is divided into blocks, so that on a certain column line, for example,
It has only 128 cells, so that the ratio between the cell capacity 11 and the bit line 14 capacity is within an acceptable range.

The sense amplifier consists of two cross-coupled drive transistors 15 connecting a pair of sense nodes 16 and 17 to a ground node 18. Nodes 16 and 17 are connected to bit line 14 by two separate coupling transistors 20 and 21 having clock voltages φs and φt on their gates, respectively. Transistor 20 serves to set a reference voltage on sense node 16 (similar to a dummy cell in a conventional sense amplifier), and transistor 21 serves to connect the sensed cell to another sense node 17. As shown in the timing table of FIG. 2, the clock φs drops in voltage before (or at the same time as) the selected Xw voltage on one of the row lines 13 goes high, causing the reference voltage on node 16 to drop. Insulate. Then, the selected cell capacitor element 1
After a 1 causes the voltage on the bit line to drop (or no voltage drop, depending on whether a 1 or a 0 is stored), the clock φt drops the voltage sensed at node 17 to another. Insulate from

Each bit line 14 has a clock φpc at the gate.
is precharged by the transistor 24 to which the voltage is applied. This precharge clock φpc is at a high potential during the precharge cycle, and then the potential of the bit line 14 is held at the precharge level of approximately Vdd before φs or The voltage will drop. Normally, the voltage of the precharge clock is reduced by receiving a chip enable clock from outside the chip.
For devices with multiplex addresses,
A row address strobe voltage initiates a read cycle. followed by column address strobe
CAS follows. Therefore, the diagram in FIG. 2 corresponds to that in a multiplex device.

Ground node 18 is connected to ground through a transistor 25 receiving gate clock voltage φ1. As can be seen from FIG. 2, approximately the time that φt is at a high potential, the clock φt is at a high potential, causing the cross-coupled drive transistor to initiate a latching operation. Transistor 25 is shared with all sense amplifiers on the chip. Also, instead of using a single grounded transistor, U.S. Pat.
Two or three transistors, which turn on with a small delay time, may be used as described in the above.

The active pulldown circuit described in U.S. Pat. Nos. 4,239,993 and 4,081,701
6 and 17. These circuits have a load transistor 27 at its gate that receives the boost block φb. Trapped voltage on gate
A shunt transistor 28 with Vtr connects the gate of transistor 27 to node 16 or 17. During precharge, the trap voltage Vtr is Vdd
is maintained at Vdd, and then when the voltage of φpc decreases, Vdd
as it drops to approximately one or two thresholds below.
The Vdd voltage remains trapped on transistor 27 and forms capacitive element 29. The voltage on one of nodes 16 or 17 drops to zero after φ1 goes high. Transistor 2 on the same side
8 is turned on, the gate of this transistor 27 is discharged, and the gate capacitance element 29 on this side has a condition of zero capacitance. Therefore, when the clock φb becomes a high potential, the capacitive element 29 is placed on the side where the potential becomes zero.
is not formed and the gate of transistor 27 on that side is shunted to its source by transistor 28, so that transistor 27 on this side
is never turned on. On the other side, transistor 28 is off and the φb voltage pulls the gate of transistor 27 to a potential above Vdd, pulling node 16 or 17 all the way to the Vdd level. If node 17 remains at a high potential, there will be a full
Vdd can be provided. When node 17 goes low, the zero is refreshed.

The output from the sense amplifier for read operations (or input for write operations) passes through a pair of transistors 30, each having φy applied to its gate.

This Y selection voltage φy is connected from the Y decoder, and connects the selected column to an I/O buffer for connection with the outside of the chip. In a read operation, clock φy goes high sometime after φ1 goes high, as shown in FIG.

Transistors 20 and 21 are connected to sense node 1
In order to keep 6 and 17 physically and electrically balanced, they each have transistors 20a and 21a connected in parallel. Similar to the transistor 20, φs is applied to the gate of the transistor 20a, but the gate of the transistor 21a is connected to ground. The apparent capacity on node 16 is greater than the capacity on node 17. This decouples more charge from node 16 than from node 17,
Generate a reference offset voltage (as is conventionally done with a dummy cell that is half the size of the capacitive cell). Transistors 20, 20a, 21, 21
All a's have the same physical size. When φs goes low, the negative going offset reduces the voltage on node 16 by a predetermined amount, for example 200 milvolts, but when φt goes low, only one transistor experiences a negative voltage change. connected, thereby reducing the voltage on node 17 by half of the above amount. But node 17
In addition to the effects described above, an offset appears depending on the storage capacitor selected.
As a result, if 0 is stored after φt,
Although the voltage at node 17 is lower than that at node 16,
If 1 is stored, node 17 will have a higher voltage than node 16. The latch formed by transistor 15 therefore flips after φ1 goes high.

FIG. 2 shows the voltages on bit line 14 and sensor nodes 16, 17 during the active cycle for the 1 stored state and the 0 stored state. Precharge clock φpc, word line voltage
Since Xw and the clocks φs and φt are boosted to a level higher than Vdd (indicated here by Vdd), the Vdd level appears completely at all nodes.

A feature of the invention is the operation during the precharge portion of the cycle. As shown in Figure 2, when the active cycle is completed and φpc goes to a high potential, the bit line 14 immediately goes back to Vdd (or Vdd - Vt).
The problem of equalizing the pressures of two separate bit wire halves that have been precharged up to 50% is eliminated. In the past, long hours were used to ensure that half the bit lines (one half being 1 and the other being 0) had exactly the same voltage. Since the halved bit wire set has a relatively large capacity, it takes a longer time to equalize the pressure. On the other hand, when the bit line 14 in the present invention is 0,
There is a slightly lower voltage than in case 1, but this is not a significant issue as both sense amplifiers are equally affected.

Naturally, nodes 16 and 17 must be pressure equalized, but since they have very small capacitances, such pressure equalization can be accomplished quickly. Transistor 31 is used to equalize the voltages at nodes 16 and 17 during φpc. After a short delay period, the next cycle is started by dropping the voltages on φpc and φs, so that the cycle time of the memory device is no longer incrementally longer than the actual access time, but is shortened.

Another important feature of the invention is that it is relatively robust to errors caused by alpha particles.
When alpha particles collide with a silicon chip, this instantly creates a small electrically conductive area. The operation of the cell or bit line is disturbed by a change in amount comparable to the change in the voltage of the data bit or bit line in which it is stored. In conventional dynamic RAM circuits where the bit lines are split in half, the alpha particles will therefore create a differential voltage at the input of the sense amplifier and possibly an error output. However, in the circuit of the invention, a change in the amount of charge on the bit line 14 caused by an alpha particle affects both inputs 16 and 17 connected to the sense amplifier equally and therefore cannot cause an error. do not have.

As described above, by using unbalanced-terminated differential sense amplifiers that are connected to all row and column lines instead of halving them, the period for voltage equalization can be shortened, and alpha particles can be reduced. It is possible to provide dynamic RAM memory that is not affected by

Although the invention has been described with reference to specific embodiments, this description is not intended to be limiting. Various modifications of the embodiments shown, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. It is therefore intended that the appended claims cover any such variations and modifications that fall within the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is an electrical schematic diagram of a portion of a memory array illustrating the sense amplifier circuit of the present invention. Second
The figure is a graph showing the voltages present in various parts of the circuit of FIG. 1 versus time. 10...Access transistor, 13...Row line, 14...Column line, 15...702 coupled drive transistor, 16, 17...Sense node, 18
...Ground node, 20, 21...Coupling transistor, 24...Precharge transistor.

Claims (1)

[Scope of Claims] 1: a column line selectively connected to a memory cell at a first time; a differential sense circuit having first and second inputs; and a differential sense circuit having the first and second inputs separately. first and second connection means for connecting the first input to the column line before the first time; energizing the first connection means to connect the first input to the column line before the first time; a first timing means for isolating said first input from said column line for a time of one time, thereby setting a reference voltage on said first input; and a period of time commencing before said first time. second timing means for energizing said second connection means to connect said second input to said column line during said second time period, said second timing means for energizing said second connection means to connect said second input to said column line at a second time after said first time; a second timing for deenergizing said second connection means to isolate an input of said column line from said column line, thereby setting a voltage on said second input in relation to the contents of a selected memory cell; A semiconductor memory circuit having means. 2. After a delay time after said second time said timing means connects said second input to said column line thereby refreshing said selected memory cell. circuit. 3. The circuit according to claim 1, wherein the memory cell in the circuit is a dynamic one-transistor cell having a storage capacitor element. 4. The circuit of claim 1, wherein the sense circuit is a bistable cross-coupled sense amplifier.