JP2508505B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device such as a so-called DRAM (Dynamic RAM) for reading and writing an information signal in a cell capacity of a memory cell.

B. SUMMARY OF THE INVENTION The present invention is a semiconductor memory device such as a so-called DRAM for reading and writing an information signal with respect to the cell capacity of a memory cell, and uses a single bit line from which the information signal of the memory cell is read. The voltage when the reference voltage is applied to the bit line and the reset state is sampled and held, and the sampled and held reference voltage and the voltage based on the information signal read from the memory cell to the bit line are compared with each other. By performing the sensing by performing the sensing, it is possible to increase the sensitivity of the sensing and increase the storage capacity by reducing the cell capacity.

C. Conventional Technology In general, so-called DRAM, etc., in which memory cells each having a cell capacitance and a switching transistor are arranged, and the information signal stored in the cell capacitance is read and written through a bit line based on a selection signal of a word line. The semiconductor memory device uses a so-called sense amplifier that detects and amplifies a minute potential difference due to charges from the cell volume at the time of reading the information signal.

FIG. 4 shows an essential part of an example of a semiconductor memory device using such a sense amplifier. Each memory cell MC shown by a broken line in the drawing is provided with a cell capacitance Cs and a switching transistor Ts. In the configuration of FIG. 4, when reading the stored contents of each cell, first, the transistors Tp 1 and Tp 2 are turned on by the precharge pulse φ _P , and the bit lines BL 1 and BL 2 are both set to the reference potential V _ref , for example. It becomes V _cc / 2. Next, in order to read one of the pair of cells MC 1 and MC 2, for example, cell MC 1, word line WL 1
Is selected and the cell capacitance Cs 1
The information signal stored in the bit line BL 1 is read out to the bit line BL 1.
If the potential of the bit line BL 1 changes by ± ΔVs with respect to the reference potential V _CC / 2 in accordance with the information signal stored in the cell capacitance Cs 1, and becomes, for example, V _CC / 2-ΔVs, the transistor Tr 2 Also has a gate potential of V _CC / 2−ΔVs. On the other hand, since the potential of the bit line BL 2 and the gate potential of the transistor Tr 1 remain the above-mentioned reference potential V _CC / 2, when the signal T _q is turned on by the signal φ _q , the transistors Tr 1 and Tr 1 are turned on. Amplification by 2 is started, and as this amplification progresses, the transistor Tr 1 is turned on and the transistor Tr 2 is almost turned off. As a result, the information signal stored in the cell capacitor CS 1 is read.

In addition, a dummy cell is used to provide the reference voltage V _CC /
A configuration for supplying 2 is also known, and in this case, a dummy cell and a gate transistor are connected for each bit line.

D. Problems to be Solved by the Invention By the way, in such a conventional semiconductor memory device, the variation in each threshold value V _th of the transistor pair for amplification Tr 1 and Tr 2 is generally about 10 mV, and Bit line BL
In addition to the sensitivity variation of about 10 mV due to the variation in capacitance of 1 and BL 2, sensitivity degradation of about 20 mV has occurred. Also, two bit lines are required for one sense amplifier, which is a layout constraint. Further, the structure using the dummy cells becomes complicated.

The present invention has been made in view of such conventional circumstances, and is a semiconductor capable of realizing a highly sensitive sensor circuit, thereby reducing the cell capacity and increasing the integration degree to increase the storage capacity. An object is to provide a memory device.

E. Means for Solving the Problems In order to solve the above-mentioned problems, the semiconductor memory device of the present invention is provided with memory cells each having a cell capacitance and a switching transistor, and a memory cell having a word line selection signal is provided. In a semiconductor memory device for reading an information signal stored in the cell capacitance through a bit line based on a reference applied to a single bit line from which the information signal of the memory cell is read through a switching transistor for precharge. An information signal read from the cell capacitance to the bit line based on the held reference potential and the word line selection signal based on the held reference potential and a reference potential that is approximately midway between the positive and negative power supplies based on the voltage. It is characterized by comprising a sense circuit for comparing the electric potential based on That.

F. The potential obtained when the information signal of the working memory cell is read out to a single bit line is the potential between the positive and negative power supplies that appears at the bit line by applying the reference voltage before this read out. By comparing and amplifying with the held reference potential, it is possible to stabilize the sensing and increase the sensitivity, and to reduce the cell capacity and expand the storage capacity.

G. Embodiment FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. The example of FIG. 1 shows the configuration of a DRAM such as a so-called video memory which is premised on inputting / outputting data in line units.

In FIG. 1, memory cells MC each having a cell capacitance Cs and a switching transistor Ts are arranged in a two-dimensional matrix of, for example, m rows and n columns (m and n are natural numbers) corresponding to two-dimensional image information. , Any position in the figure,
For example, the memory cell MC _{ij at} the position of the i-th row and the j-th column, the cell capacitance Cs _ij , and the switching transistor are represented as Ts _ij . Any row of these memory cells MC, for example the i-th
The word line W is connected to each gate of the transistors Ts _{il to} Ts _in of the row.
Li is commonly connected, and the bit line BL j is commonly connected to each of the transistors Ts _{lj to} Ts _mj in an arbitrary column, for example, the j-th column. A reference voltage, for example, V _CC / 2, is supplied to these bit lines BL 1 to BL n via switching transistors Tp 1 to Tpn for precharging, respectively. Signals appearing at ~ BL n are output gate switching transistors To 1 ~ To n, respectively.
To the sense circuits SA 1 to SA n. The respective outputs from these sense circuits SA 1 to SA n are sent to the 1-line buffer memory 11 and taken out.

Here, the arbitrary sensor circuit SA j samples and holds the potential based on the reference voltage (for example, V _CC / 2) applied to the corresponding bit line BL j as the reference potential V _ref ,
This held reference potential V _ref and any word line,
For example, a voltage V _sig which is based on the information signal read from the cell capacitance Cs _ij of the memory cell MC _ij to the bit lines BL j and compared with one another in response to the selection signal WL i, the cell MC _ij information signal Is output.

The one-line buffer memory 11 shows an example of a configuration in which data for one line (one horizontal period) is read all at once during a horizontal blanking period (H blanking period) of a video signal. A configuration may be used in which one reading is performed for each of the bit lines BL 1 to BL n. In this case, instead of the buffer memory 1, an H output decoder for outputting a selection signal for sequentially selecting each bit line BL 1 to BL n is provided, and the switching transistors To 1 to Ton for the output gate are provided. Instead of the above, switching switching transistors for output selection are provided respectively, and these output selection transistors are sequentially turned on by a selection signal from the H output decoder to appear on each bit line BL 1 to BL n. Information is read sequentially. However, in consideration of the fact that the read cycle of one bit line is long, it is necessary to pipeline the read control operation.

Next, as the configuration on the data input (write) side, the input buffer 12, the H input decoder 13 and the above bit lines BL 1
To BL n, n switching transistors T _IH 1 to T _IH n for input selection are provided, and the H input decoder 13
, By selectively turns on transistor T _IH 1~T _IH n, the input signal D _IN input via an input buffer 12
Select the bit lines BL 1 to BL n to be supplied.

The configuration of the input side may be configured by using a one-line buffer memory as in the case of the output side in the figure. In this case, switching for input gates provided for each bit BL 1 to BL n Connect each gate of the transistors in common,
The input gate control signal φ _IG may be commonly provided to each input gate transistor.

Next, the operation of the circuit having the above configuration will be described with reference to FIGS. 2 and 3.

FIG. 2 shows the operation at the time of reading information. In FIG. 2, first, the precharge gate pulse φ _PG is supplied to the transistors Tp 1 to Tpn, so that the reference voltage (for example, V _CC / 2) is applied to the bit lines BL 1 to BL n. It Potential appearing on each bit line BL 1 to BL n at this time
V _ref is detected by each of the sense circuits SA 1 to SA n according to the first sample hold pulse φ _SHI , and the detected potential V _ref is held as a reference potential or a determination level for reading information.

Next, for example, the word line selection pulse φ _wi is changed to the word line WL i.
Is supplied to each memory cell MC _il of the i-th row.
Transistor Ts _il ~Ts _in the MC _in is turned on, each cell capacity Cs
_The information signals accumulated in _{il to} Cs _in are read out to the corresponding bit lines BL 1 to BL n. In accordance with these information signals, the potential of each bit line BL 1 to BL n becomes the above reference potential V _ref.
The potential V _sig changes by ± ΔVs. Next, the potentials V _sig of the bit lines BL 1 to BL n are detected by the sense circuits SA 1 to SA n in response to the second sample hold pulse φ _SH2 , and sampled and held in advance. The potential differences are respectively amplified by comparing with the reference potential V _ref . As this amplification progresses, each bit line BL 1 to BL n
The word line selection pulse φ _wi is again supplied to the word line WL i at the timing when the potential of the memory cells MC _{il to} MC
Restores (rewrites) the information signal for the cell capacity Cs _{il to} Cs _in of _in . While these read operations are being performed, the switching transistors To 1 to Ton for each output gate are turned on by the output gate pulse φ _OG .

Here, the word line WL i generated by the word line selection pulse φ _wi
The selection operation is performed twice, that is, immediately after the first sample hold and immediately after the second sample hold, and the information signal is read from each cell by the previous operation. Information is restored to each cell by the operation of. The first and second sample hold operations are
In both cases, the word line selection operation by the word line selection pulse φ _wi is performed under the same condition of OFF state.

Next, since the operation at the time of writing information is the same as the conventional one, a brief description will be given with reference to FIG.

During information writing, while the word line WL i of any one is selected, the input selection switching transistors by the bit line selection pulse phi _IH1 to [phi] _Ihn from H-decoder 13 T _IH 1~T _IH n Are sequentially turned on, and the input signal D _IN input via the input buffer 12 is supplied to each bit line BL 1 to BL n via the turned-on transistors T _IH 1 to T _IH n, respectively, Corresponding memory cell MC _il ~
Writing of the cell capacitance Cs _il to CS _in the information signal with respect to the MC _in are sequentially performed. As described above, one line by using a buffer memory, for example, the one line information H blanking period or the like may be written simultaneously to the memory cells MC _il to MC _in.

According to the semiconductor memory device of the embodiment of the present invention as described above, since the sense circuit SA samples and holds the potential appearing on a single bit line and compares the potentials, the sense circuit SA is different from the conventional one using two bit lines. Therefore, there is no limitation on sensitivity deterioration due to variations in bit line capacitance or variations in threshold values V th of the transistor pairs of the sense amplifier. Also, since the number of bit lines is halved, it is possible to arrange a so-called open bit line type when forming elements on a semiconductor substrate.
It can contribute to high density and large storage capacity.

Here, the detection sensitivity of the sample-hold type comparator as in the above embodiment is as high as several mV, and the capacitive thermal noise at the time of reading from the memory cell to the bit line is
When the memory cell capacity is Cs and the bit line capacity is C _B , It is about 1mV or less. Regarding the potential variation of the bit line due to the capacitive coupling between the word line and the bit line, considering that there is generally about 1% capacitive coupling of the bit line, the second sample hold pulse φ
_{SH2 is performed} after the word line selection pulse φ _wi is turned off. That is, the reference potential V _ref and the information signal potential
The first and second sample-hold operations for detecting and holding V _sig are both performed under the condition that the word line selection pulse φ _wi is equal to the OFF state, and therefore variations occur. It is extremely low, has an advantage over noise, and can increase sensitivity. Furthermore, noise does not really matter for abrupt power fluctuations.
Since it takes about 200ns per 1H (about 63μs), it can be solved easily by paying attention to the system or adding a decap.

The present invention is not limited to the above-described embodiment, and for example, the word line selection pulse φ _wi
The selection operation of WL i is performed twice, that is, immediately after the first sample and hold and immediately after the second sample and hold. The line selection operation may be combined.

H. Effect of the Invention According to the semiconductor memory device of the present invention, the signal detection sensor circuit for reading the information signal stored in the memory cell can be highly sensitive and can be operated stably, and the bit line It is possible to reduce the cell area, increase the degree of integration, and facilitate the realization of a memory having a large storage capacity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining a read operation, FIG. 3 is a time chart for explaining a write operation, and FIG. FIG. 1 is a circuit diagram schematically showing an example of a conventional semiconductor memory device. 11 …… 1 line buffer memory 12 …… H input decoder 13 …… input buffer MC …… memory cell Ts …… switching transistor Cs …… cell capacity WL …… word line BL …… bit line SA …… sense circuit φ _SH1 …… 1st sample hold pulse φ _SH2 …… 2nd sample hold pulse

Claims (1)

(57) [Claims] 1. A semiconductor memory device in which memory cells each having a cell capacitance and a switching transistor are provided, and an information signal accumulated in the cell capacitance is read through a bit line in accordance with a selection signal of a word line. It has a switching transistor for precharging connected to a single bit line from which the information signal of the memory cell is read out and a sense circuit, and a reference voltage of a potential approximately midway between the positive and negative power supplies via the switching transistor for precharging. Is applied to the single bit line, the sense circuit samples and holds the potential based on the reference voltage applied to the single bit line as a reference potential, and the held reference potential and the word line Potential based on the information signal read from the cell capacitance to the bit line according to the selection signal of The compared with each other, the semiconductor memory device and outputs the information signal of the cell.