JP3243828B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a transfer gate switch control signal for controlling connection between a sense amplifier shared by a plurality of memory blocks in a semiconductor memory device and bit lines from the plurality of memory blocks. In particular, the present invention relates to a semiconductor integrated circuit that reduces a charge / discharge amount of a load connected to a switch control signal and reduces power consumption.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a circuit configuration of a conventional semiconductor integrated circuit, and FIG. 6 shows an operation timing chart of the conventional semiconductor integrated circuit shown in FIG.

In FIG. 5, BLK1 and BLK2 are memory block selection signals. VPP is a power supplied from outside the memory element or supplied by a power generation circuit (not shown) inside the memory element, and is higher than an internal power supply potential VCC for writing a High level to a memory cell (not shown). Also have a high potential. 200,201
Are the memory block selection signals BLK2 and BLK1, respectively.
And the internal power supply potential VCC using VPP as a power supply.
This is a level shift circuit that converts a level input to a VPP level and outputs the result. 202 and 203 are P-channel transistors whose gates are connected to the outputs of the level shift circuits 200 and 201, respectively, and whose sources are connected to the power supply VPP. Reference numerals 204 and 205 denote N-channel transistors whose gates are connected to the outputs of the level shift circuits 200 and 201, respectively, and whose sources are grounded. The drain of the P-channel transistor 202 and the drain of the N-channel transistor 204 are connected to generate a switch control signal SW1. Also, a P-channel transistor 2
03 and the drain of the N-channel transistor 205 are connected to generate a switch control signal SW2. 220 and 221 are memory blocks. 222 is a sense amplifier. BL1, XBL1, BL2, XBL
Reference numeral 2 denotes a bit line connected to a memory cell (not shown) in the memory blocks 220 and 221. 210,21
Reference numeral 1 denotes an N-channel transistor having a gate connected to the switch control signal SW1, a source connected to the bit lines BL1 and XBL1, and a drain connected to the sense amplifier 222, respectively. 212 and 213 are N-channel transistors each having a gate connected to the switch control signal SW2, a source connected to the bit lines BL2 and XBL2, and a drain connected to the sense amplifier 222, respectively. The memory block selection signals BLK1 and BLK2 are signals that are activated when memory cells in the adjacent memory blocks 220 and 221 are accessed with the sense amplifier 222 interposed therebetween.

The operation of the conventional semiconductor integrated circuit configured as described above will be described below with reference to FIG. First, at the time of standby, as shown in FIGS. 6A and 6B, the memory block selection signals BLK1 and BLK2 are both at the ground level. The outputs of the level shift circuits 200 and 201 are both at the ground level, the P-channel transistors 202 and 203 are turned on, the N-channel transistors 204 and 205 are turned off, and the switch control is performed as shown in FIGS. Signals SW1 and SW2 are both held at the VPP level. As a result, the N-channel transistors 210, 211, 212, and 213 are turned on, and FIG.
As shown in (f), bit lines BL1, XBL1, BL2,
XBL2 is precharged to 1/2 VCC level by a bit line precharge circuit (not shown).

Next, when a memory cell in the memory block 220 is accessed, as shown by a solid line in FIG. 6A, the memory block selection signal BLK1 transitions to the VCC level, and the output of the level shift circuit 201 becomes To the VPP level, the P-channel transistor 203 is turned off, and N
When the channel transistor 205 is turned on, FIG.
, The switch control signal SW2 transitions to the ground level. At this time, as shown by the solid line in FIG.
The switch control signal SW1 is kept at the VPP level. Therefore, the N-channel transistor 210,
211 is on and the N-channel transistor 21
2 and 213 are turned off, and the sense amplifier 222 is applied to the memory block 220 having the accessed memory cell.
, The bit lines BL2 and XBL2 connected to the memory block 221 on the opposite side are separated from the sense amplifier 222. The sense amplifier 222 is connected to the bit line BL
1, the potential difference appearing in XBL1 is amplified, but the VPP level of the switch control signal SW1 is different from the VCC level by the N-channel transistors 210, 211, 212, 2
13 is set to a higher potential than the threshold potential,
As shown by the solid lines in FIG. 6 (e), the bit lines BL1, XBL
1 is amplified to the VCC level and the ground level, and the VCC level can be written to the memory cell.

Next, when the access to the memory cell in the memory block 220 is completed, the memory block selection signal BLK1 transitions to the ground level as shown by the solid line in FIG. At the ground level, and the switch control signal SW2 transitions to the VPP level as shown by the solid line in FIG. FIG. 6 (e)
As shown by the solid line, the bit lines BL1 and XBL1 are precharged to the 1/2 VCC level by the bit line precharge circuit.

Conversely, when a memory cell in the memory block 221 is accessed, as shown by a broken line in FIG. 6B, the memory block selection signal BLK2 transitions to the VCC level, and the output of the level shift circuit 200 changes. VPP level, the P-channel transistor 202 is turned off,
When the channel transistor 204 is turned on, FIG.
As shown by the broken line, the switch control signal SW1 transitions to the ground level. At this time, as shown by the broken line in FIG.
The switch control signal SW2 is kept at the VPP level. Therefore, the N-channel transistor 212,
213 is on and the N-channel transistor 21
0 and 211 are turned off, and the sense amplifier 222 is turned on the memory block 221 having the accessed memory cell.
, The bit lines BL1 and XBL1 connected to the memory block 220 on the opposite side are separated from the sense amplifier 222. The sense amplifier 222 amplifies the potential difference appearing on the bit lines BL2, XBL2 to the VCC level and the ground level, as shown by the broken line in FIG.

Next, when the access to the memory cells in the memory block 221 is completed, the memory block selection signal BLK2 is grounded as shown by the broken line in FIG. 6F and by the broken line in FIG. 6B. Level, the output of the level shift circuit 200 becomes the ground level, and the switch control signal SW1 changes to the VPP level as shown by the broken line in FIG. As shown by the broken line in FIG. 6F, the bit lines BL2 and XBL2 are precharged to the 1/2 VCC level by the bit line precharge circuit.

[0009]

However, in the above-described configuration, when a memory cell is accessed, the bit line of the memory block having the accessed memory cell is separated from the other memory block with a sense amplifier interposed therebetween. For this reason, one of the switch control signals is changed from the VPP level to the ground level, and in the standby state, the signal is again changed from the ground level to the VPP level. As a result, the load on the VPP level generating circuit increases, and the power consumption increases. Had problems.

In view of the foregoing, it is an object of the present invention to provide a semiconductor integrated circuit that reduces power consumption.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a first switch control signal and a bit line in a first memory block. Are connected by a first transistor input to a gate, and a bit line in a second memory block is connected to the sense amplifier by a second transistor input to a gate of a second switch control signal. The switch control signal generating means for generating the first switch control signal and the second switch control signal has a source connected to the first voltage.
Connected to a first power supply for supplying the
A first memory block or the second memory block
The first is generated based on a block selection signal for selecting
And the drain is the first switch
A third node connected to the first node from which the control signal is output;
A transistor and a source connected to the first power supply;
The first internal signal is input to the gate, and the drain is
The second node to which the second switch control signal is output is
A fourth transistor connected to the first transistor and a source connected to the first transistor;
Providing a second voltage level higher than the voltage level;
And the gate is connected to the gate based on the block selection signal.
And a second internal signal generated by the
Is a fifth transistor connected to the first node
And a third power source whose source is lower than the first voltage level.
Connected to a third power supply that supplies the
A third internal signal generated based on the block selection signal.
And the drain is connected to the first node.
And a source connected to the second power supply.
Generated at the gate based on the block select signal
Is input, and the drain is connected to the second internal signal.
The seventh transistor connected to the node of
The block is connected to the third power supply and the gate is selected.
A fifth internal signal generated based on the signal is input;
An eighth transistor having a drain connected to the second node;
And a first transistor when the bit line is precharged.
A switch control signal and the second switch control signal.
At the first voltage level to access the memory cell.
Sometimes, the first switch responds to the block selection signal.
Switch control signal and the second switch control signal.
One of them is shifted to the second voltage level, and the other is shifted to the second voltage level.
A transition to the third voltage level is provided.

According to a second aspect of the present invention, in the semiconductor integrated circuit, the source and the drain are connected to the first node and the second node, respectively, and a gate is provided based on the block selection signal. sixth generated Te
Is added with a ninth transistor to which the internal signal is input. According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect , when the memory cell access is completed, the fifth transistor and the sixth transistor are connected to each other .
After the transistor, the seventh transistor, and the eighth transistor are turned off, the ninth transistor is turned on, and the first node and the second node are connected via the ninth transistor. To conduct, the first
And the second node are short-circuited via the ninth transistor, and then the third transistor and the fourth transistor are turned on, and
And the second node are charged to the first voltage level. A semiconductor integrated circuit according to a fourth aspect of the present invention is the semiconductor integrated circuit according to the first aspect,
The third power supply is a power supply of a ground potential, and the second power supply is generated by an internal power supply generation circuit.

[0013]

According to the present invention, there is provided the present invention
When the bit line is precharged to a voltage level lower than the first voltage level, first and second switch controls input to the gates of first and second transistors connecting the bit line and the sense amplifier The signals are both at the first voltage level and the first and second transistors are both conducting. Also, when the memory cell is accessed, one of the first and second switch control signals, that is, the gate voltage of one of the transistors, transitions to a second voltage level higher than the first voltage level. Then, the voltage level amplified to the first voltage level by the sense amplifier is written to the memory cell of the selected block at the same voltage level via the transistor and the bit line. Furthermore, since the voltage levels of the first and second switch control signals at the time of precharging are the first voltage levels lower than the second voltage level, the signal load charging amount at the time of precharging is reduced. can do. Further, at the time of precharging, electric charges are supplied from the power supply at the first voltage level, so that the load on the power supply at the higher second voltage level can be reduced.

According to the third aspect, after the memory cell access is completed, the fifth, sixth, seventh, and eighth transistors are turned off, the ninth transistor is turned on, and the ninth transistor is turned on. The first and second switch control signals are equalized, and the amount of signal load charging at the time of precharge can be reduced.

[0015]

(Embodiment 1) A semiconductor integrated circuit according to a first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows an example of a circuit configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is an operation timing chart of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. Show.

In FIG. 1, BLK1 and BLK2 are memory block selection signals. VPP is a power supplied from outside the memory element or supplied by a power generation circuit (not shown) inside the memory element, and is higher than an internal power supply potential VCC for writing a High level to a memory cell (not shown). Also have a high potential. 100 is a two-input OR gate for inputting the memory block selection signals BLK1 and BLK2, 101 is connected to the output of the two-input OR gate 100, and is a delay element for delaying signal propagation.
This is a two-input NOR gate that inputs the output of the input OR gate 100 and the output of the delay element 101. A two-input AND gate 103 receives the memory block selection signal BLK1 and the output of the two-input NOR gate 102, and a two-input AND gate 104 receives the memory block selection signal BLK2 and the output of the two-input NOR gate 102. 105 and 106 are 2-input AND gates 10
Drivers 107 and 108 input the outputs of 3, 104, and inverters 107 and 108 input the outputs of the two-input AND gates 103 and 104, respectively. Reference numerals 109 and 110 denote level shift circuits which receive the output of the inverter 107 and the output of the inverter 108, convert the input of the internal power supply potential VCC level to the VPP level using VPP as a power supply, and output the same. A level shift circuit 111 receives the output of the two-input NOR gate 102, converts the input of the internal power supply potential VCC level to the VPP level using VPP as a power supply, and outputs a precharge control signal PRE. 112,
113 is a level shift circuit 109, 1
It is a P-channel transistor connected to the output of No. 10 and having a source connected to the power supply VPP. Reference numerals 114 and 115 denote N-channel transistors whose gates are connected to the outputs of the drivers 106 and 105, respectively, and whose sources are grounded. Drain of P-channel transistor 112 and N
The drain of the channel transistor 114 is connected,
A switch control signal SW1 is generated. The drain of the P-channel transistor 113 and the drain of the N-channel transistor 115 are connected to generate a switch control signal SW2. Reference numerals 116 and 117 denote N-channel transistors each having a drain connected to the switch control signal SW1 and the switch control signal SW2, a source connected to the internal power supply potential VCC, and a gate connected to the precharge control signal PRE. 130 and 131 are memory blocks. 132 is a sense amplifier. BL1,
XBL1 is a bit line connected to a memory cell (not shown) in the memory block 130. BL2, XBL2
Is a bit line connected to a memory cell (not shown) in the memory block 131. Reference numerals 120 and 121 denote N-channel transistors each having a gate connected to the switch control signal SW1, a source connected to the bit lines BL1 and XBL1, and a drain connected to the sense amplifier 132, respectively. 122 and 123 are switch control signals S
W2 and the sources are bit lines BL2, X, respectively.
An N-channel transistor connected to BL2 and having a drain connected to the sense amplifier 132. The memory block selection signals BLK1, BLK2 are respectively connected to the memory blocks 130,
This signal is activated when a memory cell in the memory 131 is accessed.

The operation of the semiconductor integrated circuit according to the first embodiment of the present invention constructed as described above will now be described with reference to FIG.
This will be described with reference to FIG.

First, during standby, as shown in FIGS. 2A and 2B, memory block selection signals BLK1, BLK2
Are ground levels. Therefore, the outputs of the two-input AND gates 103 and 104 become the ground level, and the two-input OR gate
The output of gate 100 is at the ground level, the output of delay element 101 is at the ground level, and the output of 2-input NOR gate 102 is at the VCC level which is the internal power supply potential. The outputs of the drivers 105 and 106 are at the ground level,
The output of 108 becomes the VCC level, and the outputs of the level shift circuits 109 and 110 become the VPP level. Further, as shown in FIG. 2C, the precharge control signal PRE, which is the output of 111, is at the VPP level. Therefore, the P-channel transistors 112 and 113 and the N-channel transistors 114 and 115 are turned off, and the N-channel transistors 116 and 117 are turned on.
As shown in (e), the switch control signals SW1 and SW2 are both held at the VCC level. As a result, the N-channel transistors 120, 121, 122 and 123 are turned on, and as shown in FIGS.
BL1, BL2 and XBL2 are precharged to 1/2 VCC level by a bit line precharge circuit (not shown).

Next, when a memory cell (not shown) in the memory block 130 is accessed, as shown by the solid line in FIG.
Transition to a level. Therefore, the output of the 2-input OR gate 100 transitions to the VCC level, and the 2-input NOR gate 10
2 changes to the ground level, and as shown in FIG. 2C, the precharge control signal PRE output from the level shift circuit 111 changes to the VPP level, and the N-channel transistors 116 and 117 are turned off. . Then, 2
When the output of the input AND gate 103 transitions to the VCC level and the output of the driver 105 transitions to the VCC level, the N-channel transistor 115 turns on,
As shown by the solid line in FIG. 2E, the switch control signal SW2
Transitions to the ground level. When the output of the inverter 107 changes to the ground level and the output of the level shift circuit 109 changes to the ground level, the P-channel transistor 112 is turned on, and the switch control is performed as shown by the solid line in FIG. The signal SW1 changes to the VPP level. Therefore, the N-channel transistors 120 and 121
Transitions from the VCC level to the VPP level, the N-channel transistors 122 and 123 are turned off, and the memory block 131 on the opposite side of the memory block 130 having the accessed memory cell with the sense amplifier 132 interposed therebetween. Bit lines BL2, X connected to
BL2 is disconnected from the sense amplifier 132. The sense amplifier 132 amplifies the potential difference appearing on the bit lines BL1 and XBL1, but detects the VP of the switch control signal SW1.
The P level is set to a potential higher than the VCC level by more than the threshold potential of the N-channel transistors 120, 121, 122, 123, and as shown by the solid lines in FIG. 2 (f), the bit lines BL1, XBL1 Are amplified to the VCC level and the ground level, and the VCC level can be written to the memory cell.

Next, when the access to the memory cells in the memory block 130 is completed, the memory block selection signal BLK1 transitions to the ground level as shown by the solid line in FIG. Accordingly, the output of the two-input AND gate 103 transitions to the ground level, and the output of the driver 105 transitions to the ground level, so that the N-channel transistor 115 is turned off. When the output of the inverter 107 is V
The transition to the CC level causes the output of the level shift circuit 109 to transition to the VPP level, so that the P-channel transistor 112 is turned off. Furthermore, a 2-input OR gate 1
00 changes to the ground level, the output of the delay element 101 changes to the ground level, and the two-input NOR gate 102
2 transitions to the VCC level,
As shown in (c), the precharge control signal PRE output from the level shift circuit 111 transitions to the VPP level, and the N-channel transistors 116 and 117 are turned on. As a result, the switch control signals SW1 and SW2 become VC
The state transits to the C level. As shown by the solid line in FIG. 6F, the bit lines BL1 and XBL1 are precharged to the 1/2 VCC level by the bit line precharge control circuit.

Conversely, when a memory cell (not shown) in the memory block 131 is accessed, as shown by a broken line in FIG.
Transition to a level. Therefore, the output of the 2-input OR gate 100 transitions to the VCC level, and the 2-input NOR gate 10
2 changes to the ground level, and as shown in FIG. 2C, the precharge control signal PRE output from the level shift circuit 111 changes to the ground level, and the N-channel transistors 116 and 117 are turned off. . Subsequently, the output of the two-input AND gate 104 transitions to the VCC level,
When the output of the driver 106 transitions to the VCC level, the N-channel transistor 114 is turned on, and FIG.
As shown by the broken line in (d), the switch control signal SW1 transitions to the ground level. In addition, the output of the inverter 108 transitions to the ground level, and the output of the level shift circuit 110 transitions to the ground level, turning on the P-channel transistor 113, and as shown by the broken line in FIG. Signal SW2 transitions to the VPP level. Therefore, the N-channel transistors 122 and 123
Transitions from the VCC level to the VPP level, the N-channel transistors 120 and 121 are turned off, and the memory block 131 on the opposite side of the memory block 131 having the accessed memory cell is sandwiched by the sense amplifier 132. Bit lines BL1, X connected to
BL1 is disconnected from the sense amplifier 132. The sense amplifier 132 amplifies the potential difference appearing on the bit lines BL2 and XBL2, but amplifies the VP of the switch control signal SW2.
The P level is set to a potential higher than the threshold potential of the N-channel transistors 120, 121, 122, 123 with respect to the VCC level, and as shown by the broken lines in FIG. 2 (g), the bit lines BL2, XBL2 Are amplified to the VCC level and the ground level, and the VCC level can be written to the memory cell.

Next, when the access to the memory cells in the memory block 131 is completed, the memory block selection signal BLK2 transitions to the ground level as shown by the broken line in FIG. Accordingly, the output of the two-input AND gate 104 changes to the ground level, and the output of the driver 106 changes to the ground level, so that the N-channel transistor 114 is turned off. When the output of the inverter 108 is V
The transition to the CC level causes the output of the level shift circuit 110 to transition to the VPP level, so that the P-channel transistor 113 is turned off. Furthermore, a 2-input OR gate 1
00 changes to the ground level, the output of the delay element 101 changes to the ground level, and the two-input NOR gate 102
2 transitions to the VCC level,
As shown in (c), the precharge control signal PRE output from the level shift circuit 111 transitions to the VPP level, and the N-channel transistors 116 and 117 are turned on. As a result, the switch control signals SW1 and SW2 become VC
The state transits to the C level. As shown by the broken line in FIG. 6G, the bit lines BL2 and XBL2 are precharged to the 1/2 VCC level by the bit line precharge control circuit.

As described above, according to the first embodiment of the present invention, the switch control signals SW1 and SW2 are respectively connected to the P-channel transistors 112 and 113 whose sources are connected to the VPP level and the sources are set to the ground level. N-channel transistors 114 and 115 connected to each other and N-channel transistor 1 whose source is connected to the VCC level
16 and 117, and the gate of each transistor is controlled by a different signal to produce a ternary output signal, which is precharged to the VCC level during standby and switch control on the selected memory block side during memory access. By setting only the signal to the VPP level and setting the switch control signal on the non-selected memory block side to the ground level, the bit line is precharged to 1/2 VCC level during standby, and the High level is amplified to VCC level during memory access. The load of the VPP level generation circuit can be reduced, and the power consumption can be reduced.

(Embodiment 2) FIG. 3 shows an example of a circuit configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 2 shows an operation timing chart of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. In FIG. 3, BL
K1 and BLK2 are memory block selection signals. VP
P is a power supplied from outside the memory element or supplied by a power generation circuit (not shown) inside the memory element, which is higher than an internal power supply potential VCC for writing a high level to a memory cell (not shown). Has a high potential. 150 is a memory block selection signal BLK1, BL
K2 input 2-input OR gate, 151 is 2-input OR
A delay element connected to the output of the gate for delaying signal propagation, 152 is an output of the two-input OR gate and a delay element 1
This is a two-input NOR gate that receives an output of the input 51 and outputs an equalization control signal EQ. 153 is a two-input AND gate for inputting the memory block selection signal BLK1 and the output of the two-input NOR gate 152, and 154 is a memory block selection signal BLK2 and two-input NOR gate 152.
Is a two-input AND gate for inputting the output of. 155,
156 is a driver for inputting the outputs of the two-input AND gates 153 and 154, respectively, and 157 and 158 are
This is an inverter that inputs the outputs of the input AND gates 153 and 154. 159 and 160 are inverter 1
57, the output of the inverter 158, and VPP
Is used as the power supply, and the input of the internal power supply potential VCC level is
This is a level shift circuit that converts the output to a P level and outputs the result.
161 inputs the output of the two-input NOR gate 152 and
A level shift circuit that converts an input of an internal power supply potential VCC level to a VPP level and outputs a precharge control signal PRE using PP as a power supply. Reference numerals 162 and 163 denote P-channel transistors whose gates are connected to the outputs of the level shift circuits 159 and 160, respectively, and whose sources are connected to the power supply VPP. 164 and 165 are N-channel transistors whose gates are connected to the outputs of the drivers 156 and 155, respectively, and whose sources are grounded. The drain of the P-channel transistor 162 and the drain of the N-channel transistor 164 are connected, and output the switch control signal SW1. The drain of the P-channel transistor 163 and the N-channel transistor 16
5 are connected to each other and output a switch control signal SW2. 166 and 167 have their drains connected to the switch control signal SW1 and the switch control signal SW2, respectively.
An N-channel transistor whose source is connected to the internal power supply potential VCC and whose gate is connected to the precharge control signal PRE. Reference numeral 168 denotes an N-channel transistor having a gate connected to the equalization control signal EQ and a source and a drain connected to the switch control signals SW1 and SW2. 180 and 181 are memory blocks. 182 is a sense amplifier. BL1 and XBL1 are bit lines connected to memory cells (not shown) in the memory block 180. BL2 and XBL2 are bit lines connected to the memory cells in the memory block 181. 170 and 171 are gate control signals SW
1 and the sources are bit lines BL1 and XB, respectively.
An N-channel transistor connected to L1 and having a drain connected to the sense amplifier 182. 172,17
Reference numeral 3 denotes an N-channel transistor having a gate connected to the switch control signal SW2, a source connected to the bit lines BL2 and XBL2, and a drain connected to the sense amplifier 182, respectively. Memory block selection signal BLK
1 and BLK2 are signals that are activated when memory cells in adjacent memory blocks 180 and 181 are accessed with the sense amplifier 182 interposed therebetween.

The operation of the semiconductor integrated circuit according to the second embodiment of the present invention constructed as described above will now be described with reference to FIG.
This will be described with reference to FIG. First, at the time of standby, FIG.
As shown in (b), the memory block selection signal BLK1,
BLK2 are both at the ground level. Therefore, a two-input AN
The outputs of the D gates 153 and 154 are at the ground level.
The output of input OR gate 150 is at ground level, delay element 1
The output of 51 is at the ground level, and as shown in FIG. 4C, the equalize control signal EQ output from the two-input NOR gate 152 is at the VCC level which is the internal power supply potential. The outputs of the drivers 155 and 156 are at the ground level, the outputs of the inverters 157 and 158 are at the VCC level, and the outputs of the level shift circuits 159 and 160 are at the VPP level. Further, as shown in FIG. 4D, the precharge control signal PRE, which is the output of the level shift circuit 161, is VP
It becomes P level. Therefore, P-channel transistor 1
62,163 and N-channel transistor 164,1
65 turns off, and the N-channel transistors 166, 1
67, 168 are turned on, and as shown in FIGS.
The switch control signals SW1 and SW2 are both held at the VCC level. Thereby, the N-channel transistor 1
70,171,172,173 are turned on, and FIG.
As shown in (h), bit lines BL1, XBL1, BL2,
XBL2 is precharged to 1/2 VCC level by a bit line precharge circuit (not shown).

Next, when a memory cell in the memory block 180 is accessed, the memory block selection signal BLK1 transitions to the VCC level as shown by the solid line in FIG. Therefore, the output of the two-input OR gate 150 is V
CC level, and as shown in FIG.
Equalize control signal EQ output from OR gate 152
Transitions to the ground level and the N-channel transistor 1
68 turns off. Subsequently, as shown in FIG. 4D, the precharge control signal PRE output from the level shift circuit 161 transitions to the ground level, and the N-channel transistors 166 and 167 turn off. Then, two-input AND
When the output of the gate 153 transitions to the VCC level and the output of the driver 155 transitions to the VCC level, N
The channel transistor 165 turns on, and the switch control signal SW2 transitions to the ground level as shown by the solid line in FIG. Further, the output of the inverter 157 transitions to the ground level, and the output of the level shift circuit 159 transitions to the ground level.
62 turns on, and the switch control signal SW1 transitions to the VPP level as shown by the solid line in FIG. Therefore,
The gate potentials of the N-channel transistors 170 and 171 transition from the VCC level to the VPP level, the N-channel transistors 172 and 173 are turned off, and the sense amplifier 182 is sandwiched between the memory block 180 having the accessed memory cell. The bit lines BL2 and XBL2 connected to the memory block 181 on the opposite side are disconnected from the sense amplifier 182. Sense amplifier 182
Amplifies the potential difference appearing on the bit lines BL1 and XBL1, but the VPP level of the switch control signal SW1 is
N-channel transistor 170 for CC level,
The potential is set higher than the threshold potentials of 171, 172 and 173, and the bit lines BL 1 and XBL 1 are amplified to the VCC level and the ground level as shown by the solid line in FIG. It is possible to write the VCC level.

Next, when the access to the memory cells in the memory block 180 is completed, the memory block selection signal BLK1 transitions to the ground level as shown by the solid line in FIG. Accordingly, the output of the two-input AND gate 153 transitions to the ground level, and the output of the driver 155 transitions to the ground level, so that the N-channel transistor 165 turns off. The output of the inverter 157 is V
The transition to the CC level causes the output of the level shift circuit 159 to transition to the VPP level, so that the P-channel transistor 162 turns off. Furthermore, a 2-input OR gate 1
50 changes to the ground level, the output of the delay element 151 changes to the ground level, and as shown in FIG.
The transition of the equalize control signal EQ, which is the output of the input NOR gate 152, to the VCC level turns on the N-channel transistor 168. As a result, FIG.
As shown by the solid lines (e) and (f), the switch control signal S
W1 and SW2 are equalized to an intermediate potential between the VPP level and the ground level. Subsequently, as shown in FIG. 4D, the precharge control signal PRE output from the level shift circuit 161 changes to the VPP level, and the N-channel transistors 166 and 167 turn on. As a result, the switch control signals SW1 and SW2 transition to the VCC level.
Also, as shown by the solid line in FIG.
XBL1 is halved by the bit line precharge circuit.
Precharged to VCC level.

Conversely, when a memory cell (not shown) in the memory block 181 is accessed, as shown by the broken line in FIG.
Transition to a level. Therefore, the output of the two-input OR gate 150 transitions to the VCC level, and as shown in FIG.
The equalization control signal EQ output from the two-input NOR gate 152 transitions to the ground level, and the N-channel transistor 168 turns off. Subsequently, as shown in FIG. 4D, the precharge control signal PRE output from the level shift circuit 161 transitions to the ground level, and the N-channel transistors 166 and 167 turn off. Subsequently, the output of the two-input AND gate 154 transitions to the VCC level,
When the output of the driver 156 transitions to the VCC level, the N-channel transistor 164 turns on, and FIG.
As shown by the broken line in (e), the switch control signal SW1 transitions to the ground level. When the output of the inverter 158 changes to the ground level and the output of the level shift circuit 160 changes to the ground level, the P-channel transistor 163 is turned on, and the switch control is performed as shown by the broken line in FIG. Signal SW2 transitions to the VPP level. Therefore, N-channel transistors 172, 173
Transitions from the VCC level to the VPP level, the N-channel transistors 170 and 171 turn off, and the memory block 180 on the opposite side of the memory block 181 having the accessed memory cell is sandwiched by the sense amplifier 182. Bit lines BL1, X connected to
BL1 is disconnected from the sense amplifier 182. The sense amplifier 182 amplifies the potential difference appearing on the bit lines BL2 and XBL2, but detects the VP of the switch control signal SW2.
The P level is set to a potential higher than the VCC level by more than the threshold potential of the N-channel transistors 170, 171, 172, and 173. As shown by the broken lines in FIG. 4H, the bit lines BL2 and XBL2 Are amplified to the VCC level and the ground level, and the VCC level can be written to the memory cell.

Next, when the access to the memory cells in the memory block 181 is completed, the memory block selection signal BLK2 transitions to the ground level as shown by the broken line in FIG. Accordingly, the output of the two-input AND gate 154 transitions to the ground level, and the output of the driver 156 transitions to the ground level, so that the N-channel transistor 164 turns off. Also, the output of inverter 158 is V
The transition to the CC level and the transition of the output of the level shift circuit 160 to the VPP level turn off the P-channel transistor 163. Furthermore, a 2-input OR gate 1
50 changes to the ground level, the output of the delay element 151 changes to the ground level, and as shown in FIG.
The transition of the equalize control signal EQ, which is the output of the input NOR gate 152, to the VCC level turns on the N-channel transistor 168. As a result, FIG.
As shown by the broken lines (e) and (f), the switch control signal S
W1 and SW2 are equalized to an intermediate potential between the VPP level and the ground level. Subsequently, as shown in FIG. 4D, the precharge control signal PRE output from the level shift circuit 161 changes to the VPP level, and the N-channel transistors 166 and 167 turn on. As a result, the switch control signals SW1 and SW2 transition to the VCC level.
Further, as shown by the broken line in FIG.
XBL2 is halved by the bit line precharge circuit.
Precharged to VCC level.

As described above, according to the second embodiment of the present invention, the switch control signals SW1 and SW2 are respectively connected to the P-channel transistors 162 and 163 whose sources are connected to the VPP level and the sources are connected to the ground level. N-channel transistors 164 and 165 connected to each other and N-channel transistor 1 whose source is connected to the VCC level
66, 167, and a transistor 168 for controlling the gate of each transistor with a different signal to provide a ternary output signal and for equalizing the switch control signals SW1, SW2 is provided. By charging the memory and accessing the memory, only the switch control signal on the selected memory block side is set to the VPP level, and the switch control signal on the non-selected memory block side is set to the ground level.
Level is precharged, and at the time of memory access, Hi
The load on the VPP level generation circuit can be reduced while allowing the gh level to be amplified to the VCC level. Further, at the end of the memory access, after equalizing the switch control signals SW1 and SW2,
By precharging to the VCC level, it is possible to reduce the amount of charge of the switch control signals SW1 and SW2 having a large load, and it is possible to reduce internal power consumption.

In the first and second embodiments, the logically high level is the VCC level and the VPP level, and the logically low level is the ground level.
If the P level is higher than the VCC level and the VCC level is higher than the ground level, the potential is not limited. The N-channel transistor and the P-channel transistor described in the first and second embodiments are not limited to the N-channel or the P-channel.

[0032]

As described above, according to the present invention,
A switch control signal that has been conventionally precharged to a higher potential than the internal power supply potential can be precharged to the internal power supply potential, thereby reducing the amount of charge of the switch control signal having a large load.

According to the present invention, the selection switch control signal charged to a higher potential than the internal power supply potential and the non-selection switch control signal discharged to a level lower than the internal power supply potential immediately before the precharge after the end of the memory access. By performing equalization and then precharging to the internal power supply potential to reduce the amount of charge at the time of precharging the switch control signal, power consumption can be reduced, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the embodiment.

FIG. 3 is a circuit configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is an operation timing chart of the embodiment.

FIG. 5 is a circuit configuration diagram of a conventional semiconductor integrated circuit.

FIG. 6 is an operation timing chart of the conventional example.

[Explanation of symbols]

112,113,162,163 P-channel transistors 114,115,116,117,164,165,166,
167,168 N-channel transistor

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/4091

Claims (4)

(57) [Claims] 1. A first memory block, a second memory block, a sense amplifier, and a first switch control signal input to a gate to connect a bit line in the first memory block and the sense amplifier. A first transistor to be connected, a second transistor to which a second switch control signal is input to a gate to connect a bit line in the second memory block to the sense amplifier, and a first switch control signal And switch control signal generation means for generating the second switch control signal, wherein the switch control signal generation means has a source supplying a first voltage level.
A first power supply connected to the first memory block at a gate;
Or a block for selecting the second memory block.
A first internal signal generated based on a clock selection signal is input.
And the drain outputs the first switch control signal.
A third transistor connected to the first node to be connected;
A source is connected to the first power supply and a gate is connected to the first power supply.
And the drain is the second switch
A fourth node connected to the second node from which the control signal is output;
The transistor and the source are above the first voltage level
Connected to a second power supply that supplies a high second voltage level
Generated at the gate based on the block selection signal.
A second internal signal is input, and the drain is connected to the first node.
A fifth transistor connected to the source, and a source
Providing a third voltage level lower than the first voltage level;
Connected to a third power supply, and the gate of the block selection signal
And a third internal signal generated based on the
A sixth transistor connected to the first node
And a source connected to the second power supply and connected to the gate.
Fourth internal generated based on the block selection signal
A signal is input and the drain is connected to the second node.
And a source connected to the third power supply.
Connected to the gate based on the block select signal.
A fifth internal signal generated is input, and the drain is connected to the fifth internal signal.
An eighth transistor connected to the second node;
Setting the first switch control signal and the second switch control signal when the bit line pre-charged to both said first voltage level, when a memory cell access, in accordance with the block <br/> click selection signal, and characterized by shifting the either one of the first switch control signal and the second switch control signal is transitioned to the <br/> second voltage level, the other to the third voltage level Semiconductor integrated circuit. 2. The switch control signal generating means includes a source and a drain connected to the first node and the second node, respectively, and a sixth internal signal generated at a gate based on the block selection signal. The ninth where is input
The semiconductor integrated circuit according to claim 1, further comprising a transistor. 3. When the memory cell access is completed, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are turned off, and then the ninth transistor is turned on. The first node and the second node are short-circuited via the ninth transistor, and thereafter, the third transistor and the fourth transistor are turned on to connect the first node to the first node. 3. The semiconductor integrated circuit according to claim 2, wherein said second node and said second node are charged to said first voltage level. Wherein the potential of the third power source is a ground potential, the semiconductor integrated circuit according to claim 1, wherein said second power source which is a power generated by the internal power generation circuit.