JPH06259961A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce current consumption by providing a connecting means between the mth driving signal wire and the nth driving signal wire, and using a charge again by another wire. CONSTITUTION:The mth driving signal wire and the nth driving signal wire driving a memory cell respectively, are connected by connecting means. For instance, a data line pair DIi in the block AR1 of a memory cell MC, becomes a high level or a low level according to a read-out signal. The rewriting-in of each memory cell to which a word wire W11 in the AR1 is connected, is performed. Then, the word wire W11 becomes a low level, and RP1 and RN1 are reversed again. A part of the rewriting-in operation of another memory cell MC, is performed through the above connecting means by using a charge required for amplification. At this time, the rewriting-in operation is performed to 1/2 potential according to the number of the data wires of each block, and after that, an usual sense amplifier operation is performed. Consequently, since amplification is performed to the half of an original amplitude, the quantity of a through current is small, and a current consumption can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Particularly, it relates to the technology of reducing the current consumption.

[0002]

2. Description of the Related Art A conventional example will be described below. In the following description, complementary signals represented by overlining the symbols in the drawings are indicated by / before the symbol, and unless otherwise specified, the symbol indicating the terminal name is the wiring name at the same time,
In the case of a power supply that also serves as a signal name, it also serves as its voltage value.

A conventional dynamic random access memory (DRAM) has a structure as shown in FIG. That is, in the memory cell array AR, word lines W1 to W4
A memory cell MC of one transistor and one capacitor is placed at the intersection of the data lines D1 and / D2. RA1 and RA
Reference numeral 2 denotes a sense amplifier for reading and rewriting the signal of this memory cell, which is driven by common sources (sense amplifier drive signal lines) PN and PP. The signal of the common source is PC0 that short-circuits PP and PN and precharges to the voltage of HV, and p that charges PP to the high voltage VD.
The channel MOS transistors DP and PN are set to the low voltage VS.
It is generated by an n-channel MOS transistor DN discharging to. The drive signal of DP is RP and the drive signal of DN is RN. Also, PC1 and PC2 are circuits that short-circuit the data line pair and precharge to HV, and the control signal for these and PC0 is FP. DA1 and DA
Reference numeral 2 is a circuit for transferring the signal appearing on the data line pair to the circuit at the subsequent stage and transferring the signal to be written in the memory cell through the data line from the subsequent stage. The pair of I / O and / I / O is the input circuit. It corresponds to the output. The transfer opening / closing is controlled by YS1 and YS2. In such a DRAM, the charge stored in the memory cell is lost by various leak currents, and therefore the same information must be rewritten at regular intervals, which is called refresh. This refresh operation will be described with reference to FIG. R1 is a clock signal for controlling this operation, which is given by an external clock such as / RAS, or internally generated by an oscillation circuit.
First, in the initial state, CK is low level,
Since RP is high and RN is low, DP and DN are off. Further, since FP is at high level VD, the data line pair and PP and PN are short-circuited to have HV potential. Also, YS1 and YS2
Is low and DA1 and DA2 are off.
In the refresh operation, YS1 and YS2 are always low level. The word line is VS. Here, when R1 changes from the low level to the high level, FP first becomes the low level VS, and the data line pair and PN and PP become floating at the potential of HV. Since the word line W1 is selected and becomes the high level VCH here, a minute voltage difference corresponding to the information from the memory cell is generated on the data line pair D1 and / D1. Next, since RP and RN are inverted, DN is turned on, PN is discharged toward VS, and D
P is turned on and PP is charged toward VD. As a result, the sense amplifiers RA1 and RA2 operate and the minute voltage signal difference is amplified to a large amplitude VD-VS on the data line pair. When amplification is completed, the word line becomes low level VS,
RP and RN are inverted and DP and DN are turned off. After this, it is important to note that the difference between the conventional example and the present invention is F
P becomes high level VD, the data line pair and PN and PP are short-circuited, and become HV. The above is the refresh operation in the conventional DRAM.

[0004]

When it is attempted to retain the information in the DRAM by battery backup, the so-called standby power supply current is mainly determined by the refresh current, and how to reduce this is a problem. During standby, the memory cells are refreshed in order. This refresh current consists of the operating current of the refresh control circuit and the data line charging / discharging current. Among these, with respect to reduction of the current of the refresh control circuit, studies are underway to minimize the number of operating elements in the circuit. However, as for the data line current, the current consumption from the power supply side is reduced by setting a low voltage in the standby state or lengthening the refresh cycle as described in JP-A-60-45997. A method of suppressing was disclosed.

However, as shown in FIG. 25, since the degree of integration is quadrupled for each generation, the total charge amount QD charged and discharged in the refresh operation increases even if the data line voltage is lowered. Further, there is a limit to the lengthening of the refresh cycle due to the restriction from the leak current of the memory cell transistor.

Therefore, an object of the present invention is to provide a semiconductor memory device of low current consumption.

[0007]

According to the present invention, a semiconductor memory device of low current consumption is provided by reusing the current once supplied from a power supply to another circuit without immediately flowing it to the ground. To do. For this purpose, the following means are provided. That is, according to the present invention, a first memory cell, a first data line pair to which the first memory cell is connected, and a first signal amplifying a minute signal read to the first data line pair are provided. Sense amplifier, a second memory cell, and the second
Second data line pair connected to the second memory line and a second data line pair for amplifying a minute signal read to the second data line pair.
Of the first sense amplifier, the first drive signal line for driving the first sense amplifier, the first switch means for connecting the first drive signal line and the power supply line, and the second sense amplifier. A semiconductor memory device having a second drive signal line for driving and a second switch means for connecting the second drive signal line and a power supply line, wherein the first drive signal line and the second drive are provided. It is characterized in that a connecting means is provided between the signal line and the signal line.

[0008]

With the above structure, the electric charge stored on the first drive signal line side flows into the second drive signal line side through the connecting means. As much as this flowing charge,
A current flowing when a voltage is applied to the second drive signal line can be suppressed. That is, the current consumption can be reduced as compared with the conventional case by flowing the electric charge, which has been discarded by simply short-circuiting in the past, to another line and reuse it.

[0009]

1 is a diagram showing a first embodiment of the present invention. Although the symbols and the like are almost the same as those described in the conventional example, two systems of common sources (sense amplifier drive signal lines) PP1 and PP2 and PN1 connected by the switch SP and the switch SN (together with the switch S) are connected. And PN
2 to which a similar circuit is connected. The control terminals of the switches SP and SN are TP and TN.
MC is a memory cell, W11 to W22 are word lines, and D11 to / D2n are data line pairs. The block of the memory cell MC selected by the word lines W11 and W12 and the data line pair D11 to / D1n is AR1, and the word line W.
The block of the memory cell MC selected by 21 and W22 and the data line pair D21 to / D2n is AR2. Although only two word lines and two data line pairs are shown in each block in FIG. 1, many pairs are provided in the actual configuration. VD and V
S is a power supply for high level and low level of the data line, and HV is a power supply for precharging the data line pair and the common source pair (here, HV = (VD + VS) / 2).
Is. The array-related circuits AM1 and AM2 are composed of the following circuits. PC10 and PC20 are common source pair short-circuit (precharge) circuits, and PC11 to PC1
n and PC21 to PC2n are short-circuit (precharge) circuits for data line pairs, and RA11 to RA2n are sense amplifiers. DP11 is a p-channel MOS transistor that charges PP1 to VD, and its control terminal is R
P1 and DP21 are for PP2, and their control terminals are RP2. DN11 discharges PN11 to VS n
Channel MOS transistor whose control terminal is RN
1, DN21 is for PN2, and its control terminal is R
N2. The present invention does not specify the structure of these memory cells, the data line, and the common source line, for example, intersecting in the middle.

An operation example of this circuit will be described with reference to FIG. In the following description, the word line high level voltage V
All high level voltages other than CH are designated as VD, but their potentials need not be the same. In the initial state, the word lines W11 to W22 are at the low level VS. Also, RP
1 and RP2 are VD and RN1 and RN2 are VS, DP11 to DN21 are turned off, and FP1 and FP2
Is VD, so n channel M in PC10-PC2n
Since the OS transistor is on, the data line D11
~ / D21 and the common source pair PP1 to PN2 are precharged to HV. First, FP1 is low level VS
Then, the short circuit connected to this turns off and PP
1 and PN1 and the data lines D11 to / D1n become floating at the potential of HV. After that, when the word line W11 becomes the high level VCH, the transistor in the memory cell MC is turned on and a minute voltage is generated in the data line. This minute voltage is amplified when RP1 and RN1 are inverted. This operation is the same as the operation of the conventional example. RP1 and RN
Before 1 is inverted, TP and TN are temporarily turned on and HV
Even if the PP2 and PN2, which are the same as the above, are connected to the PP1 and PN1, respectively, no change occurs. The data line pairs D1i and / D1i (i = 1 to n) in AR1 become VD and VS, respectively, according to the read signal. This makes A
Rewriting of each memory cell connected to the word line W11 in R1 is performed. After this, the word line W11 becomes low level, RP1 and RN1 are re-inverted, and PP1 and PN1 become floating at the potentials of VD and VS, respectively. The operation up to this point is the same as the conventional one. Conventionally, after that, PC10 to PC1n are turned on to short-circuit the data line pair connected to PP1 and PN1 and the sense amplifier driven thereby, and precharged to the potential of HV. In other words, the charge required for amplification was short-circuited and discarded. In the present invention, this charge is used to perform a part of the rewriting operation of another memory cell.
In the next cycle, as described below, the charges used in the rewriting of AR1 described above are used for rewriting the memory cells in AR2. First, FP2 becomes low level VS, the short circuit connected to this turns off, and PP2 and PN2
The data lines D21 to / D2n become floating at the potential of HV. The word line W21 becomes the high level VCH, the transistor in the memory cell MC is turned on, and a minute voltage corresponding to the signal of the memory cell is generated in the data lines D21 and / D21 in the figure. After this minute signal is generated, in the present invention, the switches SP and SN are switched by TP and TN.
Turn on. This allows PP1, PP2 and PN
1 and PN2 are short-circuited. By this, V
The charges of PP1 which is D and the data line electrically connected to PP1 flow into PP2 which is HV to operate the p-channel MOS transistor of the sense amplifier connected to PP2. Similarly, the electric charge of PN2 which is HV flows into PN1 which is VS and the data line which is electrically connected to this, and the n-channel MOS transistor of the sense amplifier connected to PN2 is operated. As a result, the minute signals on the data lines D21 to D2n are amplified. If the number of data lines in AR1 and AR2 is the same, this amplification is performed up to half the original amplitude because the total capacitance is the same. That is, the high-level side of the data line is up to VM1 which is a potential of ½ of VD + HV, and the low-level side is up to VM2 which is a potential of ½ of VS + HV. Therefore, the potential of the data line pair on the AR1 side is also the same. After this, TP and TN are inverted and the switches SP and SN are turned off.

Next, RP2 and RN2 are inverted and a normal sense amplifier operation is performed. At this time, since the amplitude has already been amplified to half of the original amplitude, the charge to be supplemented from the power supply terminals VD and VS via DP21 and DN21 may be half the normal amount. Further, since the amplitude is amplified to half of the original amplitude, the shoot-through current in the normal sense amplifier operation is also small. On the AR1 side where the original amplitude is half, FP1 is at high level VD
Then, the short circuit is turned on and short-circuited. That is, the amount of electric charge that is short-circuited and discarded is half that in the conventional case. Now, on the AR2 side where the original amplitude is obtained by the normal sense amplifier operation, rewriting of each memory cell connected to the word line W21 is performed. next,
The word line W21 becomes low level VS, and the transistor in the memory cell is turned off. Subsequently, RP2 and RN2 are turned off, and PP2 and PN2 become floating at the potentials of VD and VS, respectively. AR in this state in the next cycle
Select another word line W12 in 1 and select D11 and / D11
If a minute signal is read out to the switch SP and SN,
A similar operation can be performed by turning on. This time, PP2 and PN2 on the data line in AR1
Also, amplification is performed up to half of the original amplitude by the charge of the data line connected to this. Such an operation is repeated for all word lines during the period indicated by CCR in FIG. 2 except the first and last cycles. In the last cycle, as in the case of AR2 in FIG.
Short to V. This allows all memory cells to be refreshed. Since the charges of the arrays on the opposite sides can be utilized except for the first and last cycles, the charge / discharge current of the data line can be halved in the present invention as compared with the conventional case. That is, assuming that the number of word lines is 2 m (each m in AR1 and AR2), the number of data line pairs per word line is n, and the data line capacity is CD, the high level of the data lines is VD and the low level is VS. Then, the charging / discharging current in the conventional method is (1/2) × n × CD × (VD-VS) × 2 m, but if the present invention is used, (1/2) × n × CD × (VD -VS) + (1/2) x
(1/2) * n * CD * (VD-VS) * (2m-1), which is almost half of the conventional method.

FIG. 3 is a second embodiment of the present invention which shows the present invention more specifically. In this embodiment, for the sets of the memory cell arrays AR11 and AR12 and AR21 and AR22, the corresponding PP and PN are connected by a switch to perform the above operation. AM11-AM22 is 2
Shared by a pair of data lines, SH11-SH22
Which data line is electrically connected is determined by an n-channel MOS transistor controlled by. With such a configuration, the layout of AM11 to AM22 can be performed at a pitch smaller than the layout pitch of the memory cells. Further, the switch SP11 connecting the PP11 and PP21 is composed of a p-channel MOS transistor. Similarly, SN11 is a switch that connects PN11 and PN21 formed of n-channel MOS transistors, SP12 is a p-channel MOS transistor switch that connects PP12 and PP22, and SN12 is an n-channel MOS that connects PN12 and PN22. It is a transistor switch. Note that these switches are a p-channel MOS transistor and an n-channel M, respectively.
A so-called analog switch using both OS transistors may be used.

An example of this operation will be described with reference to FIG. R
Reference numeral 1 is an on-chip clock signal that controls the operation of the circuit of this embodiment. Here, the case where AR11 and AR21 are selected alternately is taken as an example. Therefore, SH112, SH121, SH212, and SH221 are always at high level, and the n-channel MOS transistor connected to them is always on. SH111 and SH122 and SH211 and SH222 are at a low level V depending on the operation.
The memory cell array that becomes S and is not selected is electrically disconnected. When R1 changes from low level to high level, first SH
111 and SH122 become low level VS, AM11
And AM12 are electrically connected only to the memory cell array AR11. Also, FP11 and FP1
2 goes from the high level VD to the low level VS, and the data line and PP11 to PN12 are short-circuited and the precharge to HV is released. After that, the word line W11 is selected and becomes the high level VCH, and a minute signal is generated on the data lines D11 and / D11. Where TP1 and TP2 and T
N1 and TN2 are inverted and PP11, PP21, PP12
And PP22 and PN11 and PN21, PN12 and PN2
2 and 2 are short-circuited, but since they have the same potential, no change occurs. After TP1 and TN2 are inverted again, R
When P11 and RP12 change from the high level VD to the low level VS and RN11 and RN12 change from the low level VS to the high level VD, the sense amplifiers RA11 to RA2n operate and the minute signal on the data line is amplified. After amplification, RP11 and RP12 and RN11 and RN12
Is inverted and PP11 and PP12 and PN11 and PN
12 is in a floating state. Also, the word line W1
1 is a low level VS. Here, the word line W21 is selected and the data line D2 is selected in the next cycle of the clock R1.
A minute signal is generated at 1 and / D21. After this, TP1
And TP2 and TN1 and TN2 are inverted, and PP11 and PP21, PP12 and PP22 and PN11 and PN2
1 and PN12 and PN22 are short-circuited. As a result, the amplitude is amplified to half the original data line amplitude as described with reference to FIGS. After this,
RP11 and RP12 and RN11 and RN12 are inverted, and the data line pair is amplified to the amplitude of VD-VS. After that, FP11 and FP12 become high level, and D11 and / D11 are short-circuited. Since the following description is a repetition of this, it will be omitted, but by using the present invention in this way,
The charge / discharge current of the data line can be reduced to about half that of the conventional one. In the present invention, the charge / discharge current of the data line can be further reduced by transferring charges between the common source pairs of three or more systems.

FIG. 5 shows four common source pairs PP1-P.
It is a third embodiment of the present invention in which the charge / discharge current of the data line is reduced to 1/4 of that of the conventional case by using N4. SPmn and SNmn
(M = 1 to 4, n = 1 to 4) are common sources P, respectively.
These are p-channel MOS or n-channel MOS transistors forming a switch that connects Pm and PPn and PNm and PNn, and TPmn and TNmn are terminals for turning on / off the corresponding switches. Other means may be used for these switches. The other symbols are the corresponding symbols in FIG. 1 simply added with numbers for the four systems and have the same configuration.

An example of this operation will be described with reference to FIG. TP
Since the signals of mn and RPm are simply the inverted signals of TNmn and RNm, only TNmn and RNm are shown in the figure and TPmn and RPm are not shown. In FIG. 6, unlike the description in FIG. 2 or 4, only the period of the repetitive operation is shown and the first and last cycles are omitted. In the first state in this figure, the data line pair D1, / D1 and common source PP1, PN1 in AR1 are precharged to the potential of HV, and the data line pair D2, / D2 and common source PP2 in AR2 are precharged. , Data line pair D4 in PN2 and AR4,
In / D4 and common sources PP4 and PN4, the high level is HV + (1/2) * (VD-HV), and the low level is HV- (1/2) * (HV-VS).
Is. Amplification is completed in the data line pair D3, / D3 and common sources PP3, PN3 in AR3, the high level of which is VD and the low level of which is VS, and the word line can be returned to the non-selected state. Also, FP1 to FP4
Then, only FP1 is at a high level, so that PC10 and PC11 are on, and the other PC20 to PC41 are off. Further, TNmn and TPmn are in a state of turning off the switches. RNm and RPm are also in a state of turning off the transistors they drive.

FIG. 7 shows an example of a simulation waveform of a circuit constructed by using the present invention. The circuit of the embodiment of FIG. 1 and FIG.
It corresponds to the operation example of. The voltage waveforms of the common source and the data line and the current waveform flowing in the common source are shown. Initially, common sources PP1 and PN1 are precharged to 0.75V. Similarly, after the read signal voltage appears on the pair of data lines D11 and / D11 precharged to 0.75V, DP11 and DN11 shown in FIG.
Therefore, PP1 is 1.5V power supply VD and PN1 is 0V
Is electrically connected to the power source VS. As a result, FIG.
Sense amplifier RA11 operates to operate the data line pair D11,
/ D11 is amplified to an amplitude of 1.5V-0V. At this time, the current as shown in FIG.
Flow to P1 and from PN1 to 0V power supply VS. next,
The common sources PP2 and PN2, to which the data line pair D21 and / D21 in AR2 of FIG. 1 are connected via a sense amplifier, are connected to PP1 and PN1 by switches in S, respectively. Therefore, due to the operation peculiar to the present invention, as shown in FIG. 7, D21 and PP2 have a voltage intermediate between 1.5V and 0.75V, and / D21 and PN2 have a voltage intermediate between 0.75V and 0V. Becomes At this time, the power supplies VD, V
No current flows from S. After that, DP2 shown in FIG.
1 and DN21 electrically connect PP2 to the 1.5V power supply VD and PN2 to the 0V power supply VS. Therefore, the data line pair is amplified to the amplitude of 1.5V-0V. At this time, since the amplitude has already been amplified to about half, the current becomes smaller than that in the case where the direct data line pair is amplified to the amplitude of 1.5V-0V as shown in FIG. Therefore, the bounce of the power supply line in the actual LSI chip also becomes small.

FIG. 8 shows the time dependence of turning on the switch in S of the ratio of the charge consumed in charging and discharging the data line in AR2 to the charge in AR1 reused by the present invention. , The gate width of the MOS constituting the switch in S of FIG. 1 is shown as a parameter. Ideally, it will be 50%.
Gate width is 250μm for pMOS and 125μ for nMOS
m, the time to turn on the switch in S is 60 ns
With the above, it is close to 50%.

FIG. 9 shows a photograph of an experimental chip prepared by using the 0.25 μm processing technique in order to verify the operation and effect of the present invention. AR1 and AR2 are a 32K-bit memory cell array, DP11 electrically connected to the power supply,
The parts of DN11, DP21, DN21 and the switch S are shown surrounded by a white frame.

FIG. 10 shows a waveform measured using the experimental chip of FIG. TN, PP1, PN1, PP2 of FIG.
The waveform of PN2 is shown. As shown in FIG. 10, C in FIG.
Similar operation waveforms of PP1 to PN2 during the CR period were obtained, indicating that the present invention is effective.

FIG. 11 shows an example of the structure of a DRAM using the present invention. / RAS is a row address strobe signal which activates a row system circuit, and / CAS is a column address strobe signal which activates a column system circuit. / WE is a selection signal as to whether or not to perform a write operation, / OE is a selection signal as to whether or not to output a signal to the outside in a multi-bit configuration, and / RFSH is a selection signal as to whether or not to perform a refresh operation. This is a method of inputting address signals in time division into row system and column system (address multiplex)
However, in the case of the method that does not time-share (address non-multiplex), / RAS, / CAS instead of /
CE becomes the activation signal. CLK is an input buffer for these external signals and a circuit for generating various internal control signals from these external signals. A1 to An are address signals, and ADBuf is an address buffer. AR1 and AR2 are memory cell arrays. These two arrays may be used as so-called banks (hereinafter, AR1 is referred to as bank 1 and AR2 is referred to as bank 2) that can be selected independently of each other. Row Dec is a row decoder and word driver, and Colomb Dec is a column decoder and driver. AM1 and AM2 are data line related circuits such as a sense amplifier and a data line precharge circuit. D
in Buf is a data input buffer, Dout Buf
Is a data output buffer, Din is a data input terminal, Do
ut is a data output signal terminal. S is the short circuit described in the above embodiments specific to the present invention. RF
Is a refresh control circuit, and ADC is an address counter. These circuits determine that this DRAM starts refreshing, and the refresh operation using the present invention causes the refresh address signal A generated by the ADC.
done using iR. Although not shown in the other drawings,
It may have an externally modifiable register for storing the necessary information in various operating modes of the DRAM of the present invention. In addition, input signals such as / RAS to An and Din and Dout signals are input / output by providing dedicated pins,
There are cases where time-divisional input is performed via a narrow bus line, and cases where a read or write operation is performed after the chip has received all input signals in advance and then has determined that this DRAM chip has been selected. DRA like this
By configuring M, the refresh current D is small.
RAM can be realized.

The refresh operation of the present invention is initiated by the timing and voltage level relationships of several input signals. FIG. 12 shows a first example of the block configuration of the control circuit necessary to realize this. Blocks having the same symbols as in FIG. 11 indicate blocks having similar functions.
The CLK circuit block is an input buffer for external signals and a circuit for generating various internal control signals from these external signals. Here, only / RAS and / CAS are shown as input signals. RF is a refresh control circuit block,
The CBR detection circuit block is a circuit block that detects a timing relationship between specific input signals (here, as an example, / CAS falls before / RAS falls). The timer is a circuit block that starts operating when the CBR detection circuit block detects the timing relationship described above, and switches the output signal CRR after a certain time tR from this time. The clock generation circuit block generates the internal clock signal CKi when the CRR is switched. The ADC generates the refresh address signal AiR necessary for the refresh operation by the internal clock CKi. By using such a circuit block configuration, the timing relationship of the input signals can be detected, and the operation of the present invention can be started when a certain time has elapsed from this detection.

The operation of the DRAM of FIG. 11 using the circuit block of FIG. 12 will be described with reference to FIG. First, / RAS and / CAS are at a high level at first. Here, / CAS switches to a low level at time t1, and then / RAS switches at this time at t2. This / RAS and / CAS
When both of them are at the low level for the time tR (for example, 8 microseconds), the timer detects that this time has elapsed and switches the output signal CRR from the low level to the high level in the example of this figure. By this switching of CRR, the internal clock CKi is generated as shown in the figure. Based on this CKi, the control signal and the refresh address signal AiR for the refresh operation of the present invention described in FIGS. 1 to 6 are generated. by this,
For example, the word line W1 in AR1 and the data lines D1, / D1 and the word line W2 in AR2 of the DRAM of FIG.
13 and the data lines D2 and / D2, the refresh operation according to the present invention as shown in FIG. 13 is performed. This operation is sequentially performed on all the memory cells at regular intervals while / RAS and / CAS are both low. Also,
In order to end this operation state, / RAS and / CAS are set to the high level in any order.

FIG. 14 shows another example of the operation timing of the DRAM using the circuit of FIG. In (1), / RAS
When the refresh control signal / RFSH is switched from a high level to a low level while (/ CE in the case of address non-multiplex) is at a high level, the timer operates and measures the time tR, and when tR elapses, the CRR is switched. The refresh operation according to the present invention is performed as in FIG. At the end, / RFSH can be returned to the high level again. In (2), the timer operates and the time tR is measured by switching the specified single signal, for example, / CE, and when tR elapses, the CRR is switched and the refresh operation is performed as in FIG. is there.
In order to return to the normal operation, / CE is started, the refresh operation is completed, and after the lapse of time tP, the next operation is started. In (3), / CE is at a high level and / OE
Is detected to be low level, the timer operates and measures the time tR, and when tR elapses, the CRR is switched to start the refresh operation of the present invention. In order to return to the normal operation, / OE is raised to complete the refresh operation, and after a lapse of time tS, the next operation is started. Note that / CE in (2) and (3) may be / RAS, for example.

Next, FIG. 15 shows a second example of the control circuit in the DRAM of FIG. Unlike FIG. 12, the refresh control circuit RF has no timer and is composed of a CBR detection circuit block and a CRR determination circuit block. CB
The R detection circuit block detects the timing relationship as described above, and here, generates the internal clock CKi for the refresh operation. The CRR determination circuit block determines the timing relationship and the voltage relationship, and generates a signal CRR indicating whether or not the refresh operation according to the present invention is performed. For example, the refresh operation of the present invention is performed when CRR is at a high level, and the normal refresh operation is performed when CRR is at a low level. The ADC is an address counter and generates a refresh address signal AiR.

DRA of FIG. 11 using the configuration of FIG.
FIG. 16 shows a first timing example of M. First, time t
1 / CAS switches from the high level to the low level, and then / RAS switches from the high level to the low level at time t2. The CBR detection circuit detects this, the refresh address signal AiR is generated, and the refresh operation is started. Further, at time t3, when / CAS remains at the low level and / RAS changes, the CRR detection circuit detects this and CRR is switched from the low level to the high level, and the operation of the present invention starts. In the first half of the first cycle # 1, the operation of the present invention is the same as that of the normal operation.
The CRR may be switched at this time t3. Therefore, if you start / CAS and then / RAS,
Normal refresh operation is performed. In the last cycle #n, / CAS is first set to a high level at time t4 and then t
At 5 / RAS goes high. As a result, CRR becomes low level, and the refresh operation according to the present invention ends. The refresh address signal is externally / RA
It may be input in synchronization with S. In this way, no address generation circuit is needed inside the chip.

FIG. 17 shows a second timing example. Here, since the internal operation is similar to that of FIG. 16, only / RAS, / CAS and CRR are shown. 16 is different from FIG. 16 in that / RAS is used as a clock in FIG. 16 and / CAS is used as a clock in FIG. That is, first, at time t1, / CAS is switched from the high level to the low level to start the refresh operation and the internal circuit starts to operate. Unlike FIG. 16, the switching of the signal CRR that starts the operation of the present invention is performed at time t3 /
This is done by keeping RAS low and / CAS switching high. Therefore, if / RAS is raised and then / CAS is raised, a normal refresh operation is performed. In the last cycle #n, / RAS
First becomes high level at time t4, and then at / 5 / CAS
To a high level.

FIG. 18 shows a third timing example,
Both RAS and / CAS are used as clocks. First /
CAS is stopped at time t1, then / RAS is set at time t
Stop at 2. Then, at t3, / RAS is launched,
If / CAS rises at t4, the refresh operation of the present invention is performed. Although not shown, conversely, if / CAS rises at t3 and / RAS rises at t4, the conventional refresh operation is performed. The operation of starting / RAS is repeated n-1 times, and / C is executed in the last cycle.
Start AS first. At this time, the address signal may be generated by an internal generation circuit or may be externally applied.
By doing so, the refresh operation of the present invention can be performed. Also, as indicated by # 1 in FIG. 18, / RA
If S and / CAS are changed only once, then / RA
The refresh operation of the present invention may be automatically performed a certain number of times without changing S and / CAS. The number of times may be stored in an externally rewritable register provided inside the chip.

The DRAM includes a so-called synchronous DRAM which operates in synchronization with the system clock. In this DRAM, whether the input signal when the clock is input is high level or low level is read, and the operation mode is designated by this combination to operate. The synchronous DRAM is described in Nikkei Electronics, May 11, 1992, pages 143 to 147. FIG. 19
An example of the operation timing of the synchronous DRAM to which the present invention is applied is shown in FIG. Here, the operation mode is designated by a combination of input signal levels at the rising edge of the clock CK. The hatched portions in the figure show the state of don't care at any level.
At one rising edge of the clock CK, when the clock enable signals / CKE, / RAS, / CAS, and the chip select signal CS are low level, and / WE and the specific address signals An and An-1 are both high level, The refresh operation of the present invention is performed. This is n as in the case of FIG.
-Repeat once. At the last nth time, both An and An-1 are set to the low level to specify the end of the refresh operation of the present invention. Address signals other than An and An-1 may be input from the outside, or an address generating circuit may be provided in the chip to generate a necessary address for each operation.
Further, the refresh operation of the present invention may be performed plural times by the above-mentioned designation once, and the information of this number may be stored in the internal register.

FIG. 20 shows an example of the number of operation mats in the normal operation and the refresh operation in the present invention. At the time of refreshing, the operation of the present invention is performed between the sub-array in AR1 and the sub-array in AR2. According to the present invention, the charging / discharging current of the data line at the time of refreshing can be reduced to 1/2 or less, but it is desirable to reduce the operating current of the peripheral circuit as much as possible. To this end, in order to reduce the number of operations of peripheral circuits necessary for refreshing all memory cells, it is advisable to operate a larger number of subarrays during the refresh operation than during the normal operation. In the example of FIG. 20, during normal operation,
For example, only the sub-array SR11 in the array AR1 and the sub-array SR25 in the array 2 are operated, but four times as many sub-arrays are operated during the refresh operation.
As a result, the current consumption in the normal operation can be suppressed and the current can be reduced by using the present invention during the refresh operation.

FIG. 21 shows an example of the array structure used in the present invention. The alphabetical portions of the symbols in the drawings show the same contents as the circuits or signals of the symbols having the same alphabetical portions as in FIG. The feature of this array configuration is that the arrays AR1 and AR2 in FIG. 1 are each divided into four, and data line pairs such as D111 and / D11 connected to one sense amplifier are divided.
This is because a switching nMOS controlled by the signal FC1 is inserted between the pair 1 and the pair D112 and / D112.
By doing so, for example, when a memory cell connected to a pair of D112 and / D112 is selected, D111 and / D112 are selected.
Both the 111 pair and the D112, / D112 pair must be charged and discharged, but when a memory cell connected to the D111, / D111 pair is selected, this switching nMO
When S is turned off, the charge / discharge current of the data line pair can be halved. Word line W11 in sub-array AR111 of FIG.
1 and W122 in the sub-array AR122 are selected at the same time. Alternatively, the word line W112 in the sub array AR112 and the W121 in the sub array AR121 are selected at the same time. If you decide like this,
The charge / discharge current of the data line pair to which the memory cell selected by one word line is necessarily connected becomes half of the other by turning off the switching nMOS. As a result, the charging / discharging current of the data line can be reduced to 3/4 as a whole. Details of this technique are described in JP-A-60-202596. Therefore, by using such an array structure in the present invention, the data line charging / discharging current can be further reduced. For this purpose, two such arrays are provided as shown in the figure, and the switch circuits SN and S are provided between them.
P is provided. By doing so, the charging / discharging current that becomes 3/4 is further reduced to 1/2 or less as described with reference to FIGS.
That is, it can be reduced to 3/8 or less of the conventional one.

Although the example in which the present invention is used for the refresh operation during standby of the DRAM is mainly described above, the present invention can be similarly applied to the refresh operation during standby of the pseudo SRAM. The present invention can also be applied to the read operation of a serial access memory such as an image memory in which the order of reading the memory cells is predetermined. Information to be read may be sequentially written in advance in a memory cell array in which PP and PN of two or more systems can be short-circuited. Also, D
In RAM, it can also be applied to a method of connecting two transistors in parallel to one capacitor and refreshing in parallel with reading, as described on pages 65 to 66 of the digest of 1991 SYMPOSIUM ON VLSI CIRCUITS. it can. In addition, the 1991 ISSCC digest 106th
The present invention is also applicable to a method in which the DRAM memory cells described in pages 107 to 107 are connected in series and are sequentially read.
It can also be applied to the hierarchical data line system in Japanese Patent Application No. 4-11727. Further, the present invention can be applied to the normal read operation of the DRAM without changing the essence of the present invention, and the present invention can be applied to the control circuit.

FIG. 22 is a diagram showing a system configuration using the present invention. Arrows indicate the flow of signals. M is a DRAM using the present invention, CPU is a processing device for controlling the entire system, RAG is a refresh address generating device, TC is a control signal generating device of a memory device portion using the present invention, and SLCT is a CPU. 1 shows a select device for switching between an address signal sent from the RAG and a refresh address signal sent from the RAG. The PFY is another device in the system, for example, an external storage device, a display device, a numerical operation device, or the like, and may be connected to another information processing device through a communication line including wireless communication. DATA
Represents data exchanged between the CPU and M,
Aic is the address signal generated by the CPU, Air is R
A refresh address signal generated in AG is shown.
Indicates an address signal selected by SLCT and sent to M. ST is a status signal sent from the CPU to the RAG, and BS is a busy signal from the TC to the CPU. SE
Is a signal sent from TC for activating SLCT, and / RAS and / CAS and CK are D using the present invention.
This signal activates the RAM. SG collectively represents the exchange of signals between the CPU and other devices in the system. The M may be a pseudo SRAM or the like. At this time, of course, there are corresponding start signals and control signals. When the semiconductor device according to the present invention is used, the charging / discharging current of the data line can be almost halved during the refresh operation during standby, so that the current during standby can be reduced. Therefore, it is possible to realize a small standby current that can be driven by a battery. It is also possible to apply the idea of the present invention to other devices so that the other devices in FIG. 22 can also operate with a small standby current by a sleep signal or the like from the CPU.

[0033]

According to the first data line pair and the first PN and PP connected thereto and the second data line pair and the second PN and PP connected thereto, the first and second PP and By providing the means for short-circuiting PN, the minute signal on the second data line can be amplified up to half the original amplitude by the charge of the first data line pair and the first PN and PP connected thereto. . That is, in the conventional technique, the electric charge that has been discarded by simply short-circuiting is used to perform amplification up to half the original amplitude. After that, amplification is performed by a normal sense amplifier to obtain the original amplitude.
By repeating this, the data line current can be reduced to about half that in the conventional case.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation example of the first embodiment.

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing an operation example of a second embodiment.

FIG. 5 is a diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing an operation example of the third embodiment.

FIG. 7 is a diagram showing an example of a simulation waveform.

FIG. 8 is a diagram showing an effect of the present invention.

FIG. 9 is a view showing an experimental chip photograph for verifying the present invention.

FIG. 10 is a diagram showing operation waveforms of the present invention obtained by actual measurement.

FIG. 11 is a diagram showing a configuration example of a DRAM using the present invention.

FIG. 12 is a diagram showing a first example of a block configuration of a control circuit.

FIG. 13 is a timing example in the configurations of FIGS. 11 and 12.

FIG. 14 is an example of timing for starting measurement of time tR.

FIG. 15 is a diagram showing a second example of the block configuration of the control circuit.

16 is a first timing example in the configurations of FIGS. 11 and 15. FIG.

FIG. 17 is a second timing example in the configurations of FIGS. 11 and 15.

FIG. 18 is a third timing example in the configurations of FIGS. 11 and 15;

FIG. 19 is a diagram showing another example of input signal conditions for starting the operation of the present invention.

FIG. 20 is a diagram showing the number of operation mats.

FIG. 21 is a diagram showing an example of the array configuration of the present invention.

FIG. 22 is a diagram showing a system configuration using the present invention.

FIG. 23 is a diagram showing a conventional example.

FIG. 24 is a diagram showing an example of a refresh operation of a conventional example.

FIG. 25 is a diagram showing a problem of the conventional example.

[Explanation of symbols]

AR, AR1 to AR4 ... Memory cell array, MC ... Memory cell, DMC ... Dummy memory cell, W11 to W2m ...
Word line, DW11 to DW22 ... Dummy word line, D1
1- / D1 (2n) ... data line, PC0-PC2, PC
10-PN2n-short circuit, RA11-RA2n ...
Sense amplifier, PP, PN, PP1 to PN4, PP11
-PN22 ... Common source line, DA1, DA2 ... Input / output gate, S, SP, SN, SP11 to SN12 ... Switch circuit, AM ... Data line related circuit, CLK ... Control circuit,
RF ... Refresh control circuit, ADC ... Address counter, ADC ... Y system address generation circuit, ADBuf ... Address buffer, Din Buf ... Din buffer, Do
ut Buf ... Dout buffer, Row Dec ... X
Decoder, word driver, Column Dec ... Y
Decoder driver.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masayuki Nakamura 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Shigenori Sakomura 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Inside the Center (72) Inventor Goro Tachibagawa 1-280 Higashi Koigokubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masakazu Aoki 1-280 Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi Ltd.

Claims (10)

[Claims] 1. A semiconductor memory device having a means for performing an operation of writing the same stored information as the information stored in a memory cell into the memory cell and a means for determining the start of the operation, in the m-th semiconductor memory device. A memory cell, an mth data line pair to which the mth memory cell is connected, an mth sense amplifier for amplifying a minute signal read to the mth data line pair, An n-th memory cell, an n-th data line pair to which the n-th memory cell is connected, and an n-th data line pair for amplifying a minute signal read to the n-th data line pair. A sense amplifier; an mth drive signal line for driving the mth sense amplifier; an mth switch means for connecting the mth drive signal line and a power supply line; Drive the sense amplifier of the nth A driving signal line and an n-th switch means for connecting the n-th driving signal line and the power supply line, wherein the m-th driving signal line and the n-th driving signal line are connected to each other. A semiconductor memory device characterized in that a connecting means is provided between them. 2. The semiconductor memory device according to claim 1, wherein the means for determining the start of the operation measures the time after the first input signal switches from the first potential to the second potential. A semiconductor memory device comprising means and means for generating a signal for starting the operation when a predetermined time has passed. 3. The semiconductor memory device according to claim 1, wherein the means for determining the start of the operation is the second input signal after the first input signal is switched from the first potential to the second potential. 2. A semiconductor memory device comprising: means for detecting that the first potential has been switched to the second potential. 4. The semiconductor memory device according to claim 1, further comprising address information generating means for selecting a memory cell. 5. The semiconductor memory device according to any one of claims 1 to 4, wherein the number of memory cells in which the operation is performed when the operation is performed using a means for determining the start of the operation is A semiconductor memory device characterized in that, when the operation is performed without using a means for determining the start of the operation, the number is larger than the number of memory cells in which the operation is performed. 6. The semiconductor memory device according to claim 1, wherein a period for turning off the m-th switch means and a period for turning off the n-th switch means. The semiconductor memory device is characterized in that there is an overlapping period, and the m-th driving signal line and the n-th driving signal line are connected by the connecting means during the overlapping period. 7. The semiconductor memory device according to claim 6, wherein the m-th sense amplifier amplifies a minute signal read to the m-th data line pair, and the m-th switch. After turning off the means, the connection means once connects and disconnects the mth drive signal line and the nth drive signal line, and then turns on the nth switch means to turn on the above. A semiconductor memory device characterized in that an infinitesimal signal read to the nth data line pair is amplified by an nth sense amplifier. 8. The semiconductor memory device according to claim 6, wherein after amplifying the minute signal read to the n-th data line pair, the n-th switch means is turned off and the connection is further established. Means for connecting the m-th drive signal line and the n-th drive signal line once and then disconnecting them, and then turning on the m-th switch means to turn on the m-th sense amplifier by the m-th sense amplifier. A semiconductor memory device characterized by amplifying a minute signal read to an m-th data line pair. 9. The semiconductor memory device according to claim 1, wherein the mth memory cell and the nth memory cell each include one transistor and one capacitor. A semiconductor memory device characterized by: 10. The semiconductor memory device according to claim 1, wherein another chip control signal, an address signal, or data is taken into the chip and the chip is synchronized with a clock input to the chip. A semiconductor memory device characterized in that data is taken out from the semiconductor memory device.