JP3434753B2 - Data transfer circuit for semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION A data transfer circuit for a semiconductor memory circuit according to the present invention selects a desired one from the amplified sense amplifiers by opening and closing a switch,
It relates to high speed data transfer to a read line.

[0002]

2. Description of the Related Art In recent years, with an increase in capacity of semiconductor memory devices, an increase in the number of switches connected to a read line and an increase in area have led to an increase in junction capacitance and wiring capacitance, which results in deterioration of data transfer time and thus access time. It became a problem and needed improvement. In order to meet this demand, for example, as disclosed in Japanese Patent Laid-Open No. 7-6584, the output of the sense amplifier is latched by a line buffer composed of an inverter flip-flop, and the output is input to the gate and the source is grounded. A method has been proposed in which the drain is used as the source of the column selection signal switch and the drain is connected to the read line.

The technique disclosed in the document showing this prior art is shown in FIG. 7, in which the sense amplifier 101 includes NMOS transistors 103 and 10 forming a transfer switch circuit via a pair of bit lines 120 and 121.
4 is connected. The NMOS transistors 103 and 104 forming the transfer switch circuit are switches controlled by the data transfer control signal Φ152,
It is composed of NMOS transistors 103 and 104 which function as data transfer gates. The gates of the NMOS transistors 103 and 104 are connected to the data transfer control signal line 152, respectively. One terminal of the transistors 103 and 104 has a bit line pair 1
20 (121), the other terminal is the line buffer circuit 1
06 output node 122 (123). The line buffer circuit 106 is formed by a flip-flop circuit, and the output node 122 and the output node 123 are driven by the output data of the sense amplifier. The NMOS transistors 107 and 109 that form the buffer circuit are drive-controlled by the potential of the output node 122 or 123.

The read data buses 124 and 125 are equalized to a predetermined level in advance. NMOS transistor 10 forming an output switch circuit
Reference numerals 8 and 110 are composed of NMOS transistors 108 and 110 functioning as column selection gates driven by column selection lines. When the column selection line 158 is at "H" level, the output switch circuit 20 outputs the data output from the NMOS transistors 107 and 108 forming the buffer circuit to the read data buses 124 and 125.

[0005]

In the above structure, the switch for connecting the bit line of the sense amplifier section and the bit line of the line buffer section must be turned off until the activation of the sense amplifier is completed. There is a drawback that the data of the sense amplifier is destroyed by the data latched by. Furthermore, until the data of the sense amplifier is latched in the line buffer, the switching transistor which receives the column selection signal as an input must be turned off by a delay element for a certain period of time to cause a malfunction. . FIG. 8 is a timing chart when the structure of this prior art is applied to a semiconductor memory device. The delay time from the internal clock CLK to the external data output terminal DO was 3.2 ns. A main object of the present invention is to provide a semiconductor memory device which transfers data of only a selected sense amplifier among a plurality of sense amplifiers to a read line in association with activation of the sense amplifier.

[0006]

A data transfer circuit for a semiconductor memory device according to the present invention includes a row selection decoder for selecting a row address of a memory cell matrix, and a column selection decoder for selecting a column address of the memory cell matrix. A row address decoder that transfers row address data to the row selection decoder, a column address decoder that transfers column address data to the column selection decoder, and an output signal of the column selection decoder from a bit line pair in the memory cell matrix. A column selection switch that selects a unique bit line pair and propagates data to the sense amplifier section switch; and a row selection decoder and a column selection switch connected to two or one memory cell matrix. The minute difference potential of the memory cell selected by the decoder is connected to the memory cell. Propagated to the sense amplifier unit bit line pair and the bit line pairs and said column selection switch via said sense amplifier unit switch, and the memory block composed of a sense amplifier for amplifying a minute difference voltage of the memory cell,
A block selection circuit for selecting a unique memory block from a plurality of the memory blocks, a write amplifier block for transferring write data to the memory cell matrix, a data input block for transferring write data to the write amplifier, and the sense circuit. A sense amplifier selection signal for selecting an amplifier, a sense amplifier activation signal for activating the sense amplifier, a bit line pair output from the memory cell matrix, and a sense amplifier section bit line pair of the sense amplifier are connected. A sense amplifier section selection switch, an equalizer circuit for equalizing and precharging the sense amplifier section bit line, an equalizer control signal for controlling the equalizer circuit, and a sense amplifier for inputting each of the sense amplifier section bit line pairs. Section inverter pair and A pair of drive elements having the amplifier section inverter pair as the gate input, the source being grounded and the drain being the read line pair, and the read line pair precharge element having the equalization signal as the input, the source as the power supply, and the drain as the read line pair, It is composed of a data output block that receives the read line pair and a control block that controls the element group, and it is premised that there are a plurality of the memory blocks. Inputting to the drive element pair of the read line pair.

Further, the signal obtained by ANDing the sense amplifier selection signal and the sense amplifier activation signal,
It is characterized in that a unique memory block is selected from the plurality of existing memory blocks, a sense amplifier in the selected memory block is activated, and at the same time, data transfer to the data read line pair is performed in conjunction with each other. When the read operation is not performed, the sense amplifier section bit line pair holds the power supply level, and when the read operation is performed, the sense amplifier section bit line pair is floated and selected by the equalizer control signal and the equalizer circuit. The minute difference potential of the memory cell is propagated. When the difference potential of the sense amplifier section bit line pair becomes a desired value, the sense amplifier is activated by the sense amplifier activation signal, the minute difference potential is amplified, and one side of the sense amplifier section bit line pair is amplified. Is set to the power supply level and the other is set to the ground level, and at the same time, the sense amplifier section selection switch is cut off to stop the signal propagation to the bit line pair of the memory cell. In the complementary read line pair, one of the read lines and the first 2
A second two-input NAND whose output is the input NAND
And the data driven from the pair of drive elements is latched by a flip-flop configured by a first two-input NAND which receives the output of the other two read lines and a second two-input NAND. . Further, the anti-phase signal of the output of the second 2-input NAND of the flip-flop is used as an external output terminal. In the sense amplifier, one of the sense amplifier section bit line pairs is input to a first 2-input NOR, and the other of the sense amplifier section bit line pairs is input to a second 2-input NOR. The delay signal of the logical product of the activation signal and the sense amplifier selection signal is the first delay signal.
Connected to unconnected inputs of the two-input NOR and the second two-input NOR, the inverter pair is replaced with the first and second two-input NOR pairs, and the first and second two-input NOR are connected.
The output of the pair is input to the drive element pair.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a data transfer circuit showing the configuration of the first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the NAND circuit 1 that receives the sense amplifier activation signal ΦS and the sense amplifier selection signal ΦC0 as input.
And an inverter 2 that receives the output of the NAND circuit 1 as an input
And an inverter 3 which receives the output of the inverter 2 as an input,
An inverter 4 which receives the output of the inverter 3 and outputs the sense amplifier activation delay signal ΦSS, and a bit line pair DT which receives the sense amplifier activation delay signal ΦSS as a gate input
And a transistor 5 for connecting the sense amplifier section bit line ST, a transistor 6 for connecting the bit line pair DB and the sense amplifier section bit line SB with the sense amplifier activation delay signal ΦSS as a gate input, and a bit line equalizer control signal ΦP. NAN to which sense amplifier selection signal ΦC0 is input
A D circuit 28, an inverter 29 that receives the output of the NAND circuit 28 as an input and outputs a bit line equalizer signal ΦSP, and a transistor 7 that connects the bit line equalizer signal ΦSP to the gate input and connects the sense amplifier section bit line ST to the power supply level. And the bit line signal ΦSP of the sense amplifier section
Is used as a gate input, and the sense amplifier section bit line SB is connected to the transistor 8 and the bit line equalizer signal ΦSP is used as a gate input.
The transistor 9 connecting T and SB and the sense amplifier activation delay signal ΦSS are input to the gate of the transistor 15, and the sense amplifier section bit line signal ΦST and the sense amplifier section bit line are constituted by the transistors 11, 12, 13, and 14. Sense amplifier SA that amplifies the potential difference of the signal ΦSB
And an inverter 16 that inputs the sense amplifier section bit line signal ΦST and outputs the signal inverter output signal ΦTO
And an inverter 17 that receives the sense amplifier section bit line signal ΦSB as an input and outputs an inverter output signal ΦBO,
A transistor 18 which uses the inverter output signal ΦTO as a gate input and connects the read line pair signal ΦRB to the ground level.
And a transistor 19 for connecting the read line pair RT to the ground level with the inverter output signal ΦBO as a gate input.
, And transistors 21 and 22 that receive the bit line equalizer control signal ΦP as input and connect the read line pair signals ΦRT and ΦRB to the power supply level, respectively, and the read line pair signal ΦR.
A transistor 23 that inputs B to connect the read line pair RT to the power supply level, a transistor 24 that inputs the read line pair signal ΦRT to connect the read line pair RB to the power supply level, a read line pair signal ΦRB and the NAND circuit 25.
Output signal ΦLB of the NAND circuit 26, the read line pair signal ΦRT and the output signal Φ of the NAND circuit 26.
NAND circuit 25 that receives LT and NAND circuit 2
When the sense amplifier activation signal ΦS is at a low level, the sense amplifier section bit line signal ΦST and the bit line pair signal ΦDB are both at the power supply level. When the bit line equalizer control signal ΦP goes high due to the holding and reading states, the bit line equalizer circuit formed by the transistors 7, 8 and 9 is turned off,
After a difference potential is generated between the complementary bit line bit line pair signals ΦDT and ΦDB, the sense amplifier is activated by the change of the sense amplifier activation signal ΦS, and the sense amplifier section bit line signal ΦST or the sense amplifier section bit line signal ΦSB Either of them becomes the ground level, whereby the inverter output signal ΦTO or the inverter output signal ΦBO becomes the high level, and the read line pair signal ΦRT or the read line pair signal ΦRB becomes the ground level.

FIG. 2 is a functional block diagram showing an embodiment in which the data transfer circuit shown in FIG. 1 is applied to a semiconductor memory device. In addition, the portion surrounded by the broken line in FIG.
Shows the configuration range of. The control block 50 controls writing when the write signal WEB is at low level and controls reading when the write signal WEB is at high level in response to the rise of the external control signal CLKEX. The row address decoder 71 takes in the external row address signal Ax under the control of the control block 50, and the column address decoder 72 takes in the external column address signal Ay. The row selection decoders 51 and 54 select a row address corresponding to the address of the row address decoder in synchronization with the external control signal CLKEX.

The column selection decoders 52 and 55 select a column address corresponding to the address of the column address decoder 72 in synchronization with the external control signal CLK. Block selection circuit 53,
Reference numeral 56 outputs a signal that is the logical product of the highest-order address signal output from the row address decoder 71 and the control signal from the control block 50. The sense amplifier block 62 and write amplifier 63 or the sense amplifier block 66 and write signal are output. Any one of the amplifiers 67 is selected.

At the time of reading, when the row selection decoder 51 is selected, the row address of the memory cell matrix 60 is selected, the memory cell data of the selected row address is output to the bit line pair, and further to the column selection decoder 52. The corresponding column selection switch 61 is opened, and the data of the memory cell 60 is transferred to the sense amplifier block 62.

Similarly, when the row selection decoder 54 is selected, the row address of the memory cell matrix 64 is selected,
The memory cell data of the selected row address is output to the bit line pair, the column selection switch 65 corresponding to the column selection decoder 55 is opened, and the data of the memory cell is transferred to the sense amplifier block 66. The signal lines of the column selection switches 61 and 65 are complementary signal line pairs, and the sense amplifier block 6
2 or the sense amplifier block 66 is selected, the differential potential of the complementary signal line is amplified and the read line pair R
Transfer to. The precharge circuit 68 includes the control block 5
The read line pair R is precharged in synchronization with the internal clock CLK output from 0. Internal clock CLK
Is low, the read line pair R is held at a high level. When the internal clock CLK is at a high level, the supply of electric charges from the power supply to the read line pair R is stopped and the read line pair R is brought into a floating state.

The data output block 70 outputs the read line pair signal ΦR from the external output terminal DO in synchronization with the internal clock CLK. The data input block 73 transfers the data taken in from the external input terminal DI to the data read line pair R. When the write amplifier 63 is selected by the block selection circuit 53, the data of the read line pair R is transferred by opening the column selection switch 61 of the column address corresponding to the column selection decoder 52 in synchronization with the internal clock CLK. Data is written in the memory cell of the row address of the memory cell matrix 60 selected by the row selection decoder 51.
The same applies when the write amplifier 67 is selected by the block selection circuit 56. In the functional block diagram of FIG. 2, the read line pair R is shared at the time of reading and at the time of writing, but it may be provided independently according to the purpose.

The operation of this embodiment will be described below with reference to FIGS.
Will be explained. In FIG. 1, the bit line equalizer control signal ΦP is an in-phase signal of the internal clock CLK, and when the internal clock CLK is low level, the transistors 21 and 2 are connected.
2 is turned on and read line pair signals ΦRT and ΦRB
Is set to a high level, and when the internal clock CLK is low level, the transistors 21 and 22 are turned off, and the read line pair signals ΦRT and ΦRB are set to a floating state. Similarly, the sense amplifier activation signal ΦS is also the internal clock CL.
Although it is the in-phase signal of K, it has a delay larger than the number of stages of the normal element with respect to the rising change of the internal clock CLK, but has a delay similar to the number of stages of the normal element with respect to the falling change of the internal clock CLK. Is set to. The sense amplifier selection signal ΦC0 is synthesized by the row address decoder signal and becomes high level when selected.

The bit line equalizer signal ΦSP is the bit line equalizer control signal ΦP and the sense amplifier selection signal ΦC0.
Is a signal obtained by taking the logical product of, and the transistor 7 which is at the low level during the standby period and constitutes the bit line equalizer circuit,
8 and 9 are turned on to equalize and precharge the bit line signal pair signals ΦST and ΦSB in the sense amplifier block. At the time of reading, the bit line equalizer control signal ΦP becomes high level in synchronization with the bit line equalizer circuit. The transistors 7, 8 and 9 constituting the transistor are turned off to put the sense amplifier section bit line signals ΦST and ΦSB in a floating state.

The sense amplifier activation delay signal .PHI.SS becomes low level in the standby state, turning off the transistor 15 to turn off the sense amplifier and turning on the transistors 5 and 6 to turn on the bit of the column selection switch 61. The line pair ΦDT and ΦDB is connected to the sense amplifier section bit line signal pair ΦST and ΦSB. The delay inverters 2 and 3 read the bit line pair signals ΦST and ΦS during reading.
The delay time is set so that the sense amplifier activation delay signal ΦSS becomes high level when the difference potential of B reaches a desired value. When the sense amplifier activation delay signal ΦSS becomes high level, the bit line pair In order to eliminate the influence of the wiring capacitance of the signals ΦDT and ΦDB, the transistors 5 and 6 are turned off and the transistor 15 is turned on to activate the sense amplifier, and the bit line pair ΦST and ΦST.
A difference potential of several tens of mV of SB is amplified to a power supply level and a ground level.

The inverter output signals ΦTO and ΦBO are at the ground level in the standby state, and the transistors 18 and 1
9 is turned off, and at the time of reading, one of the sense amplifier section bit line pair signals ΦST and ΦSB becomes the ground level due to the rise of the sense amplifier activation delay signal ΦSS, and the bit line signal at the ground level side is input. Inverter output ΦTO or ΦBO becomes high level, and the charge of the read line pair signal ΦRT or ΦRB is discharged. At this time, either the transistor 23 or 24 whose gate input is the discharge line on the discharged side is turned on, and the high level of the read line on the undischarged side is held. NAN
The latch circuit constituted by the D circuits 25 and 26 holds the value of the output terminal DO when the internal clock CLK is at a low level and prevents the output terminal DO from outputting an uncertain value due to a rising change of the internal clock CLK. It is provided to do so. The inverter 27 is set so as to ensure a sufficient driving capability even if the output terminal DO is connected to a wiring or the like having a parasitic capacitance of several PF.

Based on the above, description will be made with reference to the timing chart of FIG. Internal clock CL at time T0
K, bit line equalizer control signal ΦP, sense amplifier selection signal ΦC0, sense amplifier activation signal ΦS, bit line equalizer signal ΦSP, sense amplifier activation delay signal Φ
SS, inverter output signal ΦTO, inverter output signal ΦBO are low level, bit line pair signals ΦDT, ΦDB,
The sense amplifier section bit line pair ΦST and ΦSB and the read line pair ΦRT and ΦRB have a high level, and the external row address signal Ax, the external column address signal Ay, and the external output terminal DO have arbitrary values. However, to explain the operation, the inverter 27
And the NAND circuit output signal Φ of the latch NAND circuit 26
Both LT are low level, and the NAND circuit output signal ΦLB of the NAND circuit 25 is high level.

External row address signal A at time T1
x, the external column address signal Ay changes. At time T2, the sense amplifier selection signal ΦC0 changes from the low level to the high level in response to the change of the row address decoder.
At time T3, the internal clock CLK changes from low level to high level. At time T4, the bit line equalizer control signal ΦP changes from the low level to the high level, and the read line pair signals ΦRT and ΦRB become the floating level. In addition, the bit line equalizer control signal ΦP
Change the bit line equalizer signal ΦSP from low level to high level at time T5, causing the sense amplifier section bit line signals ΦST and ΦSB to be in a floating state. At time T5, a potential difference starts to be generated between the bit line pair signals ΦDT and ΦDB according to the cell data of the memory matrix selected by the row selection decoder and the column selection decoder. The bit line on the side

At time T6, the potential of the sense amplifier section bit line pair signal ΦSB starts to drop from the power supply level and a potential difference starts to be generated between the sense amplifier section bit line signal ΦSB and the sense amplifier section bit line signal ΦST. At time T7, the sense amplifier activation signal ΦS changes from low level to high level. This change in the sense amplifier activation signal φS changes the sense amplifier activation delay signal φSS at a predetermined time. At time T8, the potential of the signal ΦSB begins to drop from the power supply level and the potential difference between the signal ΦSB and the sense amplifier bit line signal ΦST reaches a desired value, and at the same time, the sense amplifier activation delay signal ΦSS changes from low level to high level and the sense amplifier is activated. Are activated, and the potential of the sense amplifier section bit line signal ΦSB starts to drop sharply at time T9 and reaches the ground level.

At time T10, the output of the inverter 17 receiving the sense amplifier section bit line signal ΦSB changes from low level to high level, turning on the transistor 19. On the other hand, the sense amplifier block bit line signal Φ
Since ST is a power supply level, the inverter output signal ΦTO of the inverter 16 which receives the sense amplifier section bit line signal ΦST holds a low level, and the transistor 18 maintains an off state. At time T11, since the transistor 19 is on, the charge of the read line signal ΦRB is discharged, and the potential drops from the high level to the ground level. On the other hand, the read line pair signal ΦRT was in a floating state near the high level because the transistor 18 was in the OFF state, but the potential of the read line pair signal ΦRB was at the ground level, so that the transistor 23 was in the ON state and the charge was supplied from the power supply. receive.

At time T12, the read line pair signal ΦR
Since B becomes the ground level, the output signal ΦLT of the NAND circuit 26 changes from the low level to the high level, and N
The NAND circuit output signal ΦLB of the AND circuit 27 changes from high level to low level. At time T13, the external output terminal signal DO of the inverter 27 changes from low level to high level, and the data reading of the memory cell is completed. When the internal clock CLK changes from high level to low level at time T14, the bit line equalizer control signal ΦP also changes from high level to low level at time T15.

At time T16, the read line pair precharge transistors 21 and 22 are turned on, and the read line pair signal ΦRB changes from low level to high level in response to the supply of electric charges from the power supply. As a result, the NAND circuit 25 latches the low level. At time T17, when the sense amplifier activation delay signal ΦSS changes from the high level to the low level, at time T18, the bit line pair signal Φ
DB and the bit line pair signal ΦSB change from low level to high level. At time T19, the sense amplifier section bit line signal ΦSB becomes high level, so that the inverter output signal ΦBO of the inverter 17 changes from high level to low level, turning off the transistor 19.

From the above, the bit line equalizer circuit is provided in the sense amplifier section SA, and the output signals ΦTO and ΦB of the inverter which receives the bit line pair ST and SB respectively.
O is input to the gates of the switching transistors 18 and 19 that connect the read lines RT and RB to the ground level. In the standby state, the bit line pair ST, SB and the read line pair RT, RB are set to high level. Further, since the outputs of the inverters 16 and 17 having the bit line pair ST and SB as inputs are at the ground level, the switching transistor 18 and
19 is an off state. When reading is started, the bit line equalizer circuit and the precharge circuit of the read line pair are turned off, the complementary bit line pair and data line pair of the sense amplifier are set in the floating state, and then a potential difference is generated in the bit line pair. The rising of the sense amplifier activation signal ΦS activates the sense amplifier, and only one side of the bit line pair becomes the ground level. The output of the inverter that receives the bit line on the side of the ground level becomes high level, the switch transistor is turned on, and the read line connected to this transistor becomes the ground level. Therefore, the data of the sense amplifier can be transferred to the read line in association with the activation of the sense amplifier, and the effect of speeding up the data transfer can be obtained.

FIG. 4 is a circuit diagram showing the configuration of the second embodiment of the present invention. As shown in FIG. 4, in this embodiment, the sense amplifier block is further devised. In FIG. 4, the inverters 16 and 17 of FIG.
The NOR circuit 3 is replaced with the R circuit 34 and the NOR circuit 35.
4. An inverter 31 that receives the sense amplifier activation delay signal ΦSS for controlling the NOR circuit 35, an inverter 32 that receives the output of the inverter 31, and a read line pair discharge transistor that receives the output of the inverter 32 as an input. An inverter 33 that outputs the switch signal ΦN is provided.

The inverters 16 and 17 are connected to the NOR circuit 34,
The purpose of replacing with the NOR circuit 35 is that when the sense amplifier activation delay signal ΦSS changes from low level to high level in FIG. 1, the sense amplifier section bit line pair ΦST and ΦSB are momentarily supplied with the power supply voltage when the sense amplifier is activated. Of the inverters 16 and 17 at the next stage from the low level to the high level, the transistors 18 and 19 are turned on, and the read line pair signal ΦR
This is to make the NOR circuit 34 and the NOR circuit 35 ready for operation at the time when the activation of the sense amplifier is completed, in order to avoid a malfunction such as discharging the charges of T and ΦRB.

The operation will be described below with reference to the timing chart shown in FIG. At time T0, the internal clock CLK, the bit line equalizer control signal ΦP, and the sense amplifier selection signal Φ
C0, sense amplifier activation signal ΦS, bit line equalizer signal ΦSP, sense amplifier activation delay signal ΦSS, N
OR circuit output signals ΦTO and ΦBO are low level, bit line pair signal ΦDT, bit line pair signal ΦDB, sense amplifier section bit line pair ΦST, sense amplifier section bit line signal ΦS
B, the read line pair discharge transistor switch signal ΦN, and the read line pair signals ΦRT and ΦRB are high levels, and the external row address signal Ax, the external column address signal Ay, and the external output terminal signal DO are arbitrary values. However, to explain the operation, the inverter 27 and the latch NAN
The output signals ΦLT of the D circuit 26 are both low level and NAN.
The output signal ΦLB of the D circuit 25 is at a high level.

External row address signal A at time T1
x, the external column address signal Ay changes. At time T2, the sense amplifier activation signal ΦC0 changes from the low level to the high level in response to the change of the row address decoder. At time T3, the internal clock CLK changes from low level to high level. At time T4, the bit line equalizer control signal ΦP changes from the low level to the high level, and the read line pair signals ΦRT and ΦRB become the floating level. The change of the bit line equalizer control signal ΦP changes the bit line equalizer signal ΦSP from low level to high level, and the sense amplifier section bit line pair signals ΦST and ΦSB are made floating. On the other hand, the bit line pair signals ΦDT and Φ according to the cell data of the memory matrix selected by the row selection decoder and the column selection decoder.
Although a differential potential starts to be generated in DB, it is assumed here that the bit line on the side where the bit line pair signal ΦDB is at the low level for the purpose of explanation of the operation.

At time T6, the potential of the sense amplifier section bit line pair signal ΦSB starts to drop from the power supply level and a potential difference starts to be generated between the sense amplifier section bit line pair signal ΦSB and the sense amplifier section bit line signal ΦST. At time T7, the sense amplifier activation signal ΦS changes from low level to high level. This change in the sense amplifier activation signal φS changes the sense amplifier activation delay signal φSS at a predetermined time. At time T8, the sense amplifier section bit line signal ΦSB follows the potential of the bit line pair signal ΦDB and starts to drop from the high level, and at the same time when the potential difference from the sense amplifier section bit line signal ΦST reaches a desired value. The sense amplifier activation delay signal ΦSS changes from low level to high level and the sense amplifier is activated. As a result, at time T9, the potential of the sense amplifier section bit line signal ΦSB suddenly drops to the ground level.

At time T10, when the switch signal ΦN of the read line pair discharge transistor changes from the high level to the low level, the NOR circuit 3 which receives the sense amplifier section bit line signal ΦSB at time T11.
The NOR circuit output signal ΦBO of 5 changes from the low level to the high level, turning on the transistor 19. On the other hand, since the sense amplifier section bit line signal ΦST is at the power supply level, the NOR circuit output signal ΦT which is the output of the NOR circuit 34 to which the sense amplifier section bit line signal ΦST is input.
O holds the low level, and the transistor 18 maintains the off state. At time T12, since the transistor 19 is in the on state, the charge of the read line pair signal ΦRB is discharged, and the potential drops from the high level to the ground level. On the other hand, the read line pair signal ΦRT is the transistor 1
Although 8 is in the OFF state and is floating near the high level, the potential of the read line pair signal .PHI.RB is at the ground level, so that the transistor 23 is in the ON state and the charge is supplied from the power supply.

At time T13, the read line pair signal ΦR
The output signal ΦLT, which is the output of the NAND circuit 26, changes from the low level to the high level due to the B being at the ground level, and the output signal ΦLB of the NAND circuit 27 changes from the high level to the low level. At time T14, the external output terminal signal DO of the inverter 27 changes from low level to high level, and the data reading of the memory cell is completed.

When the internal clock CLK changes from the high level to the low level at time T15, the bit line equalizer control signal ΦP and the sense amplifier activation signal ΦS change from the high level to the low level at time T16. At time T17, the precharge transistors 21 and 22 of the read line pair are turned on due to the change of the bit line equalizer control signal ΦP, and the read line pair signal ΦRB is supplied with electric charge from the power source and changes from low level to high level. The circuit 25 latches the low level. On the other hand, the change in the bit line equalizer signal ΦSP causes the sense amplifier section bit line pair signals ΦST and ΦSB to be equalized and precharged. Similarly, the bit line pair signals ΦDT and ΦDB are also equalized and precharged. At time T18, when the sense amplifier activation delay signal ΦSS changes from the high level to the low level, the switch signal ΦN of the read line pair discharge transistor changes from the low level to the high level at time T19. Further, at T19 at the same time, the sense amplifier section bit line signal ΦSB becomes high level, and at time T20, the output signal ΦBO of the NOR circuit 35 changes from high level to low level, turning off the transistor 19. As described above, in the present embodiment, compared to the first embodiment, it is possible to obtain the effect of completely preventing a malfunction with respect to a waveform mismatch operation.

[0033]

As described above, the first effect of the present invention is that the constant current source is provided in the sense amplifier section and the activation of the sense amplifier can be controlled. The transistors that make up the bit line pair are set to the high level together, and the transistors that make up the bit line equalizer circuit are turned off, and the sense amplifier is activated when reading. Since only one side of the pair is at the ground level, it is possible to directly input the reverse phase signal of each bit line to the switch that grounds the read line, so data transfer from the sense amplifier activation to the read line is continuous. Therefore, the speed can be increased. FIG. 6 is a timing chart when the first embodiment is applied to a 1024 word 16-bit semiconductor memory device having a gate length of 0.18 μm. The delay time from the internal clock CLK to the external data output terminal DO is 2.6 ns. FIG. 9 is a timing diagram when applied to the conventional semiconductor memory device shown in FIG. 8. The delay time from the internal clock CLK to the external data output terminal DO is 3.2 ns. From this result, according to the present invention, the speed can be increased by about 19% as compared with the conventional one.

The second effect is that the control signal and the circuit configuration are simplified and the area can be reduced. A third effect is that only a sense amplifier selected from among a plurality of sense amplifiers operates by a signal obtained by taking a logical product of a sense amplifier activation signal and a sense amplifier selection signal, so that unnecessary current consumption can be reduced. It can be achieved. The fourth effect is that the read line pairs are complemented and each output is latched by the flip-flop of the 2-input NAND circuit, so that even if the external synchronous control signal operates in the state where the external address does not change, The external output can hold the data of the memory cell matrix of the changed external address, and the semiconductor memory device to which the present invention is applied has the effect of facilitating the system design.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a data transfer circuit according to the present invention.

FIG. 2 is a functional block diagram of a semiconductor memory device to which the first embodiment of the data transfer circuit according to the present invention is applied.

FIG. 3 is a timing chart showing the operation of the first embodiment of the data transfer circuit according to the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of a data transfer circuit according to the present invention.

FIG. 5 is a timing diagram showing the operation of the second embodiment of the data transfer circuit according to the present invention.

FIG. 6 is a timing chart for explaining the effect of applying the first embodiment of the present invention.

FIG. 7 is a data transfer circuit diagram of a conventional example.

FIG. 8 is an explanatory timing chart when a data transfer circuit of a conventional example is applied.

[Explanation of symbols]

1, 25, 26, 28 NAND circuits 2-4, 16, 17, 27, 29, 31-33 Inverters 5-9, 11-15, 18, 19, 21-24 Transistors 34, 35 NOR circuit 50 Control block 51 , 54 row selection decoder 52, 55 column selection decoder 53, 56 block selection circuit 60, 64 memory cell matrix 61, 65 column selection switch 62, 66 sense amplifier block 63, 67 write amplifier 68 precharge circuit 70 data output block 71 rows Address decoder 72 Column address decoder 73 Data input block 101 Sense amplifiers 102 to 105 Transistor 106 Line buffer circuits 107 to 113 Transistor 114 Data output circuits 124 and 125 Read data bus ΦS Sense amplifier activation signal ΦC0 Sense amplifier Selection signal ΦSS Sense amplifier activation delay signal ΦDT, ΦDB Bit line pair signal ΦST, ΦSB Sense amplifier block bit line signal ΦSP Bit line equalizer signal ΦP Bit line equalizer control signal ΦTO, ΦBO Inverter output signal ΦRT, ΦRB Read line pair signal ΦLB , ΦLT Read line pair signal or NAND output signal ΦN Switch signal ΦR Read line pair signal CLK Internal clock CLKEX External control signal Ax External row address signal Ay External column address signal DO External output terminal DI External input terminal DB Bit line pair DT Bit line pair RB read line pair RT read line pair SA sense amplifier SB sense amplifier section bit line ST sense amplifier section bit lines T1 to T19 time WEB write signal Φ120, Φ121 bit line pair signal Φ122, Φ123 output node Φ124, Φ1 25 Read data bus signal Φ151 Bit line equalizer control signal Φ152 Data transfer control signal Φ153 Column line selection signal Φ154 Read data bus equalize control signal

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/409 G11C 11/419

Claims (6)

(57) [Claims] 1. A row selection decoder for selecting a row address of a memory cell matrix, a column selection decoder for selecting a column address of the memory cell matrix, and a row address decoder for transferring row address data to the row selection decoder. A column address decoder that transfers column address data to the column selection decoder, and a unique bit line pair is selected from the bit line pairs in the memory cell matrix by an output signal of the column selection decoder and the data is supplied to the sense amplifier section switch. A column selection switch that propagates and a memory cell matrix connected to two or one memory cell matrix, and a minute difference potential between the memory cells selected by the row selection decoder and the column selection decoder in the memory cell matrix is applied to the memory cell. The connected bit line pair, the column selection switch, and the sense amplifier section switch. A memory block composed of a sense amplifier that propagates to the bit line pair of the sense amplifier via the switch and amplifies a minute potential difference of the memory cell, and a unique memory block is selected from a plurality of the memory blocks. A block selection circuit, a write amplifier block for transferring write data to the memory cell matrix, a data input block for transferring write data to the write amplifier, and a sense amplifier selection signal for selecting the sense amplifier,
A sense amplifier activation signal for activating the sense amplifier; a sense amplifier section selection switch for connecting a bit line pair output from the memory cell matrix and a sense amplifier section bit line pair of the sense amplifier; An equalizer circuit for equalizing and precharging a partial bit line, an equalizer control signal for controlling the equalizer circuit, a sense amplifier section inverter pair for inputting each of the sense amplifier section bit line pairs, and the sense amplifier section inverter A pair of gate inputs, a source of which is grounded and a drain of which is a read line pair; a drive element pair of which the equalization signal is input, a source of which is a power supply and a drain of which is a read line pair; A data output block with a pair of inputs and the above elements A group of control blocks for controlling a group, and assuming that there are a plurality of memory blocks, a negative phase signal of the sense amplifier section bit line pair is input to the drive element pair of the read line pair. Data transfer circuit of semiconductor memory device. 2. A unique memory block is selected from a plurality of the memory blocks existing in accordance with a signal obtained by taking a logical product of the sense amplifier selection signal and the sense amplifier activation signal, and sense in the selected memory block is selected. 2. The data transfer to the data read line pair is performed in conjunction with the activation of the amplifier at the same time.
A data transfer circuit of the semiconductor memory device described. 3. When the read operation is not performed, the sense amplifier section bit line pair holds the power supply level, and when the read operation is performed, the sense amplifier section bit line pair is brought into a floating state by the equalizer control signal and the equalizer circuit. ,
The minute difference potential of the selected memory cell is propagated. When the difference potential of the sense amplifier section bit line pair becomes a desired value, the sense amplifier is activated by the sense amplifier activation signal, the minute difference potential is amplified, and one side of the sense amplifier section bit line pair is amplified. At a power supply level and the other at a ground level, at the same time, the sense amplifier section selection switch is cut off to stop signal propagation to the bit line pair of the memory cell.
A data transfer circuit of the semiconductor memory device described. 4. A second two-input NAND which receives one of the read lines and an output of the first two-input NAND in the complementary read line pair, and the other read line and the second two. 2. The data transfer circuit for a semiconductor memory device according to claim 1, wherein the data driven from the drive element pair is latched by a flip-flop composed of a first 2-input NAND which receives an output of the input NAND. . 5. The data transfer circuit of a semiconductor memory device according to claim 4 , wherein a negative phase signal of an output of said second two-input NAND of said flip-flop is used as an external output terminal. 6. In the sense amplifier, one of the sense amplifier section bit line pair is input to a first two-input NOR, and the other of the sense amplifier section bit line pair is input to a second two-input NOR. A delay signal of a signal obtained by ANDing the sense amplifier activation signal and the sense amplifier selection signal is connected to unconnected inputs of the first two-input NOR and the second two-input NOR, and the inverter pair is connected. Is replaced with the first and second 2-input NOR pair, and the first and second 2
2. The data transfer circuit for a semiconductor memory device according to claim 1, wherein the output of the input NOR pair is input to the drive element pair.