JP3596937B2 - Semiconductor storage device - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor memory device.In placeIn particular, a writing time can be reduced, and a low power consumption static semiconductor memory device (hereinafter referred to as an SRAM).)Related.
[0002]
[Prior art]
As a conventional technique related to writing in an SRAM, for example, a technique described in Japanese Patent Application Laid-Open No. 05-166376 is known.
[0003]
FIG. 10 is a time chart for explaining the write operation of the SRAM of the prior art. Hereinafter, the write operation of the SRAM of the prior art will be described with reference to FIG. In FIG. 10, AD is an external address signal, WE is an external write signal, Din is an external write data, W is an internal write signal, and D is an internal write data. Note that ￣ indicates the negation of the signal shown before it, and the same applies in the following description.
[0004]
Writing to the SRAM according to the prior art takes t_WAS After a lapse of time, the external write signal WE # is asserted and falls, and the internal write signal WE becomes a predetermined time t after the fall of the external write signal WE #._d Falling down with a delay, the predetermined writing time t_wpIs ensured, and is started in response to the rise of the external write signal WE #. Note that the external write signal WE #ButIt is started at the end of the write cycle. Also, the writing time t_wpIs determined by adding a predetermined margin in consideration of various fluctuation factors such as the capacity size of a storage device, characteristics of a write amplifier, write characteristics of a memory cell, power supply voltage fluctuation, temperature fluctuation, and process fluctuation.
[0005]
[Problems to be solved by the invention]
As described above, the internal write signal W # in writing to the SRAM in the related art rises in response to the rise of the external write signal WE # that rises at the end of the write cycle. Memory cycle. For this reason, in the prior art described above, when the next memory cycle is a read cycle, recovery from a large-amplitude signal to a memory cell at the time of writing to a small-amplitude signal at the time of reading is delayed, and the read access time is significantly increased. This causes a problem.
[0006]
Also, the above-mentioned prior art has an internal write time t_wpIn consideration of various fluctuation factors, a considerable margin is provided from the actual write operation time, so that the time from the completion of data writing to the memory cell to the end of the write cycle is wasted. Therefore, there is a problem that a large write current continues to flow and power consumption at the time of writing increases. This is a major obstacle to reducing power consumption, especially in wide-bit memories such as x32 bits and x64 bits.
[0007]
Also, in the above-described conventional technology, the write request isIssueDuring this time, it is not possible to respond to requests such as disabling the write operation by controlling the operation of the write control circuit, and it is difficult to expand the application of the storage device. .
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, prevent the end of a write operation from penetrating into the next memory cycle, reduce power consumption, and improve the application of a storage device. To provide an expandable semiconductor memory deviceRukoAnd there.
[0009]
[Means for Solving the Problems]
According to the present invention, the object is:
A write end detection unit that receives a signal of the write common data line pair as an input, and the write end detection unit includesA MOS transistor switch having a performance equivalent to a write column selection switch for a memory array; a simulated line means having a delay characteristic equivalent to a data line in the memory array; and a write time characteristic equivalent to a memory cell in the memory array. Simulation memory means, and buffer means for outputting a write end signal,
Driving the simulated memory means and outputting a signal of one storage node of the simulated memory means from the buffer means as a write end signalThis is achieved by:
[0011]
[Action]
According to the present invention, when the write end detecting means provided in the semiconductor memory device detects the end of writing data to the memory array, the internal write operation can be ended without waiting for the end of the external write signal. Therefore, the power consumption due to the internal write pulse can be reduced, and the influence on the next read cycle following the write cycle can be eliminated, so that high-speed data writing and reading can be performed.
[0012]
Further, according to the present invention, since the write control unit can invalidate the write operation during the continuous data write processing by the skip signal, for example, the actual write operation can be performed only on either the odd address or the even address. It is possible to perform control of writing data and skipping writing of the other address. When an electronic device is configured using such a storage device, various new applications of the storage device can be achieved. .
[0013]
【Example】
Hereinafter, an embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to the drawings.
[0014]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a detailed configuration of a main part of the embodiment of the present invention, and FIG. 4 is a chart showing a configuration example of a memory cell, FIG. 5 is a block diagram showing a configuration example of a write end detection circuit, and FIG. 6 is a time chart for explaining the operation of the write end detection circuit shown in FIG. 1, 2, 4, and 5, 100 is a semiconductor memory device, 101 is a memory array, 110 is a row decoder, 120 is a column decoder, 130 is a column selection circuit, 140 is a sense amplifier, 150 is an output buffer, 160 is a write control circuit, 170 is a write amplifier, 180 is a write end detection circuit, and 400 is a memory cell.
[0015]
As shown in FIG. 1, the entire semiconductor memory device 100 according to one embodiment of the present invention is configured to include a plurality of functional circuits. Hereinafter, those functional circuits will be described.
[0016]
The memory array 101 is a static memory array in which a plurality of memory cells are arranged in a matrix. The row decoder 110 determines a row address of the memory array 101 by using an address AX as an input. The column address of the memory array 101 is determined using the address AY as an input. The column selection circuit 130 connects the memory cell selected according to the output of the column decoder 120 to the sense amplifier 140 or the write amplifier 170 for reading data, and the output buffer 150 outputs read data to the outside.
[0017]
The write control circuit 160 receives an external chip select signal CSN (hereinafter, referred to as a CSN signal) and a write command signal WEN (hereinafter, referred to as a WEN signal), and receives an internal write pulse signal WEP (hereinafter, referred to as a WEP signal), A write mode signal WMOD (hereinafter, referred to as a WMOD signal) and an internal chip select signal CSP (hereinafter, referred to as a CSP signal) are generated. The CSP signal is connected to the row decoder 110, the column decoder 120, the sense amplifier 140, and the output buffer 150. When the semiconductor memory device 100 is not selected, the operation of these circuits is stopped, and the power consumption of the semiconductor memory device is reduced. Has been reduced.
[0018]
The write amplifier 170 drives the write common data lines WCD1 and WCD2 based on the WEP signal and the write data signal DIN, and writes desired data to the memory array 101.
[0019]
The write end detection circuit 180 is a characteristic circuit provided according to the present invention, and detects a write end by using the WMOD signal from the write control circuit 160 and the signals to the write common data lines WCD1 and WCD2 as inputs. An end signal WEND is generated and fed back to the write control circuit 160. Upon receiving this signal, the write control circuit 160 terminates the WEP signal.
[0020]
Note that in one embodiment of the present invention, the write control circuit 160 receives a write skip signal SKIP from outside, and when this signal is asserted, the write operation can be skipped even in a write cycle.
[0021]
Next, a detailed configuration of a main part of an embodiment of the present invention will be described with reference to FIG.
[0022]
In FIG. 2, M₁₁~ M_m1And M_1n~ M_mnAre memory cells, each of which has a complementary data line d₁₁, D₁₂And d_n1, D_n2It is connected to the. Further, the memory cell M₁₁, M_1nIs the row selection line X₁  And M_m1, M_mnIs the row selection line X_m  It is connected to the. Complementary data line d₁₁, D₁₂And power supply V_cc, And PMOS load means 201 and 202 are connected to each other._n1, D_n2And power supply V_cc, PMOS load means 203 and 204 are connected. Further, the NMOS column selection switches 211 and 212 for writing have respective drains connected to the data line d.₁₁, D₁₂The source is connected to the write common data lines WCD1 and WCD2, and the gate is connected to the column select signal Y1. Similarly, the write NMOS column select switches 213 and 214 are connected to the respective drains. Is the data line d_n1, D_n2The source is connected to the write common data lines WCD1 and WCD2, and the gate is connected to the column selection signal Yn.
[0023]
In the above description, the memory cell M₁₁~ M_mnIs not particularly limited, for example, as shown as a memory cell 400 in FIG. 4, a memory element including two inverter circuits 401 and 402 and a data line d driven by a word signal WL as a row selection line.₁  , D₂  Are connected to the memory element.
[0024]
The write control circuit 160 includes an inverter 161, a NOR gate 162, a delay circuit 163, and an AND gate 164. The inverter 161 outputs an inverted signal CSP of the external chip select signal CSN, and the NOR gate 162 receives the CSN signal and the WEN signal as inputs, and generates an internal write mode signal WMOD when both are at a low level. This WMOD signal is input to the write end detection circuit 180 and also input to the delay circuit 163, and the delay output is connected to one input of the AND gate 164. The other inputs of the AND gate 164 are connected to a write end signal WEND from the write end detection circuit 180 and an external write skip signal SKIP as an optional input.
[0025]
A write end detection circuit 180, which will be described in detail later, detects the end of writing to the memory cell based on the WMOD signal output from the write control circuit 160 and the signals on the write common data lines WCD1 and WCD2, and performs the write operation. The end signal WEND signal is fed back to the write control circuit 160. When receiving the WEND signal, the write control circuit 160 lowers the internal write pulse WEP at that time even if the external signals CSN and WEN are kept asserted, and terminates the write operation.
[0026]
Next, a write operation in one embodiment of the present invention will be described with reference to a time chart shown in FIG. Note that the read operation is the same as that of the conventional technique, and the description thereof is omitted.
[0027]
In the write cycle shown in FIG._WAS  After a time, the external write command signal WEN is asserted. This WEN signal is held at a low level until the end of the write cycle. The write mode signal WMOD is a signal that goes high when both the chip select signal CSN and the WEN signal are low, and is kept low otherwise. The internal write pulse WEP rises td time after the fall of the WEN signal. This time td is used to ensure that writing to a regular address is performed._WAS  And the decoder delay time t_DEC  From the relationship
t_WAS+ Td ≧ t_DEC
Is determined to satisfy
[0028]
When WEP rises, one of the write common data lines WCD1 and WCD2 is driven to a low level in accordance with the write data DIN, and the other is kept at a high level. When one of WCD1 and WCD2 is driven to a low level, the write end detection circuit 180 operates in response to the drive._WMAfter a lapse of time, the write end signal WEND falls. Thereafter, the WEND signal is maintained at a low level until the WMOD signal falls at the end of the write cycle. In addition, WEP falls in response to the fall of the WEND signal. The internal write operation is performed only during the period when the WEP is at the high level, and only during that period, one of WCD1 and WCD2 is maintained at the low level. When WEP goes low, WCD1 and WCD2 are both driven high.
[0029]
The dotted line shown in FIG. 3 shows the operation in the case of the conventional technique. In the case of the conventional technique, the internal write pulse WEP falls after a time td from the fall of the WMOD signal. For this reason, in the prior art, the time for keeping WCD1 or WCD2 falling is also long before the fall of WEP, and it penetrates to the next cycle. If a read cycle is executed immediately after a write cycle, This has caused a significant increase in access time.
[0030]
In the case of the embodiment of the present invention, the write end signal WEND is output before the end time of the write cycle, and in response, the WEP signal falls and WCD1 or WCD2 rises. For this reason, the embodiment of the present invention can eliminate an increase in access time when a read cycle is executed immediately after a write cycle in the related art. Further, since the internal write pulse WEP falls without waiting for the end of the external write command signal WEN, subsequent power consumption in the write cycle can be eliminated, and the power consumption of the entire storage device can be reduced. Can be planned.
[0031]
Next, a specific configuration example of the write completion detection circuit 180 will be described with reference to FIG. In FIG. 5, reference numeral 500 denotes a simulated memory cell, and 530 denotes a simulated wiring.
[0032]
The write end detection circuit 180 includes a simulated memory cell 500 having a write time characteristic equivalent to the memory cell described with reference to FIG. 4, an NMOS switch 521, 522 having characteristics equivalent to the column selection switches 211 to 214 described with reference to FIG. Data line d in FIG.₁₁, D₁₂~ D_n1, D_n2And a NOR gate 510.
[0033]
The gates of the NMOSs 503 and 504 constituting the simulated memory cell 500 are connected to the power supply V._ccIt is connected to the. The WMOD signal is input to the drain of the NMOS 503, and the node P2 is connected to the drain of the NMOS 504. Also, the internal storage node Q_P  , Q_N  Q out of_P  Is connected to one input of a NOR gate 510, and the other input of the NOR gate 510 is connected to an optional write skip signal SKIP as required. If SKIP is not used, the SKIP input of NOR gate 510 is fixed at a low level, and NOR gate 510 operates as an inverter.
[0034]
The NMOS switches 521 and 522 have their drains connected to the write common data lines WCD1 and WCD2, the gate of the NMOS switch 521 connected to the drain of the NMOS switch 522, and the gate of the NMOS switch 522 connected to the gate of the NMOS switch 521. The respective sources are commonly connected to the node P1.
[0035]
A simulated wiring 530 composed of, for example, a resistor and a capacitor is connected between the nodes P1 and P2. This simulated wiring 530 is a data line d.₁₁, D₁₂~ D_n1, D_n2If the wiring delay can be ignored, it can be omitted.
[0036]
Next, the operation of the write end detection circuit 180 shown in FIG. 5 will be described with reference to the time chart shown in FIG.
[0037]
When the WMOD signal is at a low level, the common data lines WCD1 and WCD2 are both at a high level. Accordingly, at this time, both of the NMOSs 521 and 522 are turned on, the nodes P1 and P2 are at a high level, and the drain of the NMOS 504 of the pseudo memory cell 500 is at a high level. On the other hand, since the drain of the NMOS 503 is at a low level, the node Q_P  Is lowered to a low level, so that node Q_N  Is at a high level. Note that the SKIP signal is held at a low level, and in this state, the write end signal WEND is at a high level.
[0038]
From the state described above, a write cycle starts, and at time t₁  When the WMOD signal rises to a high level at a predetermined time t_d1Later, the internal write pulse WEP rises. When WEP rises, for example, WCD1 of the write common data line falls to a low level in response to write data, and WCD2 remains at a high level. When WCD1 falls, nodes P1 and P2 sequentially go low through NMOS 521. When the node P2 goes low, the node Q_N  Is lowered to a low level, and the node Q_P  Is raised to a higher level. Node Q_P  To a high level means that the writing of the data to the pseudo memory cell 500 has been completed, that is, the writing of the data to the actual memory cell has been completed. t₂  To set the write end signal WEND to low level and output the write end.
[0039]
This write end signal is fed back to the write control circuit 160, and the internal write pulse WEP falls. When the internal write pulse WEP falls, WCD1, P1, and P2 also sequentially rise and the write operation ends. Thereafter, the write cycle ends, and the time t₃  When the WMOD signal falls, the node Q_P  Is low level, node Q_N  Are sequentially set to the high level, and the node Q_P  , The write end signal WEND returns to a high level.
[0040]
The dotted line shown in FIG. 6 shows the operation in the case of the conventional technology. In the case of the conventional technology, the internal write pulse WEP is set to t after the fall of the WMOD signal._d1It had been shut down after hours. For this reason, in the related art, the time during which WCD1 or WCD2 is turned down is equal to the time t.₃  If the read cycle is executed immediately after the write cycle, the access time is remarkably increased.
[0041]
In one embodiment of the present invention, the write cycle end time t₃  Time t before₂  , A write end signal WEND is output, and in response, the WEP signal falls and WCD1 or WCD2 also rises. For this reason, the embodiment of the present invention can eliminate an increase in access time when a read cycle is executed immediately after a write cycle in the related art. Further, since the internal write pulse WEP falls without waiting for the end of the external write command signal WEN, subsequent power consumption in the write cycle can be eliminated, and the power consumption of the entire storage device can be reduced. Can be planned.
[0042]
FIG. 7 is a block diagram showing another configuration example of the write completion detection circuit. In FIG. 7, reference numeral 700 denotes a simulated memory cell, and 731 and 731 denote simulated wirings.
[0043]
The illustrated write end detection circuit 180 includes a simulated memory cell 700 composed of a flip-flop whose write time characteristic is equivalent to that of the memory cell described with reference to FIG. 4, and a characteristic equivalent to the column selection switches 211 to 214 described with reference to FIG. The NMOS switches 721 and 722 and the data line d in FIG.₁₁, D₁₂~ D_n1, D_n2And the NOR gate 710.
[0044]
The simulated memory cell 700 is constituted by a flip-flop and an output inverter 703 by NAND gates 701 and 702, and one input of the NAND gate 701 is supplied with a write command signal WMOD. The NMOS switches 721 and 722 have their drains connected to the write common data lines WCD1 and WCD2, and their gates connected to the power supply VCD._ccConnected in common. The simulation wiring 731 is connected between the source of the NMOS 721 and one input of the NAND gate 702, and the simulation wiring 732 is connected between the source of the NMOS 732 and another input of the NAND gate 702. These simulated wirings are composed of, for example, a resistor and a capacitor.
[0045]
The output of the inverter 703 in the simulated memory cell 700 is connected to one input of the NOR gate 710, and the other input of the NOR gate 710 is connected to the write skip signal SKIP as necessary. When SKIP is not used, the SKIP input of NOR gate 710 is fixed at a low level, and NOR gate 710 operates as an inverter. Note that the dummy wirings 731 and 732 can be omitted if the wiring delay of the data line can be ignored.
[0046]
FIG. 8 is a block diagram showing still another configuration example of the write completion detection circuit. In FIG. 8, 800 is a dummy memory cell, and 820 is an ENOR (Exclusive NOR) gate.
[0047]
The illustrated write end detection circuit 180 includes a simulated memory cell 800 configured by a flip-flop having a write time characteristic equivalent to the memory cell described with reference to FIG. 4, and an ENOR 820 that sets the flip-flop. The flip-flop includes NAND gates 801 and 802, and an output inverter 803 is provided in the simulated memory cell 800. A write command signal WMOD is input to one input of a NAND gate 801 that forms a flip-flop. This flip-flop changes its output to low when one of WCD1 and WCD2 goes low during a write operation. Set by ENOR gate 820 to level.
[0048]
During a write operation, when the flip-flop is set, as a result, the node Q_P  Is high level, node Q_N  Is at a low level, a high-level signal is output from the inverter 803, and the write end signal WEND is at a low level.
[0049]
In the example shown in FIG. 8, the data line d in FIG.₁₁, D₁₂~ D_n1, D_n2Although a simulated wiring equivalent to this wiring is omitted, a simulated wiring can be provided between the ENOR gate 820 and the NAND gate 802 as necessary. The output of the inverter 803 is connected to one input of a NOR gate 810, and the other input of the NOR gate 810 is connected to a write skip signal SKIP as necessary. If SKIP is not used, the SKIP input is fixed at a low level, and NOR gate 810 operates as an inverter.
[0050]
The write end detection circuit having the configuration shown in FIGS. 7 and 8 described above operates similarly to the write end detection circuit described with reference to FIG. 5, and by using such a circuit, An increase in access time during execution of a read cycle immediately after a write cycle can be eliminated, and power consumption can be reduced.
[0051]
FIG. 9 is a block diagram showing an application example of the present invention. In FIG. 9, 900 is a data processing device such as a microprocessor or a microcontroller, and 910 and 920 are storage devices having a write skip function according to the above-described embodiment of the present invention.
[0052]
The illustrated application example is a data processing system using a semiconductor memory device according to an embodiment of the present invention, in which a data processing device 900 and storage devices 910 and 920 include an address bus AB, a data bus DB, a control bus CB, The data processing device 900 reads data from or writes data to the storage devices 910 and 920 by being connected to each other via a line SKIP.
[0053]
The storage devices 910 and 920 have a write skip function, and the presence / absence of a write skip operation is controlled according to a signal input to the terminal S. For this reason, the data processing device 900 can assert the skip signal SKIP at an arbitrary time while issuing a write command through the control bus CB, thereby performing control to invalidate the writing to the storage device at that time. it can.
[0054]
Therefore, according to the application example of the present invention described above, for example, actual data is written to only one of the odd address and the even address while continuously performing writing from one address to another address. The writing of the other address can be skipped. In this application example of the present invention, by using the semiconductor memory device according to the present invention, various other new memory devices other than those described above can be applied.
[0055]
【The invention's effect】
As described above, according to the present invention, when the internal write operation is completed, the write can be completed without waiting for the end of the external write command signal, so that the adverse effect on the next read cycle can be eliminated. Further, the time spent for the writing operation can be shortened, so that the power consumption at the time of writing can be reduced.
[0056]
Further, as an optional system, a skip signal can be used, so that writing is performed continuously from one address to another while, for example, the actual address is written only to either the odd address or the even address. Data can be written and control can be performed to skip writing of the other address, and various new applications of the storage device can be implemented.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to one embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed configuration of a main part of one embodiment of the present invention.
FIG. 3 is a time chart illustrating a write operation.
FIG. 4 is a diagram illustrating a configuration example of a memory cell;
FIG. 5 is a block diagram illustrating a configuration example of a write end detection circuit;
FIG. 6 is a time chart for explaining the operation of the write end detection circuit shown in FIG. 5;
FIG. 7 is a block diagram illustrating another configuration example of the write completion detection circuit;
FIG. 8 is a block diagram showing still another configuration example of the write completion detection circuit.
FIG. 9 is a block diagram showing an application example of the present invention.
FIG. 10 is a time chart for controlling the operation of the writing circuit according to the related art.
[Explanation of symbols]
100 storage device
101 Memory Array
110 row decoder
120 column decoder
130 column selection circuit
140 sense amplifier
150 output buffer
160 Write control circuit
170 Write Amplifier
180 Write end detection circuit
400 memory cells
500, 700, 800 simulated memory cells
530,731,732 Simulated wiring
900 data processing device
910, 920 Storage device

Claims (3)

In a semiconductor memory device having data reading and writing functions,
A write end detecting means for inputting a signal of the write common data line pair is provided, the write end detecting means comprising: a MOS transistor switch having a performance equivalent to a write column selection switch for the memory array; Simulated line means having a delay characteristic equivalent to a line, simulated memory means having a write time characteristic equivalent to a memory cell in a memory array, and buffer means for outputting a write end signal,
A semiconductor memory device, wherein the simulation memory means is driven, and a signal of one storage node of the simulation memory means is output from the buffer means as a write end signal . In a semiconductor memory device having data reading and writing functions,
Comprising a write end detecting means which receives the common data line pair of the signal for writing, the write end detecting means, and M OS transistor switches that have a column select switch equivalent performance for writing to the memory array, the memory array includes a pattern quasilinear path means that having a data line equivalent delay characteristics of the inner, and flip-flop means having a memory cell equivalent writing time characteristics in the memory array, and a Baffua means for outputting a write end signal,
A semiconductor memory device which drives the flip-flop means and outputs a signal of one storage node of the flip-flop means as a write end signal from the buffer means. In a semiconductor memory device having data reading and writing functions,
Write end detection means for inputting a signal of the write common data line pair, wherein the write end detection means outputs a low level signal when one of the common data line signals is at a high level and the other is at a low level. An ENOR circuit, flip-flop means having write time characteristics equivalent to those of memory cells in the memory array, and buffer means for outputting a write end signal ;
A semiconductor memory device which drives the flip-flop means and outputs a signal of one storage node of the flip-flop means as a write end signal from the buffer means.

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