JPH08212777A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To obtain a semiconductor memory device in which data can be transferred surely from a serial register up to a memory cell array provided with a sense amplifier composed of a latch circuit constituted as an inverter. CONSTITUTION: A memory cell array 32 for a RAM part is provided with a plurality of word lines, with a plurality of bit line pairs and with a plurality of memory cells C, and it can read and write data regarding the arbitrary cells C. Sense amplifiers 38 are latch circuits, and they amplify the potential of the bit line pairs. A serial register 42 for a SAM part comprises a plurality of SAM cells 61 composed of latch circuits. An activation circuit 67 supplies a power supply to the register 42 so as to activate the SAM cells 61. A transfer gate transistor 43 transfers a plurality of pieces of data of one out of the cell array 32 and the register 42 to the other out of them. A cutoff control means is contained in a transfer control circuit 44, and it controls the activation circuit 67 so as to cut off the supply of the power supply to the register 42 when data in the register 42 is transferred to the cell array 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More specifically, the present invention relates to an image display memory (VRAM: video random access memory) having both a random access memory (DRAM) and a serial access memory (SAM).

The VRAM can mutually transfer data between the DRAM and the SAM. This data transfer includes read transfer for transferring the DRAM data to the SAM and write transfer for transferring the SAM data to the DRAM. The present invention relates to a technique for accurately performing write transfer.

[0003]

2. Description of the Related Art FIG. 10 shows a conventional VRAM. VRA
M1 is a memory cell array 2 and SA that constitute a DRAM
The serial register 3 forming M is provided.

The memory cell array 2 has a plurality of bit line pairs B.
L ₁ , BL ₁ bar to BL _n , BL _n bar (B in FIG. 10)
L ₁ and BL ₁ bar, and BL _n and BL _n bar only are shown), and a plurality of word lines WL _{1 to} WL _m (FIG. 10) are provided.
Then, only WL ₁ and WL ₂ are shown). A column gate (not shown) is connected to one end of each bit line pair, and a row decoder (not shown) is connected to one end of each of the word lines WL _{1 to} WL _m .

A memory cell C is connected between each bit line and each word line. Therefore, when any one pair of bit lines is selected and when any one word line is selected, one memory cell C is selected. Data is read from or written to the selected memory cell C. When the memory cell is not selected, the potential of each bit line pair is set to Vcc / 2 by the action of an equalizer (not shown).

Each bit line pair BL ₁ , BL ₁ bar to B
A sense amplifier 5 for amplifying the data of each bit line pair is connected to the ends of the L _n and BL _n bars. Each sense amplifier 5 has high-potential and low-potential power supply lines PSG, NS
An inverter composed of PMOS and NMOS transistors 6 and 7 connected in series between G and P connected in series between the high-potential and low-potential power supply lines PSG and NSG.
The latch circuit is composed of an inverter composed of MOS and NMOS transistors 8 and 9. PMOS and NMO
The gates of the S transistors 6 and 7 are connected to the output of the inverter formed by the transistors 8 and 9 and also to the bit lines BL ₁ bar to BL _n bar. PMOS
The gates of the NMOS transistors 8 and 9 are connected to the output of the inverter composed of the transistors 6 and 7 and also connected to the bit lines BL _{1 to} BL _n .

An activation circuit 10 for activating each sense amplifier 5 is connected to one end of the high potential power supply line PSG and the low potential power supply line NSG. The source of the PMOS transistor 11 is connected to the power supply Vcc, and the drain is connected to the high potential power supply line PSG. The source of the NMOS transistor 12 is connected to the ground GND, and the drain is connected to the low potential power supply line NSG. PMO
A signal PLE obtained by inverting the sense amplifier activation signal PLE via the inverter 13 is provided to the gate of the S transistor 11.
The bar has been entered. The sense amplifier activation signal PLE is input to the gate of the NMOS transistor 12. After one of the word lines is set to the H level and the memory cell is selected, the sense amplifier activation signal PLE is set to the H level for a predetermined period. When all word lines are at L level and no memory cell is selected, sense amplifier activation signal PLE is held at L level.

Therefore, when the memory cell is not selected,
When the sense amplifier activation signal PLE becomes L level, P
The MOS and NMOS transistors 11 and 12 are turned off. The high potential power supply line PSG is a PMOS transistor 11
Is cut off from the power supply Vcc, and the low potential power supply line NSG is cut off from the ground GND when the NMOS transistor 12 is turned off. At this time, the potentials of the high-potential and low-potential power supply lines PSG and NSG are set to Vcc / 2 by the action of an equalizer (not shown). Since the potential difference between the high-potential and low-potential power supply lines PSG and NSG disappears, each sense amplifier 5 is inactivated.

Further, when the sense amplifier activation signal PLE becomes H level during the selection of the memory cell, the PMO
The S and NMOS transistors 11 and 12 are turned on. The high potential power supply line PSG is supplied with the power supply Vcc based on the turning on of the PMOS transistor 11, and the low potential power supply line NSG is supplied.
Is connected to the ground GND when the NMOS transistor 12 is turned on. Since the difference between the potential of the high-potential power supply line PSG and the potential of the low-potential power supply line NSG becomes Vcc, each sense amplifier 5 is activated. Each sense amplifier 5 has a corresponding bit line pair BL ₁ , BL ₁ bar to BL _n ,
The BL _n bar data is amplified and the amplified data is retained.

The serial register 3 has a bit line pair BL ₁ ,
BL ₁ bar to n corresponding to BL _n and BL _n bar, respectively
Pair of serial bit lines SBL ₁ , SBL ₁ bar to SB
L _n , SBL _n bar (only SBL ₁ , SBL ₁ bar, SBL _n , SBL _n bar are shown in FIG. 10) and n SAs
M cell 14 and. Serial bit lines SBL _{1 to} S
BL _n is connected to the bit lines BL _{1 to} BL _n via n transfer gate transistors 4, respectively. A transfer control signal TR0 is input to the gate terminal of each transfer gate transistor 4 from a transfer control circuit (not shown). An NMOS is provided for each serial bit line SBL ₁ bar to SBL _n bar.
The transistor 19 is connected to the NMOS transistor 1
The gate of 9 is connected to the ground GND. Therefore, each NMOS transistor 19 is turned off, and each serial bit line SBL ₁ bar to SBL _n bar is connected to the bit line BL ₁
It is completely separated from the bar to the BL _n bar.

Therefore, when the transfer control signal TR0 becomes H level, each transfer gate transistor 4 is turned on, and the DRAM
It is possible to perform a read transfer for transferring the data of the (memory cell array 2) to the SAM (serial register 3) or a write transfer for transferring the data of the SAM (serial register 3) to the DRAM (memory cell array 2).

Each SAM cell 14 has an inverter composed of PMOS and NMOS transistors 15 and 16 connected in series between the high-potential and low-potential power supply lines PSA and NSA, and the high-potential and low-potential power line PSA. , NSA
It is a latch circuit composed of an inverter composed of PMOS and NMOS transistors 17 and 18 connected in series between them. PMOS and NMOS transistors 15 and 16
Of the serial bit line SBL is connected to the output of the inverter composed of the transistors 17 and 18.
It is connected to ₁ bar to SBL _n bar. The gates of the PMOS and NMOS transistors 17 and 18 are connected to the output of the inverter composed of the transistors 15 and 16 and also connected to the serial bit lines SBL _{1 to} SBL _n .

High-potential and low-potential power supply lines PSA, NS
An activation circuit 20 for activating each SAM cell 14 is connected to one end of A. The drain of the NMOS transistor 21 is connected to the power supply Vcc, and the source is connected to the high potential power supply line PSA. The source of the NMOS transistor 22 is connected to the ground GND, and the drain is connected to the low potential power supply line NSA. Both NMOS
The activation signal SLE is applied to the gates of the transistors 21 and 22.
0 is entered. The activation signal SLE0 is set to the L level only during a certain period in the VRAM read transfer, and is held at the H level during the other period including the write transfer.

Therefore, when the activation signal SLE0 becomes L level during read transfer, the NMOS transistor 2
1, 22 are turned off. High potential power line PSA is NMOS
When the transistor 21 is turned off, it is disconnected from the power supply Vcc, and the low potential power supply line NSA is connected to the NMOS transistor 2
Each SAM cell 14 becomes inactive because it is disconnected from the ground GND based on the turning off of 2.

When the activation signal SLE0 goes high, the NMOS transistors 21 and 22 are turned on. The high-potential power supply line PSA is supplied with almost the power supply Vcc when the NMOS transistor 21 is turned on, and the low-potential power supply line N is supplied.
SA is connected to the ground GND when the NMOS transistor 22 is turned on. Since the difference between the potential of the high-potential power supply line PSA and the potential of the low-potential power supply line NSA becomes approximately Vcc, each SAM cell 14 is activated. And each SA
The M cell 14 has a corresponding serial bit line pair SBL ₁ , S
The data of BL ₁ bar to SBL _n and SBL _n bar is amplified and the amplified data is held.

The write transfer operation in the VRAM 1 configured as described above will be described with reference to FIG. During the write transfer, the activation signal SLE0 is held at the H level, the NMOS transistors 21 and 22 are turned on, and the difference between the potential of the high potential power supply line PSA and the potential of the low potential power supply line NSA becomes approximately Vcc. . Therefore, each SAM cell 14 is activated, and each SAM cell 14 holds H level (= logical value 1) or L level (logical value 0) data.

First, any one of the word lines in the memory cell array 2, for example, the word line WL ₁ is selected based on the row address signal, and its potential is set to the H level.
As a result, one row (n bits) of memory cells C connected to the word line WL ₁ is selected.

Next, the transfer control signal TR0 is turned on the transfer gate transistor 4 to be the H level, the data serial bit lines SBL ₁ to SB of each SAM cell 14
L _n , transfer gate transistor 4 and bit lines BL ₁ to
It is transferred to each sense amplifier 5 via BL _n .

Thereafter, when the sense amplifier activation signal PLE is changed from the L level to the H level, the PMOS transistor 11 and the NMOS transistor 12 are turned on, and the potential of the high potential power supply line PSG and the low potential power supply line NSA. And the difference is Vcc. Therefore, each sense amplifier 5 is activated, each sense amplifier 5 amplifies the data of the bit line pair BL ₁ , BL ₁ bar to BL _n , BL _n bar, and the data is amplified to the memory cell C corresponding to the sense amplifier 5. Write the data.

[0020]

However, the farther the layout position of each transfer gate transistor 4 is from the signal source (not shown) of the transfer control signal TR0, the more
It takes a lot of time for the transfer control signal TR0 to propagate. Therefore, the transfer gate transistors 4 are turned on at different times, and the transfer gate transistors 4 close to the signal source.
Is turned on early based on the signal TR0, and the transfer gate transistor 4 far from the signal source is turned on late based on the signal TR0 '.

At this time, the sense amplifier activation signal PLE
Is at the L level, the PMOS transistor 11 and the NMOS transistor 12 are off, and the potentials of the high-potential and low-potential power supply lines PSG and NSG are held at Vcc / 2.

The SAM cell 14 corresponding to the transfer gate transistor 4 which is turned on earlier based on the transfer control signal TR0.
Data of H level. Then, since the SAM cell 14 is activated, the voltage of the drain (node on the NMOS transistor 7 side) of the PMOS transistor 6 of the sense amplifier 5 corresponding to this SAM cell 14 gradually rises. The drain voltage of the PMOS transistor 6 is the gate voltage (= the voltage of the bit line BL bar (= Vcc /
When it becomes larger than the value obtained by adding the threshold voltage VthP to 2)), the PMOS transistor 6 is turned on. When the PMOS transistor 6 is turned on, the H-level data of the SAM cell 14 causes the potential of the high potential power supply line PSG to reach Vcc.
It rises from / 2.

Further, the data of the SAM cell 14 corresponding to the transfer gate transistor 4 which is turned on earlier based on the transfer control signal TR0 is set to the L level. Then, since the SAM cell 14 is activated, the voltage of the drain (node on the PMOS transistor 6 side) of the NMOS transistor 7 of the sense amplifier 5 corresponding to the SAM cell 14 gradually decreases. The drain voltage of the NMOS transistor 7 is the gate voltage (= voltage of the bit line BL bar (= Vcc
/ 2)) becomes smaller than the value obtained by subtracting the threshold voltage VthN from the threshold voltage VthN, the NMOS transistor 7 is turned on. NMO
When the S-transistor 7 is turned on, the SAM cell 14 becomes L
The level data lowers the potential of the low potential power supply line NSG from Vcc / 2.

As described above, there are a plurality of transfer gate transistors that are turned on quickly based on the transfer control signal TR0, and the number of H level data and the number of L level data transferred via these transfer gate transistors are substantially equal. And Then, the potential of the high potential power supply line PSG is Vcc / 2.
, And the potential of the low potential power supply line NSG decreases from Vcc / 2. In this way, the potentials of the high-potential power supply line PSG and the low-potential power supply line NSG are opened from Vcc / 2, so that all the sense amplifiers 5 are input before the H-level sense amplifier activation signal PLE is input. Will be activated.

Therefore, the sense amplifier 5 corresponding to the transfer gate transistor 4 which is not yet turned on latches the data of the selected memory cell C. Therefore, these transfer gate transistors 4 are transferred to the transfer control signal TR.
If the data transferred from the SAM cell 14 has a reverse phase to the data in the memory cell C when it is turned on late based on 0 ', the transfer data cannot be written in the memory cell C, and the write transfer is surely performed. I can't do it.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reliably transferring data.

[0027]

To achieve the above object, the present invention comprises a plurality of memory cells connected to a plurality of word lines and a plurality of bit line pairs, and reads and writes data from and to any memory cell. A writable memory cell array, a first memory including a latch circuit including an inverter, and a plurality of sense amplifiers for amplifying potentials of a plurality of bit line pairs, and a latch circuit including a serial circuit A second memory including a serial register having a plurality of cells to be accessed, and an activation circuit for activating the plurality of cells by supplying power to the serial register; a first memory; A transfer gate provided between the memory and one of the memories for transferring a plurality of data to the other memory. A transfer control means for controlling the activation circuit so that the supply of power to the serial register is stopped when the plurality of data in the second memory are transferred to the first memory by making the transfer gate conductive. And.

[0028]

Therefore, according to the present invention, when the plurality of data in the second memory are transferred to the first memory, the power supply to the serial register is cut off, so that the cells of the serial register are deactivated. Becomes Therefore, the potential of the bit line is only slightly changed by the data transferred through the conductive transfer gate, and the malfunction of the sense amplifier is prevented.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an image display memory (VRA).
An embodiment embodied in M) will be described with reference to FIGS.

FIG. 3 shows the configuration of the VRAM 30 of this embodiment. The VRAM 30 includes a RAM unit 31 as a first memory that can be randomly accessed, and a SAM unit 41 as a second memory that can be serially accessed. R
The AM section 31 includes a memory cell array 32, an input circuit 33,
Column address buffer 34, row address buffer 3
5, a row decoder 36, a column decoder 37, a sense amplifier 38, and a RAM input / output circuit 39. The SAM unit 41 includes a serial register 42, a transfer gate 43, a transfer control circuit 44, a serial address counter 45, a serial decoder 46, and a SAM input / output circuit 47.
It consists of.

As shown in FIG. 1, the memory cell array 2 includes a plurality of bit line pairs BL ₁ , BL ₁ bar to BL _2n , BL _2n bar (BL ₁ , BL ₁ bar, BL _n , in FIG. 1). BL _n , bar BL _{n + 1} , BL _{n + 1} bar, B
L _2n and BL _2n bars only are shown), and a plurality of word lines WL _{1 to} WL _m (W in FIG. 1) extending in the row direction are provided.
Only L ₁ and WL ₂ are shown). Bit line pair BL ₁ ,
A column decoder 37 (see FIG. 3) is connected to one end of each of BL ₁ bar to BL _2n and BL _2n bar via a column gate (not shown), and one end of each of the word lines WL _{1 to} WL _m. A row decoder 36 (see FIG. 3) is connected to the section. A memory cell C is connected between each bit line and each word line. As shown in FIG. 2, the memory cell C is NM.
It has an OS transistor and a capacitor.

Therefore, when any one bit line pair is selected and any one word line is selected, one memory cell C connected to the selected bit line pair and word line is selected. Is selected. Data is read from or written to the selected memory cell C.

As shown in FIG. 2, the bit line pair BL ₁ , B
An equalizer 55 including three NMOS transistors is connected to L ₁ bar to BL _2n and BL _2n bar. The equalizing signal BRS is input to the gate of the NMOS transistor that constitutes the equalizer 55. Therefore,
When the H level equalizing signal BRS is input when the memory cell is not selected, the bit line pair BL ₁ and BL ₁
The potentials of the bars ˜BL _2n and BL _2n are set to Vcc / 2 by the action of the equalizer 55.

As shown in FIGS. 1 and 2, each bit line pair BL
_1, BL ₁ bar to BL _2n, BL _2n bar of each bit line pair BL ₁ at the ends, BL ₁ bar to BL _2n, the sense amplifier 38 for amplifying data of BL _2n bar is connected. Each sense amplifier 38 includes an inverter composed of a PMOS transistor 51 and an NMOS transistor 52 connected in series between a high potential power supply line PSG and a low potential power supply line NSG, and a high potential power supply line PSG and a low potential power supply line. The latch circuit includes an inverter including a PMOS transistor 53 and an NMOS transistor 54 connected in series between NSGs. The gates of the PMOS transistor 51 and the NMOS transistor 52 are PMOS
The bit line B is connected to the output of the inverter composed of the transistor 53 and the NMOS transistor 54.
It is connected to L ₁ bar to BL _2n bar. The gates of the PMOS transistor 53 and the NMOS transistor 54 are the PMOS transistor 51 and the NMOS transistor 5, respectively.
It is connected to the output of the inverter composed of 2 and is also connected to the bit lines BL _{1 to} BL _2n .

An activation circuit 57 for activating each sense amplifier 38 is connected to one end of each of the high potential power supply line PSG and the low potential power supply line NSG. Activation circuit 57
Is a PMOS transistor 58 and an NMOS transistor 5
9 and an inverter 60. The source of the PMOS transistor 58 is connected to the power source Vcc, and the drain is connected to the high potential power source line PSG. The source of the NMOS transistor 59 is connected to the ground GND, and the drain is connected to the low potential power supply line NSG. To the gate of the PMOS transistor 58, the signal PLE which is the inverted sense amplifier activation signal PLE is input via the inverter 60. The sense amplifier activation signal PLE is input to the gate of the NMOS transistor 59.
After one of the word lines is set to the H level and the memory cell is selected, the sense amplifier activation signal PLE is set to the H level for a predetermined period. When all word lines are at L level and no memory cell is selected, sense amplifier activation signal PLE is held at L level.

An equalizer 56 having three NMOS transistors is connected between the high potential power supply line PSG and the low potential power supply line NSG. The equalizing signal B is applied to the gate of the NMOS transistor forming the equalizer 56.
RS is input.

Therefore, when the memory cell is not selected,
When the sense amplifier activation signal PLE becomes L level, P
MOS transistor 58 and NMOS transistor 59
Turns off. The high potential power supply line PSG is disconnected from the power supply Vcc when the PMOS transistor 58 is turned off, and the low potential power supply line NSG is disconnected from the ground GND when the NMOS transistor 59 is turned off. At this time, the potentials of the high-potential and low-potential power supply lines PSG and NSG are set to Vcc / 2 by the action of the equalizer 56. Since the potential difference between the high-potential and low-potential power supply lines PSG and NSG disappears, each sense amplifier 38 becomes inactive.

Further, when the sense amplifier activation signal PLE becomes H level during the selection of the memory cell, the PMO
The S transistor 58 and the NMOS transistor 59 are turned on. The high potential power supply line PSG is supplied with the power supply Vcc when the PMOS transistor 58 is turned on, and the low potential power supply line NSG is connected to the ground GND when the NMOS transistor 59 is turned on. Power line PSG for high potential
Since the difference between the potential of the above and the potential of the low potential power supply line NSG becomes Vcc, each sense amplifier 38 is activated. Then, each sense amplifier 38 has a corresponding bit line pair BL ₁ , BL ₁
The data of the bar to BL _2n and BL _2n bar is amplified and the amplified data is held.

As shown in FIG. 3, address signals A _{0 to} A ₈ from the outside are input to the column address buffer 34 and the row address buffer 35. The row address buffer 35 converts the input address signals A _{0 to} A ₈ into row address strobe signals (hereinafter simply referred to as row signals) R.
It is latched based on the AS bar and is output to the row decoder 36 as row address signals RA _{0 to} RA ₈ .

The row decoder 36 receives the input row address.
Signal RA₀~ RA₈One word line WL based on
select. Then, it is connected to the selected word line WL.
The data stored in the memory cell is
L₁, BL₁Bar to BL_2n, BL _2nRead out to the bar
It

The column address buffer 34 latches the input address signals A _{0 to} A _{8 based} on a column address strobe signal (hereinafter, simply referred to as a column signal) CAS bar, and at the same time, the column address signals CA _{0 to} C _0.
It is output to the column decoder 37 as A ₈ .

The column decoder 37 selects the bit line BL and the inverted bit line BL bar on the basis of the inputted column address signals CA _{0 to} CA ₈ . Then, the selected word line WL and bit line pair pair BL ₁ , BL ₁ bar ~
The memory cell at the intersection with BL _2n and BL _2n bar is determined. The determined memory cell receives RA from an external device.
Input data D _{1 to} D ₈ are written via the M input / output circuit 39. The data stored in the determined memory cell is amplified by the sense amplifier 38 and output as output data D _{1 to} D ₈ to the external device via the common bus CB and the input / output circuit 39.

As shown in FIGS. 1 and 2, the serial register
3 is the bit line pair BL₁, BL₁Bar to BL_2n, BL
_2n2n pairs of serial bit line pairs corresponding to each bar
SB ₁, SB₁Bar to SB_2n, SB_2nBar (S in Figure 1
B₁, SB₁Bar, SB_n, SB_nBar, SB_{n + 1}, S
B_{n + 1}Bar, SB_2n, SB_2nOnly the bar is shown) and 2n
SAM cell 61 of. Serial bit line pair SB
₁, SB₁Bar to SB _n, SB_nEach SA corresponding to the bar
The block 42a is formed by the M cell 61, and
Rubit line pair SB_{n + 1}, SB_{n + 1}Bar to SB_2n, SB_2n
Block 42 by each SAM cell 61 corresponding to the bar
b is configured.

The serial bit lines SB _{1 to} SB _n are NMO
The serial bit lines SB _{n + 1 to} SB _2n are connected to the bit lines BL _{1 to} BL _n via n transfer gate transistors 43a composed of S transistors, and the serial bit lines SB _{n + 1 to} SB _2n are composed of n transfer gate transistors 43 composed of NMOS transistors.
The bit lines BL _{n + 1 to} BL _2n are connected via b. The transfer control signal TR1 is input from the transfer control circuit 44 to the gate terminal of each transfer gate transistor 43a, and the transfer control signal TR2 is input from the transfer control circuit 44 to the gate terminal of each transfer gate transistor 43b. Incidentally, the level of the transfer control signals TR1, TR2 is determined based on the most significant bits CA ₈ column address signal.

An NMOS transistor 66 is connected to each serial bit line SB ₁ bar to SB _2n bar,
The gate of the transistor 66 is connected to the ground GND. Therefore, each NMOS transistor 66 is turned off, and each serial bit line SB ₁ bar to SB _2n bar is completely separated from the bit line BL ₁ bar to BL _2n bar.

When the transfer control signal TR1 goes high, the transfer gate transistors 43a are turned on and the block 42a is selected. When the transfer control signal TR2 goes high, the transfer gate transistors 43b are turned on and the block 42b is turned on. To be selected. Selected block and DR
A read transfer for transferring the data of the memory cell array 32 to the selected block or a write transfer for transferring the data of the selected block to the memory cell array 32 can be performed with the AM (memory cell array 32).

Each SAM cell 61 has a high potential power supply line PSA.
1 and P connected in series between the low potential power supply line NSA1
MOS transistor 62 and NMOS transistor 63
And a high-potential power supply line PSA1
And PM connected in series between the low potential power supply line NSA1
The latch circuit includes an inverter including an OS transistor 64 and an NMOS transistor 65. PMO
The gates of the S transistor 62 and the NMOS transistor 63 are connected to the output of the inverter composed of the PMOS transistor 64 and the NMOS transistor 65, and also connected to the serial bit lines SB ₁ bar to SB _2n bar. The gates of the PMOS transistor 64 and the NMOS transistor 65 are connected to the output of the inverter composed of the PMOS transistor 62 and the NMOS transistor 63, and the serial bit lines SB _{1 to} SB _2n are connected.
It is connected to the.

An activation circuit 67 for activating each SAM cell 61 is connected to one end of the high potential power supply line PSA1 and the low potential power supply line NSA1. Activation circuit 6
7 includes two NMOS transistors 68 and 69.
The drain of the NMOS transistor 68 is connected to the power supply Vcc, and the source is connected to the high potential power supply line PSA1. The source of the NMOS transistor 69 is the ground GN
It is connected to D, and the drain is connected to the low potential power supply line NSA1. The activation signal SLE1 is input from the transfer control circuit 44 to the gates of both NMOS transistors 68 and 69.

Therefore, when the activation signal SLE1 becomes L level, the NMOS transistors 68 and 69 are turned off.
The high-potential power supply line PSA1 is disconnected from the power supply Vcc when the NMOS transistor 68 is off, and the low-potential power supply line NSA1 is disconnected from the ground GND when the NMOS transistor 69 is off, so that each SAM cell 61 is inactive. Becomes

When the activation signal SLE1 goes high, the NMOS transistors 68 and 69 are turned on. The high-potential power supply line PSA1 is supplied with almost the power supply Vcc when the NMOS transistor 68 is turned on, and the low-potential power supply line NSA1 is connected to the ground GND when the NMOS transistor 69 is turned on. High potential power supply line PSA1
Of the potential of the low potential power supply line NSA1 is almost V
Since it becomes cc, each SAM cell 61 is activated. Each SAM cell 61 has a corresponding serial bit line pair S
The data of B ₁ and SB ₁ bar to SB _2n and SB _2n bar are amplified and the amplified data is held.

As shown in FIG. 3, the serial address counter 45 is connected to the column address buffer 34,
Column address signals CA _{0 to} CA ₈ are input. Also,
The counter 45 inputs the system clock signal SC. Then, the counter 45 sets an address (initial address) for reading data from the serial register 42 based on the input column address signals CA _{0 to} CA ₈ , and serial address signals SA _{0 to} SA ₈ indicating the initial address.
To the serial decoder 46. Also, the counter 4
Reference numeral 5 counts the input system clock signal SC and outputs the serial address signals SA _{0 to} SA _{8 obtained} by adding the count to the initial address. That is, the counter 45
Outputs serial address signals SA _{0 to} SA ₈ that are incremented by 1 each time the system clock signal SC is input.

The serial decoder 46 selects the serial bit line pair SB, SB bar based on the input serial address signals SA _{0 to} SA ₈ . The data stored in the register connected to the selected serial bit line pair SB, SB bar is output as serial output data SD _{1 to} SD ₈ via the SAM input / output circuit 47.

The input circuit 33 inputs various signals (eg, row address strobe signal RAS bar) from the outside and also inputs the most significant bit CA ₈ of the column address signal from the column address buffer 34. The input circuit 33 receives the sense amplifier activation signal PL based on various signals.
E, write transfer control signal WTRZ, upper transfer signal TU,
The lower transfer signal TL, the control signal LENX, the equalize signal BRS, the control signal BRS bar, etc. are generated and output.

The write transfer control signal WTRZ is VRAM3.
This is a control signal for setting 0 to the write transfer mode. The upper transfer signal TU and the lower transfer signal TL are generated based on the level of the column address signal CA ₈ and the data indicating whether or not the split transfer is performed in the write transfer. Split transfer is the block 4 of the serial register 42.
2a and 42b data is divided and transferred.
Column address signal C when split transfer is not performed
Both the upper transfer signal TU and the lower transfer signal TL are at the H level regardless of the level of A ₈ . When performing split transfer, the column address signal CA ₈ is at H level only escalated signal TU becomes H level, only the lower transfer signal TL when the column address signal CA ₈ is at L level to H level. The sense amplifier activation signal PLE is a signal which becomes H level for a predetermined period after the memory cell is selected, and the control signal LENX is a signal having a phase opposite to the sense amplifier activation signal PLE. The equalize signal BRS is a signal which becomes H level when the memory cell is not selected. The control signal BRS bar is a signal having a phase opposite to that of the equalize signal BRS, and is a signal that becomes H level when a memory cell is selected.

Next, details of the transfer control circuit 44 are shown in FIG.
Follow the instructions below. FIG. 4 shows a circuit section for controlling write transfer in the transfer control circuit 44. The transfer control circuit 44 includes a 3-input NAND 71, three 2-input NAND circuits 72 to 74, and inverters 75 to 80.

The NAND circuit 71 receives the control signal LENX, the write transfer control signal WTRZ and the control signal BRS bar. The NAND circuit 72 inputs the upper transfer signal TU and the output signal of the NAND circuit 71 through the inverter 75. The output of the NAND circuit 71 is output as the transfer control signal TR1 via the inverter 76. The NAND circuit 73 inputs the lower transfer signal TL and the output signal of the inverter 75. The output of the NAND circuit 73 is output as the transfer control signal TR2 via the inverter 77. The NAND circuit 74 inputs the output signal of the inverter 75 and
The output signal of the inverter 75 is converted into three inverters 78 to 8
Activation signal SL based on both input signals
Outputs E1. The NAND circuit 74 outputs the L-level activation signal SLE1 in synchronization with the switching of the output signal of the inverter 75 from the L level to the H level, and holds the L level for the propagation delay time of the inverters 78-80. That is, an L level one-shot pulse is output. In the present embodiment, the NAND circuits 71 and 74 and the inverters 75 and 78 to 80 constitute a cutoff control means, and by setting the activation signal SLE1 to the L level, the power supply to the serial register 42 is cut off. The activation circuit 67 is controlled.

Therefore, at least one of the control signal LENX, the write transfer control signal WTRZ, and the control signal BRS bar.
When the two signals are L level, the output signal of the NAND circuit 71 becomes H level and the output signal of the inverter 75 becomes L level.
Level. Therefore, the activation signal SLE1 becomes H level and the transfer control signals TR1 and TR2 become L level.

Further, the output signal of the NAND circuit 71 switches from the H level to the L level only when the control signal LENX, the write transfer control signal WTRZ and the control signal BRS bar all become the H level, and the output of the inverter 75. The signal switches from L level to H level. An L level one-shot pulse is output to activation signal SLE1 based on the switching of the output signal of inverter 75 to H level. At this time, if the upper transfer signal TU is at H level, the output signal of the NAND circuit 72 becomes L level, and the transfer control signal T at H level is passed through the inverter 76.
R1 is output. When the lower transfer signal TL is at H level, the output signal of the NAND circuit 73 becomes L level, and the transfer control signal T at H level is output via the inverter 77.
R2 is output.

Next, the VRAM 3 configured as described above
The write transfer operation of 0 will be described with reference to FIG. Write enable signal W when row signal RAS falls
When the E-bar is at the L level, the input circuit 33 outputs the write transfer control signal WTRZ at the H level, and the write transfer mode is set.

The VRAM 30 is not in the write transfer mode,
That is, when the write transfer control signal WTRZ is at L level, the activation signal SLE1 is held at H level, the NMOS transistors 68 and 69 are turned on, and the potential of the high potential power source line PSA1 and the low potential power source line NSA1 are turned on. The difference from the potential of Vcc becomes approximately Vcc. Therefore, each SAM cell 6
1 is activated, and each SAM cell 61 holds H level (= logical value 1) or L level (logical value 0) data.

Address signals A _{0 to} A ₈ are input to row address buffer 35 based on the fall of row signal RAS bar, and row address buffers 35 output row address signals RA _{0 to} RA ₈ to row decoder 36. To be done. The row address signals RA _{0 to} RA ₈ are decoded into selection signals by the row decoder 36, and _{one of} the word lines WL _{1 to} WL _m , for example, WL ₁ is set to H level based on the selection signal. As a result, one row (2n bits) of memory cells C connected to the word line WL ₁ are selected.

When the memory cell C for one row is selected,
Since the control signal LENX is at H level and the control signal BRS bar is at H level, the output signal of the NAND circuit 71 switches from H level to L level. Therefore, the activation signal SLE1 switches from H level to L level,
It is held at the L level for the propagation delay time by the inverters 78-80. While the activation signal SLE1 is at the L level, the NMOS transistors 68 and 69 are turned off, the high potential power supply line PSA1 is disconnected from the power supply Vcc, and the low potential power supply line NSA1 is disconnected from the ground GND. The cell 61 becomes inactive. At this time, when the upper transfer signal TU and the lower transfer signal TL are at H level, the transfer control signals TR1 and TR2 are at H level.

The transfer gate transistor 43a is turned on based on the H level transfer control signal TR1. Data serial bit lines SB ₁ ~ of the SAM cell 61 of block 42a based on the ON transfer gate transistors 43a
SB _n , transfer gate transistor 43a and bit line B
It is transferred to each sense amplifier 38 via L _{1 to} BL _n . The transfer gate transistor 43b is turned on based on the H level transfer control signal TR2. Each SAM of the block 42b based on the turning on of the transfer gate transistor 43b.
The data in the cell 61 is the serial bit lines SB _{n + 1 to} S _n.
B _2n , transfer gate transistor 43a and bit line BL
It is transferred to each sense amplifier 38 via _{n + 1 to} BL _2n .

By the way, each transfer gate transistor 43
The position in which a and 43b are laid out is the transfer control circuit 4
The farther from 4, the transfer control signals TR1, TR2
Takes a lot of time to propagate. Therefore, the transfer gate transistors 43a and 43b are turned on at different times, the transfer gate transistors 43a and 43b close to the transfer control circuit 44 turn on early, and the transfer gate transistors 43a and 43b far from the signal source turn on late.

At this time, the sense amplifier activation signal PLE
Is at the L level, the PMOS transistor 58 and the NMOS transistor 59 are off, and the potentials of the high-potential and low-potential power supply lines PSG and NSG are held at Vcc / 2.

The data of the SAM cell 61 corresponding to the transfer gate transistors 43a and 43b that are turned on earlier based on the transfer control signals TR1 and TR2 is set to the H level. At this time, since the SAM cell 61 is inactive, this SAM cell 61 is
The voltage of the drain (node on the NMOS transistor 52 side) of the PMOS transistor 51 of the sense amplifier 38 corresponding to the cell 61 slightly rises due to the data held in the SAM cell 61. The increase in the drain voltage of the PMOS transistor 51 is smaller than the threshold voltage VthP thereof, and the PMOS transistor 51 is held in the off state. Therefore, the potential of the high potential power supply line PSG is held at Vcc / 2. Further, the transfer gate transistors 43a and 43a turned on earlier based on the transfer control signals TR1 and TR2.
The data of the SAM cell 61 corresponding to b is set to the L level. At this time, since the SAM cell 61 is inactive, the NMO of the sense amplifier 38 corresponding to this SAM cell 61 is
The voltage of the drain of the S transistor 52 (the drain on the side of the PMOS transistor 51) is slightly lowered by the data held in the SAM cell 61. The decrease of the drain voltage of the NMOS transistor 52 is caused by the threshold voltage Vth thereof.
It is smaller than N, and the NMOS transistor 52 is held in the off state. Therefore, the potential of the low potential power supply line NSG is held at Vcc / 2. Therefore, all the sense amplifiers 38 are held inactive, and the transferred data is not latched at this point.

Thereafter, when the sense amplifier activation signal PLE switches from the L level to the H level, the PMOS transistor 58 and the NMOS transistor 59 are turned on, and the potential of the high potential power supply line PSG and the low potential power supply line NSA are changed. The difference from the potential is Vcc. Therefore, each sense amplifier 38
Is activated, and each sense amplifier 38 is connected to the bit line pair BL ₁ ,
The data of BL ₁ bar to BL _2n and BL _2n bar is amplified, the amplified data is written to the memory cell C corresponding to the sense amplifier 38, and the write transfer is completed.

As described above, in this embodiment, the transfer control circuit 44 includes the NAND circuits 71, 74 and the inverter 75,
A cutoff control means consisting of 78-80 was provided. During write transfer, when transferring data from the serial register 42 to the memory cell array 32, an L level one-shot pulse is generated in the activation signal SLE1 to turn off the activation circuit 67 and deactivate the SAM cell 61. I decided to do it. As a result, before the sense amplifier 38 is activated based on the sense amplifier activation signal PLE, the sense amplifier 38 can be prevented from malfunctioning due to the data in the SAM cell 61, and the write transfer can be reliably performed. 6 shows another transfer control circuit 81 applicable to the serial register 42 in FIG. The transfer control circuit 81 differs from the transfer control circuit 44 in that the NAND circuit 74 and the inverters 79 and 80 in the transfer control circuit 44 are omitted and the output signal of the inverter 78 is the activation signal SLE1. In the present embodiment, the NAND circuit 71 and the inverters 75 and 78 constitute a cutoff control means.

The transfer control circuit 81 can output the L level activation signal SLE1 while the write transfer control signal WTRZ, the control signal LENX and the control signal BRS bar are all at the H level. The other operations and effects of the transfer control circuit 81 are almost the same as the operations and effects of the transfer control circuit 44.

FIG. 7 shows another serial register 86 applicable to the VRAM 30 in FIG. The serial register 86 is different from the serial register 42 in that different power supply lines are provided for the blocks 42a and 42b in the serial register 42 and two activation circuits 67 and 95 are provided.

That is, the power supply line PSA1 for high potential and the power supply line NSA1 for low potential are provided for the block 42a, and the activation circuit 67 is connected to both power supply lines PSA1, NSA1. The activation signal SLE1 is input from the transfer control circuit 82 to the gates of both NMOS transistors 68 and 69 of the activation circuit 67.

Further, a high potential power supply line PSA2 and a low potential power supply line NSA2 are provided for the block 42b,
An activation circuit 95 is connected to both power supply lines PSA2 and NSA2. The activation circuit 95 includes two NMOS transistors 96 and 97. The drain of the NMOS transistor 96 is connected to the power supply Vcc, and the source is connected to the high potential power supply line PSA2. NMOS transistor 97
The source is connected to the ground GND, and the drain is connected to the low potential power supply line NSA2. The activation signal SLE2 is input from the transfer control circuit 82 to the gates of both the NMOS transistors 96 and 97.

FIG. 8 shows a circuit section for controlling the write transfer in the transfer control circuit 82. The transfer control circuit 82 is a 2-input NAND circuit 74 in the transfer control circuit 44.
And the inverters 78 to 80 are omitted, and two 2-input NO
The transfer control circuit 44 differs from the transfer control circuit 44 in that R circuits 85 and 86 and eight inverters 87 to 94 are provided.

The NOR circuit 85 inputs the output signal of the NAND circuit 72 and the output signal of the NAND circuit 72 through the three inverters 87 to 89.
The NOR circuit 85 synchronizes with the switching of the output signal of the NAND circuit 72 from the H level to the L level and the inverter 8
It outputs a one-shot pulse that becomes H level for the propagation delay time of 7 to 89, and outputs an L level signal at other times. The output signal of NOR circuit 85 is inverted by inverter 90 and output as activation signal SLE1. Therefore, based on the switching of the output signal of the NAND circuit 72 from the H level to the L level, that is, the switching of the transfer control signal TR1 from the L level to the H level, the activation signal SLE1 has an L level one-shot pulse. Is output.

The NOR circuit 86 inputs the output signal of the NAND circuit 73 and the output signal of the NAND circuit 73 through the three inverters 91 to 93.
The NOR circuit 86 synchronizes with the switching of the output signal of the NAND circuit 73 from the H level to the L level, and the inverter 9
It outputs a one-shot pulse that becomes H level for the propagation delay time of 1 to 93, and otherwise outputs an L level signal. The output signal of NOR circuit 86 is inverted by inverter 94 and output as activation signal SLE2. Therefore, based on the switching of the output signal of the NAND circuit 73 from the H level to the L level, that is, the switching of the transfer control signal TR2 from the L level to the H level, the activation signal SLE2 has an L level one-shot pulse. Is output. In this embodiment, the NAND circuits 71 to 7
3, NOR circuits 85 and 86 and inverters 75 and 87 to
The shutoff control means is constituted by 94, and the activation signal SLE
Block 4 by setting SLE2 and SLE2 to L level
The activation circuits 67 and 95 are controlled so that the power supply to 2a and 42b is cut off.

In the serial register 82 of this embodiment, when split transfer is performed in the write transfer mode, for example, when the upper transfer signal TU goes to H level, the lower transfer signal TL goes to L level. An H level transfer control signal TR based on the H level upper transfer signal TU
1 is output, and an L level one-shot pulse is output as the activation signal SLE1. Based on the activation signal SLE1 of L level, each S in the block 42a
The AM cell 61 is deactivated, and the transfer gate transistor 43 is activated based on the H level transfer control signal TR1.
a is turned on, and the data in the block 42a is transferred to the memory cell array 32. On the other hand, the lower transfer signal T of L level
Based on L, the L level transfer control signal TR2 is output and the activation signal SLE2 is held at the H level. Since the transfer control signal TR2 is at L level, the transfer gate transistor 43b is turned off, and each SAM cell 61 of the block 42b is turned on based on the H level activation signal SLE2.
Is activated. Therefore, each SAM cell 61 of the block 42b that does not transfer data can be serially accessed.

Further, in the case of split transfer, when the upper transfer signal TU becomes L level, the lower transfer signal TL
Becomes H level. An H level transfer control signal TR2 is output based on the H level lower transfer signal TL, and an L level one-shot pulse is output as the activation signal SLE2. Each SAM cell 61 in the block 42b is deactivated based on the L level activation signal SLE2, the transfer gate transistor 43b is turned on based on the H level transfer control signal TR2, and the data in the block 42b is stored in the memory cell array 32. Transferred to.
On the other hand, the L level transfer control signal TR1 is output based on the L level upper transfer signal TU, and the activation signal SLE1 is held at the H level. Transfer control signal TR
Since 1 is at L level, the transfer gate transistor 43a
Is turned off, and each SAM cell 61 of the block 42a is activated based on the activation signal SLE1 of H level. Therefore, each SAM of the block 42a that does not perform data transfer
The cell 61 can be serially accessed.

FIG. 9 shows the serial register 86 in FIG.
Shows another transfer control circuit 98 applicable to the. The transfer control circuit 98 omits the NOR circuits 85 and 86 and the inverters 87 to 94 in the transfer control circuit 82, and NAN
The output signals of the D circuits 72 and 73 are activated signals SLE1 and S
It is different from the transfer control circuit 82 in that it is LE2. In the present embodiment, the NAND circuits 71 to 73 and the inverter 75 constitute the cutoff control means, and the activation signal SL is used.
By setting E1 and SLE2 to the L level, the activation circuits 67 and 95 are controlled so that the power supply to the blocks 42a and 42b is cut off.

In the transfer control circuit 98, the upper transfer signal TU is at H level while the write transfer control signal WTRZ, the control signal LENX and the control signal BRS bar are at H level.
When it is at the level, the L-level activation signal SLE1 can be output, and when the lower transfer signal TL is at the H-level, the L-level activation signal SLE2 can be output. Other functions and effects of the transfer control circuit 98 are almost the same as those of the transfer control circuit 82.

In each of the above embodiments, the SAM cell 61 of the serial registers 42 and 86 is a latch circuit composed of an inverter, but it may be a latch circuit composed of a flip-flop, for example.

[0081]

As described in detail above, according to the present invention,
Data can be reliably transferred from the second memory having a plurality of cells including the latch circuit to the first memory including the sense amplifier including the latch circuit having the inverter configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory cell array and a serial register according to an embodiment.

FIG. 2 is a circuit diagram of the memory cell array and serial register of FIG.

FIG. 3 is a block diagram showing a general VRAM.

FIG. 4 is a circuit diagram showing the transfer control circuit of FIG.

5 is a waveform diagram showing a write transfer operation of the VRAM shown in FIG.

FIG. 6 is a circuit diagram showing another transfer control circuit.

FIG. 7 is a block diagram of another memory cell array and serial register.

FIG. 8 is a circuit diagram showing another transfer control circuit.

FIG. 9 is a circuit diagram showing another transfer control circuit.

FIG. 10 is a circuit diagram showing a conventional VRAM.

FIG. 11 is a waveform diagram showing a write transfer operation of the VRAM shown in FIG.

[Explanation of symbols]

31 RAM section as first memory 32 Memory cell array 38 Sense amplifier 41 SAM section as second memory 42,86 Serial register 42a, 42b Block 43 Transfer gate 61 SAM cell 67,95 Activation circuit 71-74 Blocking control NAND circuit 75, 78 to 80, 87 to 94 which constitutes a means Inverter 85 and 86 which constitutes a cutoff control means NOR circuit BL ₁ , BL ₁ bar to BL _2n , BL _2n bar Bit line pair C Memory cell GND Ground power supply Vcc power supply WL ₁ , WL ₂ Word line

Claims (6)

[Claims] 1. A memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit line pairs, capable of reading and writing data from and to any memory cell, and a latch circuit composed of an inverter. A first memory having a plurality of sense amplifiers for amplifying the potentials of the plurality of bit line pairs, a serial register having a plurality of cells that are serially accessed, and a serial register having a plurality of cells that are serially accessed. A second memory provided with an activation circuit for activating the plurality of cells by supplying power to a register, and a second memory provided between the first memory and the second memory are provided. In a semiconductor memory device including a transfer gate for transferring a plurality of data in one of the memories to the other memory To control the activation circuit so that the power supply to the serial register is cut off when the plurality of data in the second memory are transferred to the first memory by making the transfer gate conductive. A semiconductor memory device provided with a cutoff control means. 2. The serial register is divided into a plurality of blocks, each block including a plurality of cells,
2. The semiconductor memory device according to claim 1, wherein the transfer gate has conduction control of a gate corresponding to each of the blocks. 3. The cut-off control means controls the activation circuit so that the supply of power to the serial register is cut off for a predetermined time based on the conduction of the transfer gate. Semiconductor memory device. 4. The cutoff control means controls the activation circuit so that supply of power to the serial register is cut off only during a period when the transfer gate is conductive. Semiconductor memory device. A semiconductor memory device including. 5. A plurality of the activation circuits are provided corresponding to a plurality of blocks of the serial register, and the cutoff control means is provided for a predetermined time based on conduction of a transfer gate corresponding to a block to which data is to be transferred. 3. The semiconductor memory device according to claim 2, wherein the activation circuit corresponding to the block is controlled so that the power supply to the block to which the data is to be transferred is cut off. 6. A plurality of the activation circuits are provided corresponding to a plurality of blocks of the serial register, and the cutoff control means is provided only during a period when a transfer gate corresponding to a block to which data is transferred is conductive. 3. The semiconductor memory device according to claim 2, wherein an activation circuit corresponding to a block to which the data is to be transferred is controlled so that power supply to the block is shut off.