JP2007273079A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute transfer of data from a write-register to a read-register, or from the read-register to the write-register. <P>SOLUTION: The semiconductor integrated circuit executing transfer of data between registers is provided with; a first transistor in which one side of terminals is connected to a power source potential and the other side of the terminals is connected to a power source line of the register, and which is made a non-conduction state so that supply of the power source potential for the power source line is stopped during data transfer of the register; a second transistor in which one side of terminals is connected to aground potential and the other side of the terminals is connected to a ground line, and which is made a non-conduction state so that supply of the ground potential for the ground line is stopped during data transfer; and a third transistor which is connected to the power source line and the ground line of the register and which is made a conduction state before start of data transfer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a read register and a write register, such as a first in first out (FIFO) memory and a video random access memory (VRAM).

Conventionally, as such a technique, for example, there is one disclosed in Patent Document 1 below. Patent Document 1 describes a semiconductor integrated circuit having a plurality of write registers composed of two inverters and read registers composed of two inverters. Data stored in the write register is transferred to the read register via the transfer gate.
As prior art documents related to the present application, there are the following.
JP 7-65569 A JP-A-8-273349 JP-A-3-25787 JP-A-4-67391 JP 7-312084 A

  However, Patent Document 1 does not specify the relationship between the drive capability of the read register inverter and the drive capability of the write register inverter. When the drive capability of the read register inverter is larger than the drive capability of the write register inverter, the data transferred from the write register may be inverted by the read register. Therefore, a further improved semiconductor integrated circuit has been desired.

  The present invention provides a semiconductor integrated circuit that solves the above problems. In a semiconductor integrated circuit that transfers data between registers, a representative one of the present invention has one terminal connected to a power supply potential and the other terminal connected to a power supply line of the register. The first transistor which is in a non-conducting state to stop the supply of the power supply potential to the power supply line, one terminal is connected to the ground potential, the other terminal is connected to the ground line of the register, and the data transfer A second transistor that is turned off to stop the supply of the ground potential to the ground line, and a second transistor that is connected to the power supply line and the ground line of the register and is turned on before the data transfer is started. 3 is a semiconductor integrated circuit having three transistors.

  According to the representative example of the present invention, during the data transfer, the read register power supply line RRVDD is lower than the power supply potential, so that the apparent drive capability of the read register inverter is lowered. As a result, data transfer from the write register is executed without malfunction.

(First embodiment)
FIG. 1 is a block diagram of a semiconductor integrated circuit including a write register and a read register. The semiconductor integrated circuit of FIG. 1 is used for FIFO, VRAM, and the like.
The write registers 101, 103, 105 and 107 are connected to the write register power line WRVDD and the write register power line WRGND. For example, a power supply (VDD) for supplying a potential of 5 V is directly connected to the power supply line WRVDD. For example, a power supply (GND) that supplies a potential of 0 V is directly connected to the power supply line WRGND.

  The read registers 109, 111, 113, and 115 are connected to the read register power line RRVDD and the read register power line RRGND. The element shown in FIG. 5 is connected to the power supply line RRVDD. Similarly to the power supply line WRGND, for example, a power supply that supplies a potential (GND) of 0 V is directly connected to the power supply line RRGND. FIG. 5 will be described later.

  A transfer gate controlled by the output of the write pointer is connected between the write data buses WDB and WDBZ and the write register. The transfer gate is composed of a transistor having a gate electrode that receives the output of the write pointer. A transfer gate controlled by the output of the read pointer is connected between the read data buses RDB and RDBZ and the read register. The transfer gate is composed of a transistor having a gate electrode that receives the output of the read pointer.

  A data transfer gate controlled by a data transfer signal TRANS is connected between the write register and the read register. The data transfer gate is composed of a transistor having a gate electrode that receives the data transfer signal TRANS.

  FIG. 2 is a detailed circuit diagram of the write register and the read register. The write register is composed of an inverter INV1 composed of an NMOS transistor NTR1 and a PMOS transistor PTR1, and an inverter INV2 composed of an NMOS transistor NTR2 and a PMOS transistor PTR2. The input terminal of the inverter INV1 and the output terminal of the inverter INV2 are commonly connected to the line 203 connected to the write data bus WDBZ. The output terminal of the inverter INV1 and the input terminal of the inverter INV2 are connected in common to the line 201 connected to the write data bus WDB. The source electrodes of the PMOS transistors PTR1 and PTR2 are connected to the power supply line WRVDD. The source electrodes of the NMOS transistors NTR1 and NTR2 are connected to the power supply line WRGND.

  The read register includes an inverter INV3 including an NMOS transistor NTR3 and a PMOS transistor PTR3, and an inverter INV4 including an NMOS transistor NTR4 and a PMOS transistor PTR4. The input terminal of the inverter INV3 and the output terminal of the inverter INV4 are commonly connected to a line 207 connected to the read data bus RDBZ. The output terminal of the inverter INV3 and the input terminal of the inverter INV4 are connected in common to the line 205 connected to the read data bus RDB.

  The source electrodes of the PMOS transistors PTR3 and PTR4 are connected to the power supply line RRVDD. The source electrodes of the NMOS transistors NTR3 and NTR4 are connected to the power supply line RRGND.

  NMOS transistors NTR5 and NTR6 are connected between the write register and the read register.

  FIG. 3 is a circuit diagram of the transfer control circuit. This transfer control circuit is a circuit that generates a data transfer signal TRANS and control signals TRANSU and TRANSUZ for controlling a power supply for a register, which will be described later, in response to a transfer enable signal. While receiving the L level transfer enable signal, the transfer control circuit outputs an H level control signal TRANSUZ, an L level control signal TRANSU, and an L level data transfer signal TRANS. When the transfer enable signal changes from the L level to the H level, the L-level control signal TRANSSUZ, the H-level control signal TRANSU, and the H-level data are illustrated according to a delay time determined by a delay circuit including a plurality of inverters. A transfer signal TRANS is output. The L level period of the control signal TRANSUZ and the H level period of the control signal TRANSU are substantially the same. The H level period of the data transfer signal TRANS is the end of the H level period of the control signal TRANSU.

  FIG. 5 shows a power supply potential level transfer circuit for a read register. As described above, the power supply line RRGND is directly connected to a power supply (GND) that supplies a potential of 0V. A PMOS transistor PTR5 controlled by a data transfer signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. A high resistance element is connected between the power supply line RRVDD and the power supply GND.

  Next, the operation of the first embodiment will be described.

  First, write data is supplied to the write data buses WDB and WDBZ. For example, the H level is supplied to the write data bus WDB, and the L level is supplied to the write data bus WDBZ. When the write pointer 1 outputs H level, the transfer gate is turned on, and the data given to the write data buses WDB and WDBZ is transferred to the write register 101. The write register 101 latches the H level given to the line 201 and the L level given to the line 203. That is, the data given to the write data buses WDB and WDBZ is written into the write register 101.

  Next, when the write pointer 1 outputs L level, the transfer gate is turned off, and the transfer of data to the write register 101 is completed.

  Next, new write data is supplied to the write data buses WDB and WDBZ. For example, the L level is supplied to the write data bus WDB, and the H level is supplied to the write data bus WDBZ. When the write pointer 2 outputs H level, the transfer gate is turned on, and the data given to the write data buses WDB and WDBZ is transferred to the write register 103. The write register 103 latches the L level given to the line 201 and the H level given to the line 203. That is, the data given to the write data buses WDB and WDBZ is written into the write register 103.

  Next, when the write pointer 2 outputs L level, the transfer gate is turned off, and the transfer of data to the write register 103 is completed.

  The above operation is repeated from the write registers 101 to 107.

  Next, when the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR5 is turned off. Since the power supply line RRVDD is connected to GND through a high resistance element, when the transistor PTR5 is turned off, the potential level of the power supply line RRVDD gradually decreases from about VDD level toward the GND level. When the potential level of the power supply line RRVDD is lowered, the drive capability of the inverters INV3 and INV4 is lowered.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD is lowered, the drive capability of the inverters INV3 and INV4 is smaller than the drive capability of the inverters INV1 and INV2. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203. That is, it means that the data in the write register is accurately written in the read register.

  Next, the control signal TRANSU and the data transfer signal TRANS change to L level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR5 is turned on, so that the potential level of the power supply line RRVDD rises to about VDD level. When the potential level of the power supply line RRVDD becomes the VDD level, the driving capabilities of the inverters INV3 and INV4 are restored. Therefore, the read register can accurately latch the data transferred from the write register.

  FIG. 4 is a diagram showing a reference technique related to the present invention. In order to clarify the effects of the present invention below, the present invention and the reference technique will be compared.

This reference technique includes a PMOS transistor connected between the power supply line RRVDD and the power supply VDD and controlled by a control signal TRANSU, and an NMOS transistor connected between the power supply lines RRGND and GND and controlled by a control signal TRANSUZ. And have. In this reference technique, these transistors are turned off during data transfer. In this reference technique, the power supply line RRVDD and the power supply line RRGND are in a floating state during data transfer. Therefore, noise is supplied to the power supply line RRVDD, and the potential level of the power supply line RRVDD may be higher than the VDD level. When the potential level of the power supply line RRVDD becomes higher than the VDD level, the drive capability of the read register is apparently larger than the drive capability of the write register during data transfer. Therefore, data transferred from the write register may be changed by the read register.

  According to the present invention, since the drive capability of the read register is made lower than the drive capability of the write register only at the time of data transfer, the data transferred from the write register is not changed by the read register. Therefore, the data transfer is executed accurately.

  (Second Embodiment) The difference between the second embodiment and the first embodiment is the configuration of the power supply potential level transfer circuit for the read register.

  FIG. 6 shows a power supply potential level transfer circuit for a read register according to the second embodiment. As described above, the power supply line RRGND is directly connected to a power supply (GND) that supplies a potential of 0V. A PMOS transistor PTR6 controlled by the control signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. A high-resistance element and an NMOS transistor NTR7 controlled by a control signal TRANSU are connected between the power supply line RRVDD and the power supply GND.

  This power supply potential level transfer circuit is controlled by the output of the transfer control circuit of FIG.

  Next, the operation of the second embodiment will be described.

  When the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR6 is turned off and the transistor NTR7 is turned on. Since the power supply line RRVDD is connected to GND via the high resistance element and the transistor NTR7, the potential level of the power supply line RRVDD gradually decreases from about VDD level in the GND level direction. When the potential level of the power supply line RRVDD is lowered, the drive capability of the inverters INV3 and INV4 is lowered.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD is lowered, the drive capability of the inverters INV3 and INV4 is smaller than the drive capability of the inverters INV1 and INV2. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203. That is, the data in the write register is accurately written in the read register.

  Next, the control signal TRANSU and the data transfer signal TRANS change to L level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR6 is turned on and the transistor NTR7 is turned off, so that the potential level of the power supply line RRVD rises to about VDD level. When the potential level of the power supply line RRVDD becomes the VDD level, the driving capabilities of the inverters INV3 and INV4 are restored. Therefore, the read register can accurately latch the data transferred from the write register.

  According to the present invention, since the drive capability of the read register is made lower than the drive capability of the write register only at the time of data transfer, the data transferred from the write register is not changed by the read register. Therefore, data transfer is surely executed.

  Further, according to the second embodiment, the power supply line RRVDD is connected to the power supply GND via the resistor only at the time of data transfer. That is, no current flows from the power supply VDD to the power supply GND in a state other than during data transfer. Therefore, in the second embodiment, data transfer can be ensured and power consumption can be reduced.

  (Third Embodiment) The difference between the third embodiment and the first embodiment is the configuration of the power supply potential level transfer circuit for the read register.

  FIG. 7 shows a power supply potential level transfer circuit for a read register according to the third embodiment.

  A PMOS transistor PTR7 controlled by a control signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. A high resistance element is connected between the power supply line RRVDD and the power supply GND. An NMOS transistor NTR8 controlled by a control signal TRANSUZ is connected between the power supply lines RRGND and GND. A high resistance element is connected between the power supply line RRGND and the power supply VDD.

  This power supply potential level transfer circuit is controlled by the output of the transfer control circuit of FIG.

  Next, the operation of the third embodiment will be described.

  When the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period, and the control signal TRANSUZ becomes L level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR7 is turned off and the transistor NTR8 is turned off. Since the power supply line RRVDD is connected to GND through a high resistance element, the potential level of the power supply line RRVDD gradually decreases from about VDD level toward the GND level. Since the power supply line RRGND is connected to the power supply VDD via a high resistance element, the potential level of the power supply line RRGND gradually rises from the GND level in the VDD level direction.

  When the potential level of the power supply line RRVDD is decreased and the potential level of the power supply line RRGND is increased, the driving ability of the inverters INV3 and INV4 is decreased.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD has decreased and the potential level of the power supply line RRGND has increased, the drive capability of the inverters INV3 and INV4 is smaller than the drive capability of the inverters INV1 and INV2. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203. That is, the data in the write register is accurately written in the read register.

  Next, the control signal TRANSU and the data transfer signal TRANS change to L level, and the control signal TRANSUZ changes to H level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR7 is turned on, so that the potential level of the power supply line RRVDD rises to about VDD level. When the control signal TRANSUZ becomes H level, the transistor NTR8 is turned on, so that the potential level of the power supply line RRGND falls to the GND level. When the potential level of the power supply line RRVDD becomes the VDD level and the potential level of the power supply line RRGND becomes the GND level, the drive capability of the inverters INV3 and INV4 is restored. Therefore, the read register can accurately latch the data transferred from the write register.

  According to the present invention, since the drive capability of the read register is made lower than the drive capability of the write register only at the time of data transfer, the data transferred from the write register is not changed by the read register. Therefore, data transfer is surely executed.

  Furthermore, in the third embodiment, since the potential levels of both the power lines RRVDD and RRGND of the read register are changed during data transfer, the data is transferred more accurately than in the first embodiment. be able to.

  (Fourth Embodiment) The difference between the fourth embodiment and the second embodiment is the configuration of the power supply potential level transfer circuit for the read register.

  FIG. 8 shows a power supply potential level transfer circuit for a read register according to the fourth embodiment.

  A PMOS transistor PTR8 controlled by the control signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. A high resistance element and an NMOS transistor PTR9 controlled by a control signal TRANSU are connected between the power supply line RRVDD and the power supply GND. An NMOS transistor NTR10 controlled by a control signal TRANSUZ is connected between the power supply lines RRGND and GND. A high resistance element and a PMOS transistor PTR9 controlled by a control signal TRANSUZ are connected between the power supply line RRGND and the power supply VDD.

  This power supply potential level transfer circuit is controlled by the output of the transfer control circuit of FIG.

  Next, the operation of the fourth embodiment will be described.

  When the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period, and the control signal TRANSUZ becomes L level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR8 is turned off and the transistor NTR9 is turned on. Since the power supply line RRVDD is connected to GND via the high resistance element and the transistor NTR9, the potential level of the power supply line RRVDD gradually decreases from about VDD level toward the GND level. When the control signal TRANSUZ becomes L level, the transistor NTR10 is turned off and the transistor PTR9 is turned on. Since the power supply line RRGND is connected to VDD through the high resistance element and the transistor PTR9, the potential level of the power supply line RRGND gradually rises from the GND level toward the VDD level. When the potential level of the power supply line RRVDD is decreased and the potential level of the power supply line RRGND is increased, the driving ability of the inverters INV3 and INV4 is decreased.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD has decreased and the potential level of the power supply line RRGND has increased, the drive capability of the inverters INV3 and INV4 is smaller than the drive capability of the inverters INV1 and INV2. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203. That is, it means that the data in the write register is accurately written in the read register.

  Next, the control signal TRANSU and the data transfer signal TRANS change to L level, and the control signal TRANSUZ changes to H level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR8 is turned on and the transistor NTR9 is turned off, so that the potential level of the power supply line RRVDD rises to about VDD level. When the control signal TRANSUZ becomes H level, the transistor NTR10 is turned on and the transistor PTR9 is turned off, so that the potential level of the power supply line RRGND falls to the GND level.

  When the potential level of the power supply line RRVDD becomes the VDD level and the potential level of the power supply line RRGND becomes the GND level, the drive capability of the inverters INV3 and INV4 is restored. Therefore, the read register can accurately latch the data transferred from the write register.

  According to the present invention, since the drive capability of the read register is made lower than the drive capability of the write register only at the time of data transfer, the data transferred from the write register is not changed by the read register. Therefore, data transfer is surely executed.

  Furthermore, according to the fourth embodiment, the power supply line RRVDD is connected to the power supply GND via a resistor only during data transfer, and the power supply line RRGND is connected to the power supply VDD via a resistor only during data transfer. That is, no current flows from the power supply VDD to the power supply GND in a state other than during data transfer. Therefore, the fourth embodiment can ensure data transfer and reduce power consumption.

  (Fifth Embodiment) The difference between the fifth embodiment and the first embodiment is the configuration of the transfer control circuit and the power supply potential level transfer circuit for the read register.

  FIG. 9 is a circuit diagram of a transfer control circuit according to the fifth embodiment. This transfer control circuit is a circuit that generates a data transfer signal TRANS, control signals TRANSU and TRANSUZ for controlling the power supply for registers, and an equalize control signal TRANSSEQ in response to the transfer enable signal. While receiving the L level transfer enable signal, the transfer control circuit outputs an H level control signal TRANSUZ, an L level control signal TRANSU, an L level data transfer signal TRANS, and an L level equalize control signal TRANSSEQ. . When the transfer enable signal changes from the L level to the H level, the L-level control signal TRANSSUZ, the H-level control signal TRANSU, and the H-level data are illustrated according to a delay time determined by a delay circuit including a plurality of inverters. The transfer signal TRANS and the H level equalization control signal TRANSSEQ are output. The L level period of the control signal TRANSUZ and the H level period of the control signal TRANSU are substantially the same. The H level period of the data transfer signal TRANS is the end of the H level period of the control signal TRANSU. The H level period of the equalize control signal TRANSSEQ is immediately before the H level period of the data transfer signal TRANS.

  FIG. 10 shows a power supply potential level transfer circuit for a read register. A PMOS transistor PTR10 controlled by a control signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. An NMOS transistor NTR11 that is controlled by a control signal TRANSUZ is connected between the power supply lines RRGND and GND. An NMOS transistor NTR12 controlled by an equalize control signal TRANSEQ is connected between the power supply line RRVDD and the power supply line RRGND.

  Next, the operation of the fifth embodiment will be described.

  When the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period, and the control signal TRANSUZ becomes L level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR10 is turned off. When the control signal TRANSUZ becomes L level, the transistor NTR11 is turned off.

  Next, the equalize control signal TRANSEQ becomes H level. When the equalize control signal TRANSSEQ becomes H level, the power supply line RRVDD and the power supply line RRGND are electrically connected. Therefore, the potential level of the power supply line RRVDD and the potential level of the power supply line RRGND are equal. At this time, the potential level of the power supply line RRVDD and the potential level of the power supply line RRGND are approximately ½ VDD level. This 1/2 VDD level is the threshold voltage level of the inverters INV3 and INV4.

  When the potential level of the power supply line RRVDD and the potential level of the power supply line RRGND become the same level, the states of the inverters INV3 and INV4 become inactive.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD and the potential level of the power supply line RRGND are the same level, the states of the inverters INV3 and INV4 are inactive. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203.

  That is, the data in the write register is written into the read register accurately and rapidly.

  Next, the control signal TRANSU and the data transfer signal TRANS change to L level, and the control signal TRANSUZ changes to H level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR10 is turned on, so that the potential level of the power supply line RRVDD rises to about VDD level. When the control signal TRANSUZ becomes H level, the transistor NTR11 is turned on, so that the potential level of the power supply line RRGND falls to the GND level.

  When the potential level of the power supply line RRVDD becomes the VDD level and the potential level of the power supply line RRGND becomes the GND level, the states of the inverters INV3 and INV4 return to the operating state. Therefore, the read register can accurately latch the data transferred from the write register.

  In the fifth embodiment, since the data transfer is performed while the read register is in the non-operating state, the data transfer can be made faster than in the first to fourth embodiments. It is.

  Furthermore, the power supply potential level transfer circuit of the fifth embodiment does not use a high resistance element. Therefore, the present invention can reduce the pattern area and is less likely to be affected by variations in the manufacturing process.

  (Sixth Embodiment) The difference between the sixth embodiment and the fifth embodiment is the configuration of the power supply potential level transfer circuit for the read register.

  FIG. 11 shows a power supply potential level transfer circuit for a read register. A PMOS transistor PTR11 controlled by the control signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. An NMOS transistor NTR14 controlled by an equalize control signal TRANSEQ is connected between the power supply line RRVDD and the power supply HVDD. The power supply HVDD is about half the potential level of the power supply VDD. An NMOS transistor NTR13 controlled by a control signal TRANSUZ is connected between the power supply lines RRGND and GND.

  Next, the operation of the sixth embodiment will be described.

  When the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period, and the control signal TRANSUZ becomes L level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR11 is turned off. When the control signal TRANSUZ becomes L level, the transistor NTR13 is turned off.

  Next, the equalize control signal TRANSEQ becomes H level. When the equalize control signal TRANSSEQ becomes H level, the transistor NTR14 is turned on. When the transistor NTR14 is turned on, the potential level of the power supply line RRVDD becomes ½VDD level. This 1/2 VDD level is the threshold voltage level of the inverters INV3 and INV4.

  When the potential level of the power supply line RRVDD becomes ½ VDD level, the drive capability of the inverters INV3 and INV4 is reduced.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD is ½ VDD level, the drive capability of the inverters INV3 and INV4 is reduced. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203.

  That is, the data in the write register is written into the read register accurately and rapidly.

  Next, the control signal TRANSU and the data transfer signal TRANS change to L level, and the control signal TRANSUZ changes to H level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR11 is turned on, so that the potential level of the power supply line RRVDD becomes about VDD level. When the control signal TRANSUZ becomes H level, the transistor NTR13 is turned on, so that the potential level of the power supply line RRGND becomes GND level.

  When the potential level of the power supply line RRVDD becomes the VDD level and the potential level of the power supply line RRGND becomes the GND level, the states of the inverters INV3 and INV4 are restored. Therefore, the read register can accurately latch the data transferred from the write register.

  In the sixth embodiment, since the drive capability of the read register is lowered below the drive capability of the write register only at the time of data transfer, the data transferred from the write register can be changed by the read register. Absent. Therefore, data transfer is surely executed.

  Furthermore, the sixth embodiment is effective when there is not enough space between the power supply line RRVDD and the power supply line RRGND to form the transistor NTR12 as shown in FIG.

  (Seventh Embodiment) The difference between the seventh embodiment and the sixth embodiment is the configuration of the power supply potential level transfer circuit for the read register.

  FIG. 12 shows a power supply potential level transfer circuit for a read register. A PMOS transistor PTR12 that is controlled by a control signal TRANSU is connected between the power supply line RRVDD and the power supply VDD. An NMOS transistor NTR17 controlled by an equalize control signal TRANSEQ is connected between the power supply line RRVDD and the power supply HVDD. The power supply HVDD is about half the potential level of the power supply VDD. An NMOS transistor NTR15 controlled by a control signal TRANSUZ is connected between the power supply lines RRGND and GND. An NMOS transistor NTR16 controlled by an equalize control signal TRANSEQ is connected between the power supply line RRVDD and the power supply line RRGND.

  Next, the operation of the seventh embodiment will be described.

  When the transfer enable signal changes from L level to H level, the control signal TRANSU becomes H level for a predetermined period, and the control signal TRANSUZ becomes L level for a predetermined period. When the control signal TRANSU becomes H level, the transistor PTR12 is turned off. When the control signal TRANSUZ becomes L level, the transistor NTR15 is turned off.

  Next, the equalize control signal TRANSEQ becomes H level. When the equalize control signal TRANSSEQ becomes H level, the transistors NTR16 and NTR17 are turned on. When the transistors NTR16 and NTR17 are turned on, the potential level of the power supply line RRVDD and the potential level of the power supply line RRGND become ½ VDD level. This 1/2 VDD level is the threshold voltage level of the inverters INV3 and INV4.

  When the potential level of the power supply line RRVDD becomes the ½ VDD level, the states of the inverters INV3 and INV4 become inactive.

  Next, the data transfer signal TRANS becomes H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD and the potential level of the power supply line RRGND are 1/2 VDD levels, the states of the inverters INV3 and INV4 are inactive. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203.

  That is, the data in the write register is written into the read register accurately and rapidly.

Next, the control signal TRANSU and the data transfer signal TRANS change to L level, and the control signal TRANSUZ changes to H level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected. When the control signal TRANSU becomes L level, the transistor PTR12 is turned on, so that the potential level of the power supply line RRVDD becomes about VDD level. When the control signal TRANSUZ becomes H level, the transistor NTR15 is turned on, so that the potential level of the power supply line RRGND becomes GND level.

  When the potential level of the power supply line RRVDD becomes the VDD level and the potential level of the power supply line RRGND becomes the GND level, the states of the inverters INV3 and INV4 return to the operating state. Therefore, the read register can accurately latch the data transferred from the write register.

  In the seventh embodiment, since the data transfer is performed while the read register is in the non-operating state, the data transfer can be performed at a higher speed.

  Furthermore, in the fifth embodiment, there is a possibility that the potential levels of the power supply lines RRVDD and RRGND are not exactly ½ VDD level, but in the seventh embodiment, the potential levels of the power supply lines RRVDD and RRGND are Can be reliably set to the 1/2 VDD level. Therefore, in the seventh embodiment, data transfer can be performed at higher speed than the fifth embodiment.

(Eighth Embodiment) The difference between the eighth embodiment and the first embodiment is the configuration of the transfer control circuit and the power supply potential level transfer circuit for the read register.

  FIG. 14 is a circuit diagram of a transfer control circuit according to the eighth embodiment. This transfer control circuit is a circuit that generates a data transfer signal TRANS in response to a transfer enable signal. The transfer control circuit outputs an L level data transfer signal TRANS while receiving the L level transfer enable signal. When the transfer enable signal changes from the L level to the H level, the H level data transfer signal TRANS as shown in the figure is output according to the delay time determined by the delay circuit composed of a plurality of inverters.

  FIG. 13 shows a power supply potential level transfer circuit for a read register. An NMOS transistor NTR18 having a gate electrode to which the power supply VDD is supplied is connected between the power supply line RRVDD and the power supply VDD. This transistor NTR18 is a normally-on type transistor. The potential level of the power supply line RRVDD is always the VDD-VT level. VT is a threshold voltage of the transistor NTR18. A power supply for supplying a potential of 0 V (GND) is directly connected to the power supply line RRGND. Therefore, the potential level of the power supply line RRGND is always the GND level.

  Next, the operation of the eighth embodiment will be described.

  When the transfer enable signal changes from the L level to the H level, the data transfer signal TRANS becomes the H level. When the data transfer signal TRANS becomes H level, the transistors NTR5 and NTR6 are turned on, so that the line 201 and the line 205 are electrically connected, and the line 203 and the line 207 are electrically connected. Now, since the potential level of the power supply line RRVDD is the VDD-VT level, the driving capability of the inverters INV3 and INV4 is lower than the driving capability of the inverters INV1 and INV2. Therefore, the potential level of the line 205 easily changes depending on the potential level of the line 201, and the potential level of the line 207 easily changes depending on the potential level of the line 203.

  That is, the data in the write register is written into the read register accurately and rapidly.

  Next, the data transfer signal TRANS changes to L level. When the data transfer signal TRANS becomes L level, the transistors NTR5 and NTR6 are turned off, so that the line 201 and the line 205 are electrically disconnected, and the line 203 and the line 207 are electrically disconnected.

  In the eighth embodiment, since the potential level of the power supply line RRVDD is always lower than the potential level of the power supply line WRVDD, data transfer can be executed reliably.

  Furthermore, since the transfer control circuit of the eighth embodiment only needs to generate a data transfer signal, the transfer control circuit can be simplified. Therefore, the pattern area can be reduced as a whole semiconductor integrated circuit.

  In the first to eighth embodiments, the case where data is transferred from the write register to the read register (particularly the FIFO memory) has been described. However, the case where data is transferred from the read register to the write register (particularly the VRAM) is also conceivable.

  In that case, the present invention may be applied to the power line for the write register.

It is a block diagram of a semiconductor integrated circuit including a register. It is a figure which shows the structure of a register. It is a figure which shows a transfer control circuit. It is a reference diagram of a power supply potential level transfer circuit. 1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows the 2nd Embodiment of this invention. It is a circuit diagram which shows the 3rd Embodiment of this invention. It is a circuit diagram which shows the 4th Embodiment of this invention. It is a circuit diagram which shows the 5th Embodiment of this invention. It is a circuit diagram which shows the 5th Embodiment of this invention. It is a circuit diagram which shows the 6th Embodiment of this invention. It is a circuit diagram which shows the 7th Embodiment of this invention. It is a circuit diagram which shows the 8th Embodiment of this invention. It is a circuit diagram which shows the 8th Embodiment of this invention.

Explanation of symbols

RRVDD ・ ・ ・ Power line for read register
RRGND ・ ・ ・ Power line for read register
RDB: Read data bus
RDBZ ・ ・ ・ Read data bus
WDB: Write data bus
WDBZ: Write data bus

Claims (8)

In semiconductor integrated circuits that transfer data between registers,
A first transistor having one terminal connected to a power supply potential, the other terminal connected to a power supply line of the register, and being in a non-conductive state so as to stop supply of the power supply potential to the power supply line during the data transfer;
A second transistor having one terminal connected to a ground potential, the other terminal connected to a ground line of the register, and being non-conductive so as to stop the supply of the ground potential to the ground line during the data transfer;
A semiconductor integrated circuit comprising: a third transistor connected to the power supply line and the ground line of the register and brought into a conductive state before the data transfer is started. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the first transistor is a PMOS transistor, and the second transistor and the third transistor are NMOS transistors. The semiconductor integrated circuit according to claim 1 or 2,
The semiconductor integrated circuit according to claim 1, wherein the first transistor and the second transistor are turned off before the data transfer is started. The semiconductor integrated circuit according to claim 3.
2. The semiconductor integrated circuit according to claim 1, wherein the third transistor is turned on after the first transistor and the second transistor are turned off. In the semiconductor integrated circuit according to any one of claims 1 to 4,
The semiconductor device further includes a fourth transistor having one terminal connected to a potential lower than a power supply potential, the other terminal connected to a power supply line of the register, and a conductive state before the data transfer is started. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5, wherein
The semiconductor integrated circuit according to claim 4, wherein the fourth transistor is an NMOS transistor. The semiconductor integrated circuit according to claim 5 or 6,
A semiconductor integrated circuit, wherein the fourth transistor is turned on after the first transistor and the second transistor are turned off. The semiconductor integrated circuit according to claim 7.
The semiconductor integrated circuit according to claim 4, wherein the fourth transistor is in the conductive state simultaneously with the third transistor.

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