JPH05101663A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the current consumption for data transfer by connecting voltage holding contacts of complementary data registers to each other by a transistor switch. CONSTITUTION:An N-type MOS transistor TR 16 which takes a signal line BAL as the gate input is added between capacitors 30 and 31. After data register power supply is stopped, the signal BAL is set to the high level, and the transistor switch 16 between data register voltage holding contacts is opened. Thus, data register voltage holding contacts are balanced at 1/2 Vcc, and transistor switches 20 and 21 which connect bit lines BL and the inverse of BL and data registers LB and the inverse of LB respectively are opened, and data transfer is completed. Since contacts of registers LB and the inverse of LB have levels only varied from 1/2 Vcc at the time of opening the transistor switches, the electric charge discharged by a sense amplifier 1 is reduced to a half, and the current is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a DT operation (transfer of sensed bit data to a complementary data register capable of controlling power supply connected to each bit line through a transistor switch). ) A memory circuit having a function.

[0002]

2. Description of the Related Art In a conventional circuit, no transistor switch is provided between the voltage holding contacts of the complementary data register.

FIG. 3 shows such a conventional circuit diagram.

In FIG. 3, the conventional semiconductor memory includes a sense amplifier 1, bit lines BL and BL (inverted value), data register power supply signals PC and PC (inverted value), and data register contacts LB and LB ( N-type MOS transistors 20 and 21 whose gate inputs are the inverted value) and the DT signal.
, A P-type MOS transistor 11 having a signal PC as a gate input, an N-type MOS transistor 13 having a signal PC (inverted value) as a gate input, and a P-type MOS transistor 1
0, 12, N-type MOS transistors 14 and 15, and capacitors 30 and 31.

In FIG. 4, each part of the circuit of FIG. 3 is displaced between the power supply voltage VCC and the ground (GND). The DT operation in FIG. 3 will be described with reference to FIG. In FIG. 3 and FIG. 4, after the sensing operation of the bit lines BL and BL (inverted value) is completed, the data register power supply signals PC and PC
The power supply to the data register is stopped by setting the (inverted value) to the high / low level. After that, the transistor switches connecting the bit lines BL and BL (inverted value) and the contacts LB and LB (inverted value) of the data register are opened. As a result, the level of the contact LB / LB (inverted value) of the data register changes to the level of the bit line BL / BL (inverted value), and finally, the power is applied to the data register, so that the bit line BL to the data register is changed. • Complete the BL (inverted value) data transfer.

[0006]

In such a conventional circuit, when the transistor switches connecting the bit lines BL and BL (inverted value) and the contacts LB and LB (inverted value) of the data register respectively are opened. At the time (t1 in FIG. 4), the sense amplifier 1 discharges the electric charges charged in the contacts LB and LB (inversion value), and thus has a drawback that a large current is consumed.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a semiconductor memory which does not consume a large current.

[0008]

The structure of the semiconductor memory of the present invention is characterized in that the voltage holding contacts of the complementary data register are connected to each other by a transistor switch.

[0009]

1 is a circuit diagram showing a semiconductor memory according to an embodiment of the present invention, and FIG. 2 is a timing chart showing operation waveforms of respective portions of FIG.

In FIG. 1, one embodiment of the present invention is shown in FIG.
An N-type MOS transistor 16 having a BAL signal line as a gate input is added between the capacitors 30 and 31 and the other parts are the same as in FIG.

The DT operation will be described with reference to FIG.

Also in the circuit operation of this embodiment, the operation is the same as the conventional circuit up to the point where the data register power supply is stopped.

Then, the BAL signal is set to High to open the transistor switch between the data register voltage holding contacts.

As a result, the data register voltage holding contact is balanced to 1/2 Vcc. After that, similar to the conventional circuit operation, the transistor switch connecting each of the bit lines BL and BL (inverted value) and the data register LB and LB (inverted value) is opened, and the contact L of the data register is connected.
The level of B.LB (inverted value) changes to the level of the bit line BL.BL (inverted value), and finally the power is applied to the data register, so that the bit line BL.BL.
The BL (inverted value) data transfer is completed.

[0015]

As described above, in the circuit of the present invention, for example, the transistor switches connecting the bit lines BL and BL (inverted value) and the contacts LB and LB (inverted value) of the data transistor are opened. At the time of t1 (t1), the level change of the contacts LB and LB (reversal value) from 1/2 Vcc is sufficient, so that the charge for the sense amplifier 1 to pull out is halved compared to the conventional circuit, and therefore the current There is an effect that it decreases.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory according to an embodiment of the present invention.

2 is a timing diagram showing DT operation waveforms of the circuit of FIG.

FIG. 3 is a circuit diagram of a conventional semiconductor memory.

4 is a timing diagram showing DT operation waveforms of the circuit of FIG.

[Explanation of symbols]

1 sense amplifier 10, 11, 12 P-type MOS transistor 13, 14, 15, 16, 20, 21 N-type MOS transistor BL • BL (inversion value) bit line LB. LB (reversed value) data transistor contact

Claims (1)

[Claims] 1. A semiconductor memory, wherein two voltage holding contacts of a data register are connected to each other through a transistor switch.