JPH01138689A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the cycle time of a dynamic RAM by taking in a column address in preference to a row address in a read cycle as well as a write cycle. CONSTITUTION:In the read cycle, a word line MW1 is selected and data in a dynamic RAM cell MC1 and a dummy cell DC2 is transferred to a latch type memory cell 20 when the inverse of a row address strobe RAS is switched from '1' to '0'. When the inverse of a column address strobe CAS is switched to '0' in preference to the inverse of the RAS at this time, a column selection line CSLi is selected just after word line section and data is read out to the external, and thereafter, a transfer gate 30 between bit lines BL and the inverse of BL and the latch type memory cell 20 is turned off, and bit lines are precharged with the inverse of RAS kept in the '0' state. In the write cycle, the timing of bit line precharge in the active period of the inverse of the RAS is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and particularly to a dynamic RAM (dRAM) that integrates dynamic memory cells that perform destructive reading.

(Conventional technology) In recent years, computers have become larger and faster.

However, it has become difficult to further increase both capacity and speed. For example, when static RAM (s RAM) is used as the main memory, dynamic RAM (dRAM)
In the case of dRAM, the price is also higher than in the case of dRAM. d
When RAM is used as the main memory, the speed is s
Inferior to RAM.

The reason why dRAM is inferior to sRAM in operating speed is that dRAM has conventionally adopted an address multi-letter system to increase the degree of integration and reduce bit cost. Also, since dRAM is a destructive read type,
There are also circumstances in which refresh and bit line precharge are required.

The machine cycle of a computer using sRAM as a main memory is determined only by the access time of sRAM, but in the case of dRAM, the machine cycle is determined by the access time and bit line precharge time.

and conventional address multiplexed dRAM.
On the system, the address data selector is
It is controlled using only address strobe (CAS) information, and there is no distinction between dRAM read cycles and write cycles. That is, in the active cycle, the row address strobe (RAS) is first input to dRAM, and then the CAS is input. The address/data selector always outputs the row address and column number address in this order, and these are manually input to the dRAM chip. For this reason, dRAM
It was difficult to shorten the cycle time of the machine, and in the end, the machine cycle of the computer using this could not be shortened sufficiently.

In the future, dRAM will be used to increase the capacity of computers.

In the case of increasing the speed, an important issue is how to shorten the cycle time in the above sense.

(Problems to be Solved by the Invention) As described above, in the conventional dRAM, shortening the access time does not directly lead to shortening the cycle time, and therefore, it is not possible to shorten the machine cycle of a computer using the dRAM. There was a problem.

An object of the present invention is to solve such problems and provide a dRAM that can shorten the cycle time.

[Structure of the Invention] (Means for Solving Problems) The present invention provides an address multiplex type dRAM in which CAS is used for both read and write cycles.
It is characterized in that RAS is entered first and the column address is fetched first, and then RAS is entered and the row address is fetched.

(Function) The present invention particularly provides data reading between each bit line and an input/output line during a bit line precharge period.

This is effective when a latch type memory cell that allows writing is provided. That is, in the read cycle, RAS is “1”.
When the value changes from "0" to "0", the word line is selected and the data in the memory cell is transferred to the latch type memory cell. At this time,
If you drop CAS to “0” before RAS,
Immediately after selecting a word line, a column selection line can be selected to read data to the outside. Thereafter, by turning off the transfer gate between the bit line and the latch type memory cell, bit line precharging can be performed while RAS remains in the "0" state. As a result, the bit precharge that was conventionally performed during the RAS precharge period is
, AS can be carried out during the active period, thereby making it possible to shorten the cycle time. Also, in the write cycle, if the column address is taken in advance, the timing of bit line precharge during the RAS active period can be accelerated, which leads to a reduction in cycle time.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the main part configuration of a dRAM according to an embodiment. Multiple pairs of bit lines BL are provided on the semiconductor substrate.

BL (BLI, BLI, BL2. BL2,
) and several word lines MW (MWI, MW2
,...) are arranged in an intersecting manner, and d is placed at each intersecting position.
RAM cells MC (MCI, MC2, . . . ) are arranged.

The dRAM cell MC is selectively driven by the word line MW and exchanges data with the bit lines BL. Each bit line pair BL, BL includes one dRAM cell and one dummy cell DCI.

DC2 is provided. Dummy cell DCI.

DC2 is driven by dummy word lines DWI and DW2. The bit lines BL and one end of the BL are connected to the bit line B.
Bit line sense amplifiers 10 (10, -1, 10-2, . . . ) are provided to detect data read out to L and BL. 50' (50-1゜50-2...)
is a circuit (hereinafter referred to as a precharge circuit) that equalizes and precharges the bit lines BL, BL. Bit line B
A first transfer gate 30 is provided at the other ends of L and BL.
The latch type memory cells 20 (20-1, 20-2, . . . ) are connected via (30-1, 30-2, . . . ).

The latch type memory cell 20 is connected to the second transfer gate 4
0 (40-1, 40-2, . . . ) via input/output lines I10. Connected to I10.

FIG. 2 shows a specific configuration example of the dRAM shown in FIG. 1.

dRAM cell MC and dummy cell DC - MO
This is a well-known device consisting of an S transistor and one capacitor. The reference potential terminal of the capacitor is plate 71S@
Vpt.

Dummy cells DCI and DC2 have a precharge power supply VD.
A writing n-channel MOS) transistor Q91Q10 connected to C is provided. Bit line sense amplifier 10 includes n-channel MOS transistor pair Q4. Q5
and p-channel MOS) transistor pair Q6. Q7, and an activation signal φSE+φ is applied to the source of each pair.
SE is now included. The precharge circuit 50 is composed of three n-channel MOS transistors Q] to Q3 whose gates commonly receive an equalize signal EQL1. Ql.

Q2 is for precharging, and its sources are connected to the bit lines BL and BL, and its drains are commonly connected to the precharging power supply VBL.

Equalizing MOS transistor Q3 is the source.

Drains are connected to bit lines BL and BL, respectively.

The latch type memory cell 20 includes a flip-flop consisting of a pair of n-channel MOS transistors Q+81Q19, and a p-channel MOS transistor pair Q+81Q19.
It is constituted by a flip-flop consisting of a channel MOS transistor pair Q21+022. A latch clock φC is connected to the source of each transistor pair.
E, φCE enters. Q20 is an n-channel MOS transistor for equalization. Nodes A, A of such a latch type memory cell 20 are connected to n-channel MOS transistors Q16 . Bit line BL via Ql7.

An n-channel MOS transistor Q23 . Q24
via the input/output line I10. Connected to I10. The first transfer gate 30 is controlled by the clock φT. The second transfer gate 40 is connected to a column selection line C3L selected by a column address.

The read cycle operation of the dRAM configured in this manner will be explained with reference to FIG. FIG. 3 shows signal waveforms when data in a latch type memory cell is transferred to an input/output line using a method of precharging the bit line to (1/2) VDD. Initially, the level of the bit line equalize signal EQL1 is VDD, and the bit line precharge power supply VB is (1/2) VDP, so
The bit lines BL and BL are all precharged to (1/2) Vo·o. Now, the i-th bit line pair BLI,
Focusing on BL1, dRAM cell MC.

It is assumed that VDD (logic "1") is written in the node N1 of the capacitor. It is also assumed that the level of (1/2) VDD is initially set at the node N3 of the capacitor of the dummy cell DC2 by the write power supply VOC.

CA S l) < RA S +: Logic “1” in advance
When (Vr+t) becomes logic "0" (VIL), the column address is first taken into the chip. For example i
If the th column is selected, the column selection line C5
Although Li does not rise from VSS to VDD at this point, the i-th column address is latched into a column selection line decoder (not shown).

Next, RAS changes from logic “1” (VIH) to “0” (V,
When it becomes L), the equalize signal EQLL.

EQL2 drops from VDD to VSS, word line MW
, is selected, and this and the dummy word line D W 2 are simultaneously raised from VSS to (3/2) VDD.

As a result, dRAM cell MCIMC-me cell DC2
The contents of are read out to the bit lines BL and BL, respectively.

At this time, the equalization signal E of the latch type memory cell 2°
QL3 drops from VDD to VSS. Next, the n-channel side activation signal φSE of the bit line sense amplifier 10 becomes (
Subsequently, the p-channel side activation signal φSE falls from (1/2) VDD to VSS.

As a result, the bit line BL on the side from which logic "1" data has been read goes up to VDD, and the bit line BL from which the data of the dummy cell DC2 has been read goes down to VSS.

Next, the clock φT changes from VSS to VDD, and the first transfer gate 30 is turned on. When the latch signals φCE + φCε respectively go from (1/2) VDD to vss, the contents of the bit lines BL and BL are transmitted to the eighth nodes A and A of the latch type memory cell 20. Next, the column address latched in the column selection line decoder causes the column selection line C5Li to rise from VSS to VDD, and nodes A and A are connected to input/output lines I10. Connected to I10. In this case, Ilo keeps VDD and Ilo
falls from VDD to VSS, and the output V out of the data out amount buffer decreases from Hlz to “H” level output V
It becomes OH. At the same time, the clock φT falls from VDD to VSS, and after the latch type memory cell is separated from the bit line, the word line MWI and the dummy word line DW2 (
3/2) The voltage drops from VDD to VDD, and the bit line equalize signal EQLI rises from VSS to VDD, thereby precharging the bit line.

As described above, in the dRAM of this embodiment, by providing a latch type memory cell on the bit line and temporarily storing read data therein, the bit line can be precharged even during the RAS active period.

FIG. 4 shows signal waveforms for explaining the write cycle operation. Even in the write cycle, CAS goes from "1" to "0" before RAS, and the i-th column contention address is latched into the decoder of the column selection line.
Same as read cycle. When the write trigger signal WE changes from "1" to "0", the write system circuit operates, the data-in buffer operates, and the input/output line I10°Ilo is activated.
sense amplifier is activated. For example, if the input data is “
0”, Ilo falls from VDD to VSS and I
lo maintains VDD.

After this, when RAS changes from "1" to "0", equalize signals EQL1 to EQL3 fall from VDD to VSS,
The bit lines BLf, BL1 and the nodes At, AI of the latch type memory cells become floating. Due to the input row address, the level of word line MW1 and dummy word line DW2 rises from VSS to (3/2) VDD, and at the same time, the level of column selection line C5Li is increased due to the column address already latched in the column decoder. is VS
The clock φT also rises from VSS to VDD.
It goes up to DD. As a result, the first. The second transfer gates 30.40 are turned on, and the bit lines BLi, BLI are connected to the human output lines 110.40, respectively. connected to Ilo, while B
Li falls from )1/2) VDD to VSS, and the other BL
I rises from (1/2) VDD to VDD.

Next, the n-channel side sense amplifier activation signal φsE and the memory cell latch signal φCE simultaneously fall from (1/2) VDD to VSS, and the p-channel side sense amplifier activation signal φSE and the memory cell latch signal φCε simultaneously decrease ( 1
/2) The voltage rises from VDD to vDD, and data writing to the selected memory cell and rewriting to the unselected memory cell begin.

That is, the selected dRAM cell MCIMC-domain N1 and the node N2 of the dummy cell DC2 are connected to the bit line BL1, respectively.
．． Since it is connected to BLi, node N, drops from VDD to VSS and a logic “0” is written, and node N3
increases from (1/2) VDD to VDD. After the unselected memory cells are sufficiently rewritten, the word line MWI and the dummy word line DW2 are lowered from (3/2) VDD to VSS. At about the same time, the clock φT also drops from vDD to VSS, and when the latch type memory cell is disconnected from the bit line, the bit line equalize signal E' Q L L goes down to Vss.
The voltage rises to VDD, and bit line precharging begins.

At the same time, the equalize signal EQL2 rises from VSS to VDD, and the initial setting level of (1/2) VDD is written into the dummy cell.

In this way, in the write cycle, the data to be written is latched into the latch type memory cell quickly, so that the timing of subsequent bit line precharging can also be sped up.

As explained above, this embodiment utilizes a configuration in which each bit line is provided with a latch type memory cell, and CAS precedes RA S in both write and read cycles.
The output address is loaded into the dRAM chip before the row address. Therefore, in the read cycle, while outputting the read data to the latch type memory cell,
Bit line precharge can be performed. That is, bit line precharging, which was conventionally performed during the RAS precharge period, can be performed during the RAS active period. In the write cycle, the column selection line is selected at the same time as the word line is selected, and writing is performed quickly, and the bit line is precharged immediately after the write cycle is completed. As a result of the above, the cycle time can be significantly shortened compared to the conventional method.

In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

r Effects of the Invention] As described above, according to the present invention, - read cycle;
By loading the column address before the row address during the write cycle, the cycle time of dRAM can be significantly shortened, and if this system is applied to a computer that uses dRAM as the main memory, it can be used in high-speed machines.・It is possible to realize the cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of dRAM in one embodiment of the present invention, FIG. 2 is a diagram showing its specific circuit configuration, and FIG. 3 is a signal waveform diagram for explaining its read cycle operation. Similarly, FIG. 4 is a signal waveform diagram for explaining the write cycle operation. MC (MCI, MC2,...)...dRAM cell, DCI, DC2...dummy cell, BE, B
L (BLI, BLl, BE2.BE2...)... Bi-nt line, MW (MWL, MW2,...)
...Word line, DWI, DW2-1'Me'7-
F line, I 10゜Ilo...Input/output line, 10...Sense amplifier, 20...Latch type memory cell, 30...
- First transfer gate, 40... second transfer gate, 50... precharge circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) Randomly accessible memory cells are integrated on a semiconductor substrate, with multiple bit lines for exchanging data with each memory cell and multiple word lines that intersect with the bit lines for selecting memory cells. column address to select the bit line and row address to select the word line.
In an address multiplex semiconductor memory device where an address is input from the same pin, in both read and write cycles, the column address is first taken in by a column address strobe, and then by a row address strobe. A semiconductor memory device characterized in that a row address is captured. (2) The semiconductor according to claim 1, wherein each bit line is connected to a latch type memory cell via a transfer gate for reading and writing data during a bit line precharge period. Storage device.