JPS54131831A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS54131831A
JPS54131831A JP3989278A JP3989278A JPS54131831A JP S54131831 A JPS54131831 A JP S54131831A JP 3989278 A JP3989278 A JP 3989278A JP 3989278 A JP3989278 A JP 3989278A JP S54131831 A JPS54131831 A JP S54131831A
Authority
JP
Japan
Prior art keywords
signal
bit
memory unit
unit
shows
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3989278A
Other languages
Japanese (ja)
Inventor
Fumio Yamano
Moichi Hirasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3989278A priority Critical patent/JPS54131831A/en
Publication of JPS54131831A publication Critical patent/JPS54131831A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To form the memory unit of one word and mk-bit by using m-units of the standard basic unit featuring a fixed word length (k-bit) and thus to enhance the economical performance via standardization as well as the degree of freedom in the case of reconstitution.
CONSTITUTION: Basic unit 1a and 1b handle k-bit data signal 5a and 5b (that is, the 2k-bit data signal is used) for the error control memory unit. When the address signal 4 is supplied through common signal line 10, 2k-bit signal 5a and 5b read out are delivered immediately through encoding composite circuit 9 and in the form of correct data signal 5. At the same time, signal 11 shows that the data reading is over from signal 4, 5a, 5b, 5, unit 1a and 1b respectively, and timing signal 12 shows that composite signal 5 is obtained via circuit 9.
COPYRIGHT: (C)1979,JPO&Japio
JP3989278A 1978-04-04 1978-04-04 Memory unit Pending JPS54131831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3989278A JPS54131831A (en) 1978-04-04 1978-04-04 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3989278A JPS54131831A (en) 1978-04-04 1978-04-04 Memory unit

Publications (1)

Publication Number Publication Date
JPS54131831A true JPS54131831A (en) 1979-10-13

Family

ID=12565608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3989278A Pending JPS54131831A (en) 1978-04-04 1978-04-04 Memory unit

Country Status (1)

Country Link
JP (1) JPS54131831A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60258799A (en) * 1985-04-23 1985-12-20 Toshiba Corp Semiconductor memory
JPS6478339A (en) * 1987-09-19 1989-03-23 Hudson Soft Co Ltd Address controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60258799A (en) * 1985-04-23 1985-12-20 Toshiba Corp Semiconductor memory
JPH0226315B2 (en) * 1985-04-23 1990-06-08 Tokyo Shibaura Electric Co
JPS6478339A (en) * 1987-09-19 1989-03-23 Hudson Soft Co Ltd Address controller

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