JPH0226315B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device including a control memory circuit that controls, for example, the number of output bits of a memory main body.

[Technical background of the invention and its problems]

In recent years, for example, microcomputers have been developed in which various units such as 4 bits, 8 bits, and 16 bits are used as basic units for information processing. For this reason, even in semiconductor memory devices used in microcomputers, memory is configured in units of 4 bits, 8 bits, and 16 bits, whereas 16-bit microcomputers use memory configured in units of 8 bits. In some cases, it is necessary to configure two memories in parallel to obtain information in units of 16 bits. That is, in such a case, since it is necessary to always use two memories at a time, there are problems such as an increase in wiring when configuring the memory circuit and slow access to the memory.

That is, conventional semiconductor memory devices have fixed configurations such as the basic unit of information being determined in advance, and therefore cannot be flexibly adapted to general-purpose information processing systems.

[Purpose of the invention]

An object of the present invention is to provide a versatile semiconductor memory device that can be used flexibly, for example, for various information processing devices with different basic units of information processing.

[Summary of the invention]

The present invention is a semiconductor memory device in which a control memory is added to a memory main body. The control memory is, for example, a memory circuit that shares the address input terminal of the memory main body as a specific input terminal and stores control data input from this address input terminal. This control data is data that is predetermined in accordance with the operation control of the memory main body, such as controlling the number of output bits of the memory main body.

With this configuration equipped with control memory,
Operation control according to control data becomes possible, and versatility can be obtained.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a control memory circuit of a semiconductor memory device according to an embodiment;
FIG. 2 is a circuit diagram showing the configuration of the memory main body. In FIG. 1, the control memory circuit includes an inverter consisting of transistors f ₁ and f ₂ , a waveform shaping inverter consisting of transistors f ₃ and f ₄ , and a waveform shaping inverter consisting of transistors f ₅ and f ₆ . . The inverter made up of transistors f ₁ and f ₂ performs an inverting operation when the input signal input from the address input terminal AT is equal to or higher than a predetermined threshold level. Here, the address input terminal AT is a terminal to which an address control signal for controlling the operation of the address buffer 10 is normally input. The address buffer 10 is a buffer memory that stores address data when accessing the memory body shown in FIG. 2.

The floating gate transistor f ₁₁ is
This is a memory element of a control memory circuit, and stores "1" or "0" depending on whether or not electrons are electrically injected into the floating gate. transistor
f ₇₀ , f ₇₁ , f ₈ , f ₉ , and f ₁₀ are transistors for controlling injection of electrons into the floating gate of transistor f ₁₁ . Also, transistor
f ₁₂ and f ₁₃ are transistors for controlling the output of transistor f ₁₁ . Here, the transistors f ₁ , f ₃ , f ₅ , f ₇₀ , f ₇₁ , f ₁₂ , f ₁₃ are, for example, depletion type N-channel MOS transistors, and the transistors f ₂ , f ₄ , f ₆ , f ₈ , f ₉ and f ₁₀ are
For example, it is an enhancement type N-channel MOS transistor.

Next, the memory main body is constructed by using a plurality of memory units, for example, four memory units, as shown in FIG. This example allows information to be rewritten.
The case is shown when applied to ROM, that is, EPROM (erasable programmable read-only memory). One memory unit constituting the semiconductor memory includes first to fourth memory blocks 11 ₁ to 11 ₄
Equipped with. Although some of them are omitted in the figure, these memory blocks 11 ₁ to 11 ₄ are connected to common row lines C ₁ to _{C n}
have. On the other hand, each memory block 11 ₁ to 1
1 ₄ are the column lines L ₁₁ ~L _o1 , L ₁₂ ~L _o2 , L ₁₃ ~
It has L _o3 , L ₁₄ to L _o4 . Memory cells 12 are arranged in a matrix at the intersections of each row line and each column line. Each memory cell 12 is composed of a floating gate type MOS transistor 13 having a gate connected to a row line, a drain connected to a column line, and a source connected to ground. When electrons are injected into the floating gate of this floating gate type MOS transistor 13, the threshold voltage increases, and even if a voltage of the normal "1" level is applied to the gate, it will not turn on. , it is in the on state when no electrons are injected. In other words, it depends on whether or not to electrically inject electrons into the floating gate.
"1" or "0" will be stored.

Column lines and row lines for specifying such memory cells 12 are specified by column and row decoders 1.
4, 15. Column address data is supplied to the column decoder 14 from a CPU or the like (not shown), and selectively generates any one of column designation signals R ₁ to _Ro designating a column line. For example, the column designation signal _R1 is commonly supplied to the gates of four MOS transistors _T11 to _T14 . These transistors T ₁₁ to _{T 14} correspond to memory blocks 11 ₁ to 11 ₄ , respectively.
The sources are connected to the first column lines L ₁₁ to L ₁₄ . The above signal R ₁ causes the transistor T ₁₁ to
The gate of T ₁₄ is controlled and the transistors T ₁₁ to _{T 14}
are configured to be designated at the same time by, for example, being conductive at the same time. The signal R ₂ is supplied to the gates of MOS transistors T ₂₁ to T ₂₄ ,
Specify column lines L ₂₁ to L ₂₄ . Similarly, the signal R _o
The configuration is such that column lines L _o1 to _{L o4} are specified. On the other hand, the row decoder 15 is supplied with row address data and generates a signal specifying one of the row lines C ₁ to C _n .

For example, a signal R ₁ is generated and four column lines L ₁₁
~L ₁₄ is specified and at the same time row line C ₁ is specified, then
Memory cell 1 provided corresponding to each intersection
2 ₁ to 12 ₄ are specified. That is,
In each memory block 11 ₁ to 11 ₄ , one memory cell 12 is designated in this manner.

That is, from each memory block 11 ₁ to 11 ₄ , MOS transistors T ₁₁ to _{T o1} and T ₁₂ to
The signals of the column specified for each memory block are extracted via T _o2 , T ₁₃ - _{T o3} , T ₁₄ - T _o4 , and the signals of the column specified for each memory block 11 ₁ - 11 ₄ are extracted from points a - T o 4 respectively. d respectively supply signals from the column lines. The signals at each of points a to d are detected via MOS transistors 16 ₁ to 16 ₄ , and the respective output signals from transistors 16 ₁ and 16 ₂ and 16 ₃ and 16 ₄ are integrated, and then 17 ₁ and 17 ₂ respectively. The output signals from the transistors 17 ₁ and 17 ₂ are combined and supplied to the first output section 18 ₁ . Furthermore, the output signals from the transistors 16 ₃ and 16 ₄ are combined and supplied to the transistor 19 . The output signal from this transistor 19 is transmitted to the second output section 1
8 Supply to ₂ . Furthermore, the signals at points b and d are
These are supplied to MOS transistors 20 ₁ and 20 ₂ , respectively. The output signals from the transistors 20 ₁ and 20 ₂ are then supplied to third and fourth output sections 18 ₃ and 18 ₄ , respectively.

The gates of the transistors 16 ₁ and 16 ₃ are connected to a signal corresponding to 1 bit of address information.
_A1 is supplied to control gate opening/closing. In addition, the transistors 16 ₂ and 16 ₄ receive a signal that is an inversion of the signal A ₁ .
Gate opening/closing is controlled by _A1 . Furthermore, the transistors 17 ₁ and 17 ₂ are each gate-controlled by a signal A ₀ corresponding to 1-bit address information and its inverted signal ₀ . The transistor 19 also receives a control signal 1 supplied from the outside.
3 ₀ , gate-controlled, transistors 20 ₁ , 2
0 ₂ is controlled by control signal C ₀ .

The first to fourth output sections 18 ₁ to 18 ₄ each include a sense up 21 and an output circuit 22, and each have a first to fourth output terminal 2.
Information is output via ₃₁ to ₂₃₄ .

That is, in one memory unit of the semiconductor memory device configured as described above, for example, the control signals B ₀ and C ₀ for selecting the number of bits are both "0".
If you set it to the level state, transistor 1
9, 20 ₁ and 20 ₂ are in a cut-off state, and information transmission to the output units 18 ₂ to 18 ₄ is prohibited.
In this state, the control signals A ₀ and A ₁ serve as address information for selecting one of the memory blocks 11 ₁ to 11 ₄ , so the logic level state of the address signals A ₀ and A ₁ selects the four memory blocks. One of 11 ₁ to 11 ₄ is selected. for example
When A ₁ and A ₀ are both “1”, transistor 16
The gates ₁ , 17 ₁ are opened and the information from memory block 11 ₁ at point a is led to output 18 ₁ . Therefore, if there are four memory units shown in this figure, four bits of output information can be obtained.

Furthermore, if the signal B ₀ is set to the "1" level, the signal C ₀ is set to the "0" level, and the signal A ₀ is set to the "1" level, the transistors 17 ₂ , 20 ₁ , 20
₂ enters the cut-off state, and depending on the input of address data and the state of the signal _A1 , the stored information of one of the first and second memory blocks 11 ₁ and 11 ₂ is selectively output from the first output terminal 23 _1. Become so. At the same time, the information stored in one of the third and fourth memory blocks 11 ₃ and 11 ₄ is selectively output from the second output terminal 23 ₂ . In other words, 2-bit parallel information is now output,
8-bit information is output in four memory units.

Furthermore, if the signals B ₀ and C ₀ are both at the "1" level and the signals A ₀ and A ₁ are set at the "1" level, the transistors 16 ₂ , 16 ₄ , 17 ₂
is in a cut-off state, and the stored information of the memory cells in the first to fourth memory blocks 11 ₁ to 11 ₄ is transferred to the first to fourth output terminals 23 ₁ to 23 ₄ , respectively.
will be output from. In other words, 16 bits of information can be obtained in four memory units.

FIG. 3 shows one of the output circuits 22 ₁ to 22 ₄ ,
For example, the output circuit 22 ₃ will be taken and a specific example thereof will be shown. As is clear from the above description, the output section 18
₃ , when the signal C ₀ is "1", the transistor 20 ₁
is turned on, and output bit information from memory block ₁₁₂ is transmitted. And signal C ₀
If is "0", the transistor 20 ₁ is turned off, and at this time, the output circuit 22 ₃ does not need to operate. Therefore, signal C ₀ is "0"
In this case, it is effective to cut off the current flowing through the output circuit 22 ₃ to reduce unnecessary power.

This output circuit 22 ₃ includes an inverter circuit I ₁ to which a signal from the sense amplifier 21 ₃ is supplied. This circuit _I1 is configured to invert the signal from the sense amplifier and output the signal _X1 when the signal _C0 is "1", and this signal _X1 is sent to the next stage inverter. Further inversion occurs in circuit I ₂ . This circuit I ₂ outputs the signal X ₂ when the signal C ₀ is at the “1” level.
I am trying to output . This signal X ₂ is supplied to the gate of output transistor 30.
A transistor 31 is connected in series to this transistor 30, and the potential at the connection point is outputted from output terminals 22 ₃ to 22 ₃ . Further, the signal X ₂ is supplied to an inverter circuit I ₃ similar to the above. This circuit _I3 is designed to perform an inverting operation when the signal _C0 is "1", and the output signal from this circuit _I3 is supplied to the drain of the transistor 32 whose source is grounded. The gate of this transistor 32 has a signal
A signal ₀ which is an inversion of C ₀ is supplied, and a potential level signal X ₃ at the drain is supplied to the gate of the transistor 31.

That is, in the output circuit configured in this way, when the signal C0 is " ₁ " and the data from the sense amplifier is "0", the signal _X2 is "0".
Therefore, the transistor 30 is turned off. Also, in circuit I ₃ the signal X ₂ is inverted and the signal X ₃
becomes "1" and the transistor 32 is in the off state, so the transistor 31 is in the on state.
Therefore, "0" is output from the output terminal ₂₃₃ . Also, when the signal C ₀ is "1" and the data from the sense amplifier is "1", the signal
X ₁ , X ₂ , and X ₃ are in the level state of "0", "1", and "0", respectively, the transistor 30 is on, the transistor 31 is off, and the output terminal 23 is turned on.
"1" is output to ₃ . That is, when the signal _C0 is "1", the output circuit is in an operating state.

Next, when the signal _C0 is "0", the inverter circuits _I1 to _I3 are in a non-operating state, and at this time, the signal _X1 is "1" regardless of the data from the sense amplifier ₂₁₃ , so the signal X ₂ is "0", signal X ₃
Also, the transistor 32 is in the on state, and the value is "0".
It is becoming. Therefore, the transistor 30,
31 are both in an off state, and the output circuit 22 ₃ is in an inactive state.

In the above explanation, the output circuit 22 ₃ in the output section 18 ₃ was explained, but the same applies to the output section 18 _4. In the output section 18 ₂ , the signals C ₀ and ₀ in FIG. 2 are converted into the signals B ₀ and If you change it to ₀ ,
Can be used in similar circuits.

Furthermore, if such an output circuit is used, the transistors 19, 20 ₁ and 20 ₂ shown in FIG. 1 can be omitted.

The operation of this embodiment will be described in a semiconductor memory device comprising a control memory circuit and a memory main body configured as described above. First, in Figure 1,
The inverter made up of transistors f ₁ and f ₂ is designed so that it does not perform an inverting operation unless a voltage of, for example, 10 V or more is applied to the input terminal AT. In other words, when the input terminal AT is 10V or less, the input is "0".
, the node N ₁ remains "1".
This is to avoid responding to the input terminal AT, which fluctuates between 0V and 5V when it is used as an address input, that is, in normal use. The address buffer 10 is designed to respond to this fluctuation between 0V and 5V.
Note that the transistors f ₃ , f ₄ and f ₅ , f ₆ form an inverter for waveform shaping.

The floating gate transistor f ₁₁ is
It is a non-volatile memory element, and when electrons are not injected into the floating gate, it is turned on when a voltage of 5V is applied to the gate. Furthermore, when electrons are injected, the device remains off even if a voltage of 5V is applied to the gate. The gate potential of this element is determined by node _N4 between transistors _f70 and _f71 . Normally, when the address signal is input to the terminal AT, the nodes N ₁ , N ₂ , and N ₃ are "1", "0", and "1", respectively, so the nodes of transistors f ₅ and f _{71 N5} is at the "0" level. However, even if the node N ₅ is at the "0" level, by appropriately setting the capabilities of the transistors f ₇₀ and f ₇₁ , the node N ₄ can be set to the power supply voltage.
It can be maintained at the "1" level of about Vc, for example about 5V. At this time, the node N ₅ of the transistor f ₁₀ is at the "0" level and is off, and the node N ₃ is at the "1" level, so the transistor f ₁₂ is on. It is becoming. Therefore, the transistor f ₁₁ ,
An inverter is formed with f ₁₃ . Since no electrons are injected into the floating gate of this transistor f ₁₁ and the gate potential is at the "1" level, this transistor f ₁₁ is turned on and the node N ₇ becomes "0". . That is,
The control signal B ₀ or C ₀ is at the "0" level.

Also, if electrons are injected into the floating gate of transistor _f11 , this gate "1"
Even if a level signal is supplied, the transistor f ₁₁
remains off. That is, node N ₇ is
The signal becomes "1" level, and the signal B ₀ or C ₀ becomes "1" level.

In this way, the logic level states of the control signals B ₀ and C ₀ can be determined depending on whether or not electrons are injected into the transistor f ₁₁ .

Next, the case where electrons are injected into this floating gate transistor _f11 will be explained.
In this case, for example, at a high potential with respect to the input terminal AT,
Apply a voltage of 25V. At this time, transistor f ₂
is turned on, node N ₁ becomes "0", node N ₂ becomes "1", and node N ₃ becomes "0". and nodes N ₄ , N ₅
is charged via transistor _f9 . The potentials at nodes N ₄ and N ₅ at this time are 25V minus the threshold voltage of transistor f ₉ . Therefore, the transistor _f10 is turned on, a sufficient voltage is applied to the drain and gate of the floating gate transistor _f11 , and electrons are injected into the floating gate. In this way, the terminal AT for inputting a 1-bit address can also be used as a terminal for injecting electrons into the floating gate of the transistor _f11 .

In the embodiment of the control signal generation circuit described above, a floating gate transistor is used as the memory element, but it goes without saying that an MNOS (metal nitride oxide semiconductor) may also be used.

In this way, by storing control data in advance in the nonvolatile memory element (transistor f ₁₁ ) of the control memory circuit using the address input terminal AT, the number of output bits of the memory main body shown in FIG. 2 can be adjusted. can be determined. Therefore, in information processing apparatuses having different bit configurations, the number of output bits of the memory main body can be set according to the bit configuration. Therefore, it is possible to flexibly apply the present invention to information processing devices with various bit configurations.

Further, in the embodiment described above, the operation of the control memory circuit has been described for controlling the number of output bits of the memory main body, but the present invention is not limited to this. That is, if control data corresponding to the operation control of the memory body is stored in advance in the control memory circuit, it can be applied to other operation controls of the memory body. For example, this is a case where control is applied to make information at a specific address in the memory body inaccessible.

Although the case has been described in which the address input terminal AT is shared as the input terminal of the control memory circuit, the present invention is not limited to this, and other input terminals (for example, chip select terminals) or specially installed input terminals may be used.

〔Effect of the invention〕

As described in detail above, according to the present invention, by storing control data in accordance with the operation control of the memory body in advance, it is possible to provide versatility in the operation of the memory body. Therefore, it is possible to obtain effects such as being able to be flexibly applied as a memory device to various information processing devices having different bit configurations for information processing, for example.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a control memory circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the memory main body of the same embodiment, and FIG. 3 is the output circuit of FIG. 2. FIG. 2 is a circuit diagram showing a specific configuration. 11 ₁ - 11 ₄ ... memory block, 12 ... memory cell, 13 ... floating gate type MOS transistor, 14 ... column decoder, 15 ... row decoder, 16 ₁ - 16 ₄ , 17 ₁ - 17 ₂ , 19, 20 ₁ ,
20 ₂ ... MOS transistor, 18 ₁ to 18 ₄ ... output section, 21 ... sense amplifier, 22 ... output circuit, 23
₁ to 23 ₄ ...first to fourth output terminals, _f11 ...floating gate transistor.

Claims (1)

[Scope of Claims] 1. A memory main body having each of a matrix-shaped memory cell, an address decoder, an address input terminal, and an input/output circuit, and the address input terminal is shared and is outside the input potential level range of a normal address input signal. a control memory circuit that stores data in response to an input from the address input terminal set to a level of 1, and performs predetermined control on the memory main body in accordance with the data.