KR100250754B1 - Decoder circuit in a flash memory - Google Patents

Abstract

PURPOSE: A decoding circuit of a flash memory is provided to use a global row decoder, increase the number of local row decoders receiving the output of the global row decoder when dividing sectors in column direction as well as to minimize the loading of row address path to reduce the chip size. CONSTITUTION: The decoding circuit of the flash memory includes a global row decoder and a local row decoder. The global row decoder includes the first through forth transistors(T1,T2,T3,T4). The first and second transistors are operated with response to a XnCOM signal. The global row decoder receives the voltage transmitted by the operation of the first and second transistors. The third and forth transistors are operated with response to the translated voltage. The global row decoder outputs the voltage applied on Vppx or Veex to the global word line. The local row decoder includes fifth through seventh transistors. The local row decoder receives the global word line. The fifth through seventh transistors are operated with response to the first and second column sector address. The local row decoder outputs the voltage of the global word line to the word line.

Description

Decoder Circuit in Flash Memory

The present invention provides a flash memory device that can use a global row decoder in a flash memory device capable of writing sector by sector, and increase the number of sectors in the local row decoder that inputs the output of the global row decoder when the sector is divided in the column direction. Relates to a row decoder circuit.

In general, flash memory devices have electrical programming and erasing functions. In a sector-programmable flash memory device, write cycles are typically guaranteed at least 100,000 times. At this time, the number of stresses applied to the gate of the unit cell is the number of unit cells connected to one word line, and the number of stresses received at the drain of the unit cell is the number of unit cells connected to one bit line. 1 is a circuit diagram of a row decoder conventionally used.

First, in read mode, SnVppx is switched to the Vdd voltage level, and SnVeex and XRST are switched to the ground voltage level. At this time, the P-MOS transistor hp1 is turned on so that all node points A have the Vdd voltage level, and the Vdd voltage level applied to the node point A turns on the N-MOS transistor thn to turn on the ground voltage level at the word line SnWL. Let's have

On the other hand, only one XnCOM selected by the address has the ground voltage level, and at this time, only one XAPRED becomes the Vdd voltage level, so the NMOS transistor hn of the row decoder to be selected is turned on, and the node point A of the selected row decoder is turned on. Has a ground voltage level. Therefore, the ground voltage level applied to the node point A turns on the P-MOS transistor hp3 to have the Vdd voltage level on the word line SnWL.

Next, in program mode, the SnVppx of the selected sector switches to the Vpp voltage level, all SnVeex switches to the ground voltage level, and the XRST maintains the ground voltage level until SnVppx reaches the Vpp voltage level. At the voltage level, the XRST of the selected sector is switched to the Vpp voltage level. The SnVppx of the unselected sector maintains the Vdd voltage level, and the XRST of the unselected sector maintains the ground voltage level, so that the word line SnWL of the unselected sector has the ground voltage level.

Meanwhile, one XnCOM selected by the address has a ground voltage level. At this time, since only one XAPRED becomes the Vdd voltage level, the NMOS transistor hn of the row decoder to be selected is turned on, and the node point A of the selected row decoder is turned on. Has a ground voltage level. Therefore, the ground voltage level applied to the node point A turns on the P-MOS transistor hp3 to have the Vpp voltage level on the word line SnWL.

Finally, in the erase mode, the SnVppx of the selected sector is switched to the ground voltage level, SnVeex is switched to the -Vpp voltage level and XRST is switched to the ground voltage level. Then, SnVppx of the unselected sector is switched to the Vdd voltage level, SnVeex is switched to the ground voltage level and XRST is switched to the ground voltage level.

As a result, the node point A of the unselected sector becomes the Vdd voltage level, and thus the word line SnWL has a ground voltage level.

Meanwhile, in the row decoder of the selected sector, the NMOS transistor thn is turned on so that all word lines SnWL have a voltage level of -Vpp.

In the row decoder as described above, since the number of row decoders increases when the sectors are divided in the column direction, the number of XnCOMs of the row decoder increases so that the predecoder output load and the address buffer output load increase proportionally. Access Time) is delayed, and the size of the chip also increases.

Accordingly, the present invention uses a global row decoder in a flash memory device capable of writing sector-by-sector, and increases the number of sectors in the row address signal by increasing the number of sectors in the local row decoder that inputs the output of the global row decoder when the sector is divided in the column direction. It is an object of the present invention to provide a low decoder circuit in a flash memory device capable of increasing access time while reducing chip size by minimizing loading caused by a low address path.

The present invention for achieving the above object consists of a global row decoder for selecting a plurality of word lines, and a local row decoder for selecting each of the word lines selected by the global row decoder.

1 is a circuit diagram showing a general row decoder.

2 is a circuit diagram illustrating a global row decoder according to the present invention.

3 is a circuit diagram illustrating a local row decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

T1: first transistor T2: second transistor

T3: third transistor T4: fourth transistor

T5: fifth transistor T6: sixth transistor

T7: 7th transistor hp1 to hp3: P-MOS transistor

hn and thn: N-MOS transistor

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a global row decoder according to the present invention, in which XnCOM of the global row decoder selected by the row address signal has a Vdd voltage level.

The operation of each mode is explained first. In the read mode, Vppx is switched to the Vdd voltage level and Veex is switched to the ground voltage level. At this time, since XnCOM of the selected global row decoder is at the Vdd voltage level, the second transistor T2 is turned off, and the first transistor T1 is turned on so that the node point B becomes the ground voltage level, thereby turning on the fourth transistor T4. By turning on, the global word line GWL has a Vdd voltage level.

Meanwhile, since XnCOM of the unselected global row decoder is the ground voltage level, the second transistor T2 is turned on so that the node point B becomes the Vdd voltage level so that the third transistor T3 is turned on, thereby unselecting the global word line GWL. Has a ground voltage level.

Next, Vppx of the global low decoder is switched to the Vpp voltage level by the low sector address selected in the program mode, and Vppx of the unselected global row decoder is switched to the Vdd voltage level. At this time, the selected global row decoder turns on the first transistor T1 so that the node point B becomes the ground voltage level, and accordingly, the selected global word line GWL turns on the Vpp voltage level by turning on the fourth transistor T4. Will have

Meanwhile, since XnCOM of the unselected global row decoder is the ground voltage level, the second transistor T2 is turned on so that the node point B is at the Vpp voltage level, and the third transistor T3 is turned on to unselected global word line GWL. ) Has a ground voltage level.

Finally, in the erase mode, Vppx of the global row decoder selected by the low sector address is switched to the ground voltage level, and Vppx of the unselected global row decoder is switched to the Vdd voltage level. The Veex of the selected global row decoder is switched to the -Vpp voltage level, and the Vppx of the unselected global row decoder is switched to the ground voltage level. In addition, since the XnCOM of the global row decoder becomes the Vdd voltage level by the erase command only in the erase mode, since the Veex of the low sector selected by the low sector address is -Vpp voltage level, the first and third of the global row decoder of the selected low sector are selected. The transistors T1 and T3 are turned on so that the global word line GWL has a Vpp voltage level.

On the other hand, the Veex of the unselected global row decoder becomes the ground voltage level, and Vppx becomes the Vdd voltage level so that the second and third transistors T2 and T3 are turned on so that the global word line GWL becomes the ground voltage level.

3 illustrates the input of the global word line GWL of FIG. 2 and transmits the voltage level of the global word line GWL only to the column sector selected by the combination of the first and second column sector addresses SnCOM and SnCOMB. Is a circuit diagram of a local row decoder configured to have a ground voltage level in a word line SnWL of an unselected column sector.

Vppx and Veex of the local row decoder are switched to each mode as Vppx and Veex of the global row decoder. The fifth transistor T5 and the sixth transistor T5 in the local row decoder of the column sector selected by the combination of the first and second column sector addresses SnCOM and SnCOMB, which are gate inputs of the local row decoder, and Vppx and Veex. ) Is turned on, but in the local row decoder of the unselected column sector, the fifth transistor T5 and the sixth transistor T6 are turned off, and the seventh transistor T7 is turned on so that the word line SnWL is at ground voltage level. Will have

In operation in each mode, first, in the read mode, Vppx becomes the Vdd voltage level, Veex becomes the ground voltage level, and the selected global word line GWL is inputted with the Vdd voltage level, and the unselected global word line GWL is selected. The ground voltage level is input. At this time, since the first column sector address SnCOM is switched to the ground voltage level and the second column sector address SnCOMB is switched to the Vdd voltage level, the selected column sectors are the fifth transistor T5 and the sixth transistor T6. Turn on and turn off the seventh transistor T7 so that the Vdd voltage level of the global word line GWL is transferred to the word line SnWL.

Meanwhile, since the first column sector address SnCOM is switched to the Vdd voltage level and the second column sector address SnCOMB is switched to the ground voltage level, the unselected column sectors are the fifth transistor T5 and the sixth transistor T6. ) And the seventh transistor T7 is turned on so that all word lines SnWL have a ground voltage level.

Next, the global word line GWL selected in the program mode becomes the Vpp voltage level, and Vppx becomes the Vpp voltage level. The unselected global word line GWL becomes the ground voltage level, Vppx becomes the Vdd voltage level, and Veex becomes the ground voltage level. Since the first column sector address SnCOM is at the Vdd voltage level and the second column sector address SnCOMB is at the ground voltage level, the unselected low sectors are the fifth transistor T5 and the sixth transistor T6 in the local row decoder. Turn off and turn on the seventh transistor T7 so that the word line SnWL has a ground voltage level.

On the other hand, when the first column sector address SnCOM is at the ground voltage level and the second column sector address SnCOMB is at the Vdd voltage level, the fifth transistor T5 and the sixth transistor T6 are turned on in the local row decoder. The seventh transistor T7 is turned off to transfer the voltage level of the global word line GWL to the word line SnWL.

As a result, only one word line SnWL has a Vpp voltage level, and all other word lines SnWL have a ground voltage level.

Finally, in the erase mode, the global word line GWL selected by the low sector address becomes the -Vpp voltage level, Vppx becomes the ground voltage level, and Veex becomes the -Vpp voltage level. The unselected global word line GWL becomes the Vdd voltage level, Vppx becomes the Vdd voltage level, and Veex becomes the ground voltage level. The first column sector address SnCOM of the unselected low sector is at the Vdd voltage level, and the second column sector address SnCOMB is at the ground voltage level, thereby turning off the fifth transistor T5 and the sixth transistor T6. The seventh transistor T7 is turned on to have a ground voltage level on the word lines SnWL of all local row decoders.

Among the selected row sectors, the first column sector address SnCOM of the selected column sector becomes the -Vpp voltage level, and the second column sector address SnCOMB becomes the ground voltage level. Among the unselected column sectors, the first column sector address SnCOM is at the ground voltage level, and the second column sector address SnCOMB is at the -Vpp voltage level.

As a result, even when the global word line GWL becomes -Vpp due to the low sector address, only the local row decoders of the selected column sector turn on the fifth transistor T5 and the sixth transistor T6, and the seventh transistor ( By turning off T7, the voltage level of the global word line GWL is transferred to the word line SnWL as it is, and the fifth transistor T5 and the sixth transistor T6 of the local row decoder of the unselected column sector are turned on. The seventh transistor T7 is turned off to have the ground voltage level at the word line SnWL of the local row decoder of the unselected column sectors.

As described above, according to the present invention, a sector-by-sector write is possible. In a flash memory device, a global row decoder is used, and when a sector is divided in a column direction, the local row decoder which inputs the output of the global low decoder is increased by the number of sectors. By minimizing the load caused by the row address signal, the access time can be reduced, and the circuit of the local row decoder used is simple, so that the chip size can be reduced.

Claims (7)

A decoder circuit in a flash memory, comprising: a third and a fourth transistor configured to be input as a voltage transmitted by an operation of first and second transistors operating in accordance with a signal of XnCOM, and operating according to the voltage. And a global row decoder for outputting a voltage applied to Vppx or Veex by the operation of the fourth transistor to a global word line, and a fifth operating with the global word line as an input and operating according to first and second column sector addresses. And a local low decoder for outputting a voltage of a global word line to the word line by an operation of the fifth to seventh transistors. The XnCOM signal of claim 1, wherein the XnCOM signal is selected by the low sector address in the read and program modes, wherein the selected XnCOM signal turns off the second and third transistors and turns on the first transistor to cause the global word line to have a Vppx voltage level. And the unselected XnCOM signal turns off the first and fourth transistors and turns on the second transistor to bring the ground voltage level. 2. The XnCOM signal of claim 1, wherein the XnCOM signal is set to the ground voltage level by an erase command in an erase mode to turn off the first and fourth transistors, and turn on the second and third transistors to turn off all global word lines. A decoder circuit in a flash memory characterized by having a voltage level. The decoder circuit of claim 1, wherein the first and third transistors are N-MOS transistors, and the second and fourth transistors are P-MOS transistors. 2. The method of claim 1, wherein the selected global word line and column sector turn on the fifth and sixth transistors by the first and second column sector addresses in the read and program modes, and turn off the seventh transistor to the word line. The unselected global word lines and column sectors turn off the fifth and sixth transistors by the first and second column sector addresses, and turn on the seventh transistors to bring the word lines to ground voltage levels. And a decoder circuit in flash memory. The method of claim 1, wherein the global word line has a voltage level of -Vpp in an erase mode and the selected global word line turns on the fifth and sixth transistors by the first and second column sector addresses, and the seventh transistor. Turn off to be delivered to the word line, and the unselected global word line turns off the fifth and sixth transistors by the first and second column sector addresses, and turns on the seventh transistor so that the word line is grounded. A decoder circuit in a flash memory characterized by being at a level. The decoder circuit of claim 1, wherein the fifth transistor is a PMOS transistor, and the sixth and seventh transistors are NMOS transistors.