JPH1145591A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the delay in access speed at the time of data reading. SOLUTION: In a flash memory, a signal interrupting circuit 105 is connected between the pre-decoder 101 and the main decoder group 103, and a signal interrupting circuit 107 is connected between the connecting node between the main decoder group 103 and the signal interrupting circuit 105 and the voltage converting circuit 109. Since at the time of data reading, control signals CUT1, CUT2 from a control circuit 119 turn the signal interrupting circuit 105 on and the signal interrupting circuit 107 off, the pre-decoder 101 is separated from the voltage converting circuit 109 and the output PDOUT of the pre- decoder 101 is inputted directly into the main decoder group 103 not through the voltage converting circuit 109.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device such as a flash memory which uses a high voltage when writing and erasing data.

[0002]

2. Description of the Related Art As an example of a nonvolatile semiconductor memory device, a flash memory is generally used. Generally, a flash memory uses a high positive or negative voltage during data writing and erasing. A memory cell to which data writing or erasing is performed is selected based on a decode signal obtained by decoding an externally input address signal, and the voltage used at the time of data writing or reading is determined by the decoding signal. Is generated by voltage conversion.
Therefore, a flash memory usually includes a voltage conversion circuit in a decoder for decoding an address signal.

FIG. 7 is a circuit diagram showing a decoder and its peripheral circuit 600 in a conventional flash memory. Referring to FIG. 7, a decoder and its peripheral circuit 60 are shown.
0 is a predecoder 10 to which a row address signal is input.
1, the main decoder group 103, and the signal cutoff circuit 601
, A voltage conversion circuit 609, a memory cell column group 111,
A control circuit 619 and a decoder 121 are provided. The main decoder group 103 includes a plurality of main decoders 115x.
(X = 1, 2, 3,..., M). The memory cell column group 111 includes a plurality of memory cell columns 117x (x =
1, 2, 3,..., M). Decoder section 12
1 selectively outputs data from the bit line BL.

The main decoder 115x (x = 1, 2, 2)
,..., M) correspond to the corresponding word lines WLx (x = 1, 2, 2, 3).
,..., M) and a word line WLx (x = 1,
, M) correspond to the corresponding memory cell column 115x (x
= 1, 2, 3,..., M). A signal cutoff circuit 6 between the predecoder 101 and the voltage conversion circuit 609
01 is connected. The signal cutoff circuit 106 is turned on / off in response to the H / L level of the control signal CUT from the control circuit 619. When the signal cutoff circuit 106 is turned on,
The output PDOUT of the predecoder 101 is the signal cutoff circuit 1
The voltage is input to a voltage conversion circuit 609 via a line 06 and is converted into a voltage. The positive or negative high voltage obtained by the voltage conversion is input to the main decoder group 103. Voltage conversion circuit 60
9 indicates that the signal cutoff circuit 601 is turned off and the predecoder 10
It has a latch for holding the output PDOUT of the predecoder 101 received immediately before even if it is electrically disconnected from 1.

FIG. 8 shows the signal cutoff circuit 601 shown in FIG.
FIG. 4 is a circuit diagram showing a voltage conversion circuit and a voltage conversion circuit; Referring to FIG. 8, signal cutoff circuit 601 includes an NMOS transistor. The voltage conversion circuit 609 has a latch circuit including two inverters in its configuration.

Next, the operation of the decoder and its peripheral circuit 600 will be described. In decoder and its peripheral circuit 600, predecoder 101 is always driven by a normal power supply voltage. When a high voltage is required for data writing or erasing, the pre-decoder 10
One output PDOUT is latched. When the output PDOUT is latched, the signal cutoff circuit 601 is turned off in response to the L-level control signal CUT from the control circuit 619, and the predecoder 101 and the voltage conversion circuit 609 are electrically disconnected. In the voltage conversion circuit 609, the power supply voltage VP
By raising or lowering WLG and VNWL, the latched output PDOUT of predecoder 101 is output.
Is voltage converted to generate a positive or negative high voltage. Main decoder 115x is also driven by boosted or stepped-down power supply voltages VPWLG and VNWL, further decodes the positive or negative high voltage, and applies its output to a control gate of memory cell column 115x via word line WLx.

[0007]

However, it is not necessary to apply the above-mentioned positive or negative high voltage at the time of data reading, and the power supply voltage VPWLG of the voltage conversion circuit 609 is not required.
And VNWL are set to the normal power supply voltage and do not perform voltage conversion. Therefore, the voltage conversion circuit 609 is not used. Therefore, in the conventional case, it is merely redundant that the output PDOUT of the predecoder is input to the main decoder 115x via the voltage conversion circuit 609 at the time of data reading, and the access speed is reduced due to the propagation delay at this time. There was a problem. If the propagation delay is to be eliminated, it is necessary to increase the size of the voltage conversion circuit. In this case, there is a problem that the area occupied by the layout increases.

Further, at the time of data writing or erasing, the high voltage obtained by voltage conversion circuit 609 is applied to predecoder 101.
, It is necessary to cut off the voltage conversion circuit 609 and the predecoder 101 by the signal cutoff circuit 601. However, since the signal cutoff circuit 601 is provided in front of the main decoder group 103, when the signal cutoff circuit 601 is turned off at the time of data writing or erasing, the main decoder group 103 is simultaneously turned on.
01, and as a result, there is a problem in that during the writing or erasing operation, the memory cell column 117x on which writing or erasing is not performed cannot be accessed at all.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a nonvolatile semiconductor memory device capable of eliminating a delay in access speed at the time of data reading without increasing a layout occupation area. The purpose is to provide. It is another object of the present invention to provide a nonvolatile semiconductor memory device that can access a memory cell column in which writing or erasing is not performed during a data writing or erasing operation.

[0010]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a first selection line group including a plurality of selection lines; and a plurality of memory cell columns each connected to a different selection line. A first memory cell column group consisting of: a first decoding unit that decodes an address signal and outputs a first signal for selecting a selection line of the first selection line group; Voltage conversion / latch means for outputting and latching a second signal after voltage conversion, and connected to a plurality of selection lines, for decoding the first or second signal and outputting a third signal A second decoding unit; a first decoding unit connected between the first decoding unit and the second decoding unit;
Switching means, a second switching means connected between a connection node between the first switching means and the second decoding means and the voltage conversion / latch means, and a first memory cell column group. At the time of data reading, the first switching means is turned on, and the second switching means is turned off. At the time of data writing and data erasing, the first and second switching means are turned on, and a predetermined time has elapsed. And control means for turning off the first switching means.

A nonvolatile semiconductor memory device according to a second aspect of the present invention is the nonvolatile semiconductor memory device according to the first aspect, wherein the first and second selection line groups each including a plurality of selection lines and a plurality of memory cell columns are provided. A second memory cell group different from the first, a first switching means, and a third switching connected between a connection node between the first memory cell string group and the second switching means. Means, the second group of memory cells is connected to a connection node between the first switching means and the third switching means, and the second control means comprises first and second memory cells. At the time of data reading, data writing and data erasing in the memory cell column group, the third switching means is turned on, and at the time of data writing and reading only in the first memory cell column group, first, second and 3 to turn on the switching means, and turns off the third switching means after a predetermined time has elapsed.

According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the voltage conversion / latch means converts the second signal to a positive or negative signal having an absolute value larger than the internal power supply voltage. Convert to a negative voltage.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

(1) First Embodiment FIG. 1 is a circuit diagram showing a decoder and its peripheral circuit 100 in a flash memory according to a first embodiment of the present invention. Referring to FIG. 1, a decoder and its peripheral circuit 100 include a predecoder 101 to which a row address signal is input, a main decoder group 103, signal cutoff circuits 105 and 107, a voltage conversion circuit 109, and a memory cell column. Group 111, a control circuit 119, and a word line WLx (x
= 1, 2, 3,..., M) and a decoder 121. The main decoder group 103 further includes a plurality of main decoders 115x (x = 1, 2, 3,..., M).
The memory cell column group 111 includes a plurality of memory cell columns 117x.
(X = 1, 2, 3,..., M). The decoder 121 selectively outputs data from the bit line BL. The main decoder 115x is connected to the corresponding word line WLx
And the word line WLx is connected to the corresponding memory cell column 1
15x. The bit lines connected to the memory cells in the memory cell column are indicated by BL, and the source lines are indicated by S. A signal cutoff circuit 105 is connected between the predecoder 101 and the main decoder group 103. Signal cutoff circuit 10
A signal cutoff circuit 107 is connected between a connection node between the power supply 5 and the main decoder group 103 and the voltage conversion circuit 109. Predecoder 101 is always driven by normal power supply voltage Vcc regardless of operations such as reading, writing, and erasing.

FIG. 2 shows the signal cutoff circuit 107 shown in FIG.
2 is a circuit diagram illustrating an example of a voltage conversion circuit 109. FIG. The signal cutoff circuit 107 is formed of, for example, a MOS transistor, and is turned on / off in response to a control signal CUT2 from the control circuit 119. Although not shown, the signal cutoff circuit 10
Reference numeral 5 also includes a MOS transistor, for example, and is turned on / off in response to a control signal CUT1 from the control circuit 119. Even if the voltage conversion circuit 109 is disconnected from the predecoder 101 by the signal cutoff circuit 107 (or 105), the output PDOUT of the predecoder 101 received immediately before is output.
Has a latch circuit composed of two inverters capable of holding the current. The output PDOUT is converted by the voltage conversion circuit 109, and the obtained high voltage is input to the main decoder group 103.

A decoder and its peripheral circuit 100 will be described below.
Will be described. FIG. 3 shows the control circuit 11 shown in FIG.
9A and 9B are timing charts showing control signals CUT1 and CUT2 of the signal cutoff circuits 105 and 107 output from the memory cell column group 111, and FIG. 5 is a timing chart when data is written or erased. Here, the signal cutoff circuits 105 and 107 are turned on when the control signals CUT1 and CUT2 are at the H level, and are turned off when the control signals CUT1 and CUT2 are at the L level.

Referring to FIGS. 1 and 3A, first, at the time of data reading, after the operation starts, control signal CUT1 goes high and control signal CUT2 remains low, so that
The signal cutoff circuit 105 remains on, and the signal cutoff circuit 107 remains off. Therefore, the output PDOUT from the predecoder 101 passes through the signal cutoff circuit 105 and is input to the main decoder group 103. At this time, since the signal cutoff circuit 107 is off, the output PDOUT is not input to the voltage conversion circuit 109. Therefore, the structure is not input to the main decoder group 103 via the voltage conversion circuit 109, so that a delay in access time as in the conventional case can be eliminated.

Referring to FIGS. 1 and 3B, when data is written or erased, control signals CUT1 and CUT2 are both at H level for the first predetermined time T after the start of operation.
The signal cutoff circuits 105 and 107 are both turned on. Therefore, the output PDOUT from the predecoder 101 is input to the voltage conversion circuit 109 via the signal cutoff circuits 105 and 107, and the voltage conversion circuit 109 latches the value.
When a predetermined time T has elapsed and the latch is completed, the control signal CUT
1 is at the L level, and the signal cutoff circuit 105 is turned off. The latched predecoder output PDOUT is voltage-converted by raising or lowering the power supply voltages VPWLG and VNWL of the voltage conversion circuit 109 to generate a positive or negative high voltage. The generated high voltage is input to the main decoder group 103 via the signal cutoff circuit 107.
Power supply voltages VPWLG, VNW of main decoder group 103
L is also stepped up or stepped down at the same time, and the main decoder group 103 operates according to the voltage-converted logic, and its output is supplied to the word line WLx. During this operation, since the signal cutoff circuit 105 is in the off state, the high voltage generated by the voltage conversion circuit 109 is not reversely applied to the predecoder 101.

As described above, according to the flash memory according to the first embodiment of the present invention, the output PDOUT of predecoder 101 is applied to main decoder group 103 without passing through voltage conversion circuit 109 during normal access such as data reading.
Is input to Therefore, it is possible to eliminate the delay of the access time without increasing the layout occupation area.

(2) Second Embodiment FIG. 4 is a circuit diagram showing a decoder and its peripheral circuit 400 in a flash memory according to a second embodiment of the present invention. The decoder and its peripheral circuit 400 are shown in FIG.
Are provided with a main decoder group 203 and signal cutoff circuits 205 and 220 in the decoder and its peripheral circuit 100 shown in FIG. Referring to FIG. 4, a connection node between signal cutoff circuit 105 and main decoder group 203,
A signal cutoff circuit 205 is connected between the signal cutoff circuit 107 and a connection node between the main decoder group 103.
The main decoder group 203 is connected to word lines WLy (y = 1, 2, 3,..., N) in the same manner as the main decoder group 103, and the word lines are connected to the memory cell column group 211. The main decoder group 203 further includes a plurality of main decoders 215y (y = 1, 2, 3,..., N).
The memory cell column group 211 includes a plurality of memory cell columns 217y.
(Y = 1, 2, 3,..., N). The signal cutoff circuit 205 also includes a MOS transistor or the like, and turns on / off in response to a control signal CUT3 from the control circuit 119.
Turn off. The bit line BL of the memory cell column group 111 and the bit line BL of the memory cell column group 211 are
0.

FIG. 5 shows the signal cutoff circuit 220 shown in FIG.
FIG. 4 is a circuit diagram showing an example of the embodiment. Referring to FIG. 5, signal cutoff circuit 220 includes a plurality of NMOS transistors connecting bit lines BL in memory cell column group 111 and bit lines BL in memory cell column group 211, and control signal CUT4 is at H level. Turns on when it is low, and turns off when it is low.

A decoder and its peripheral circuit 400 will be described below.
Will be described. FIG. 6 shows the control circuit 11 shown in FIG.
9, signal cutoff circuits 105, 107 and 20
5,220 control signals CUT1, CUT2, CUT3
6 is a timing chart showing a CUT 4 and a CUT 4;
(A) is for reading data in the memory cell column groups 111 and 211, (b) is for writing or erasing data in the memory cell column groups 111 and 211, and (c) is data reading for the memory cell column group 211. 6 is a timing chart at the time of data writing or erasing in the memory cell column group 111. Here, the control signals CUT1, CUT2,
Signal cutoff circuit 10 when CUT3 and CUT4 are at H level
5, 107, 205, and 220 are turned on, and are turned off when they are at the L level.

First, referring to FIG. 4 and FIGS. 6 (a) and 6 (b), a case where data reading, writing and erasing are performed in both memory cell column groups 111 and 211 will be described. When the signal cutoff circuit 205 is turned on, if the memory cell column groups 111 and 211 are collectively regarded as one memory cell column group, the configuration becomes the same as that of the peripheral circuit 100 according to the first embodiment shown in FIG. Therefore, the same effect can be obtained by controlling the signal cutoff circuits 105 and 107 exactly in the same manner as described in the first embodiment.

Next, referring to FIG. 4 and FIG.
A case where data writing or erasing is performed only by the memory cell column group 111 and normal access such as data reading is performed by the memory cell column group 211 will be described. After the operation starts,
The signal cutoff circuits 105, 107, 205, and 220 are all turned on. A predetermined time T (predecoder 101
(The time required for the output PDOUT to be latched by the voltage conversion circuit 109), the signal cutoff circuit 205 is cut off. As a result, the voltage conversion circuit 109 is separated from the main decoder group 203, and the high voltage obtained by the voltage conversion in the voltage conversion circuit 109 is applied to the main decoder group 20.
3 can be prevented from being applied to the pre-decoder 101 simultaneously. After the lapse of the predetermined time T, the signal cutoff circuit 220 is further cut off, and the memory cell column group
1 bit line BL and bit line B of memory cell column group 211
L is shut off. Therefore, data is not transmitted to the bit line BL of the memory cell column group 111. Therefore, while data writing or erasing is performed in memory cell column group 111, normal access operation such as data reading can be performed in memory cell column group 211.

In the example shown in (c), the signal cutoff circuit 220 is cut off after a predetermined time T has elapsed.
The signal cutoff circuit 220 may be cut off from the beginning.

As described above, according to the flash memory according to the second embodiment of the present invention, similarly to the case of the flash memory according to the first embodiment, memory cell column groups 111,
In the case where a normal access operation such as data reading is performed in both of the main decoder group 211 and the main decoder group 10, the output PDOUT of the predecoder 101 does not pass through the voltage conversion circuit 109.
3,203. Therefore, it is possible to eliminate the delay of the access time without increasing the layout occupation area.

Further, while data is written or erased in the memory cell column group 111, the memory cell column group 2
Normal access such as reading can also be performed at 11.

[0028]

According to the nonvolatile semiconductor memory device of the first aspect, when data is read from the first memory cell column group, the second switching means is cut off by the control means. Without the first
Is input from the first decoding means to the second decoding means. Therefore, it is possible to eliminate the delay of the access time due to the voltage conversion / latch means at the time of data reading.

When the first signal output from the first decoding means is latched by the voltage conversion / latch means, the second switching means is turned off. The output high voltage is the first
Can be prevented from being reversely applied to the decoding means.

According to the nonvolatile semiconductor memory device of the second aspect, in addition to the effect of the first aspect, data writing or data erasing is performed in the first memory cell column group, and the second memory cell column is written. When data reading is performed in the group, the first, second, and third switching means are turned on by the control means, and the first signal is latched by the voltage conversion / latch means after a predetermined time has elapsed. Since the third switching means is turned off, the voltage conversion / latch means is disconnected from the second decoding means, and the second signal output from the voltage conversion / latch means is input to the first decoding means. Is the second
Is not input to the decoding means. Therefore, even when data is written or erased in the first memory cell column group, data can be read in the second memory cell column group.

According to the nonvolatile semiconductor memory device of the third aspect, in addition to the effects of the first and second aspects, the present invention can be applied to a flash memory or the like that requires a high voltage at the time of data writing or data erasing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a decoder and its peripheral circuits in a flash memory according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing an example of the voltage conversion circuit shown in FIG.

FIG. 3 is a timing chart showing control signals of a signal cutoff circuit output from the control circuit shown in FIG. 1;
(A) shows data reading in a memory cell column group,
(B) is a timing chart at the time of data writing or erasing in the memory cell column group.

FIG. 4 is a circuit diagram showing a decoder and its peripheral circuits in a flash memory according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing an example of the signal cutoff circuit shown in FIG.

6 is a timing chart showing a control signal of a signal cutoff circuit output from the control circuit shown in FIG. 4,
(A) is for data reading in two memory cell column groups, (b) is for data writing or erasing in two memory cell column groups, (c) is data reading for one memory cell column group, 10 is a timing chart at the time of data writing or erasing in the other memory cell column group.

FIG. 7 is a circuit diagram showing a decoder and its peripheral circuits in a conventional flash memory.

FIG. 8 is a circuit diagram showing a signal cutoff circuit and a voltage conversion circuit shown in FIG.

[Explanation of symbols]

100, 400 decoder and its peripheral circuit, 101
Predecoder, 103, 203 main decoder group,
105, 107, 205 signal cutoff circuit, 109 voltage conversion circuit, 111, 211 memory cell column group, 115x
(X = 1, 2, 3,..., M), 215y (y = 1, 2, 2, 3)
3,..., N) main decoder, 117x (x = 1,
2,3, ..., m), 217y (y = 1,2,3, ...,
n) memory cell column, 119 control circuit, WLx (x =
, M), WLy (y = 1, 2, 3,...,
n) Word line.

Claims (3)

[Claims] A first selection line group including a plurality of selection lines; a first memory cell column group including a plurality of memory cell columns connected to the selection lines different from each other; A first decoding unit for outputting a first signal for selecting a selection line of the first selection line group; a voltage conversion of the first signal to output a second signal; Voltage conversion / latch means for latching; second decoding means connected to the plurality of selection lines for decoding the first or second signal and outputting a third signal; First switching means connected between the first switching means and the second decoding means; and a connection node between the first switching means and the second decoding means and the voltage conversion / latch means. Connected second switching Means for turning on the first switching means and turning off the second switching means at the time of reading data from the first memory cell column group, and at the time of data writing and data erasing. And a control means for turning on the second switching means and turning off the first switching means after a predetermined time has elapsed. 2. A second group of select lines different from the first group of a plurality of select lines; a second group of memory cells different from the first group of a plurality of memory cell columns; and the first switching Means, and third switching means connected between a connection node between the first memory cell row group and the second switching means, wherein the second memory cell row group is Connected to a connection node between the first switching means and the third switching means, wherein the second control means performs data reading, data writing, and data erasing in the first and second memory cell column groups. Turning on the third switching means, turning on the first, second, and third switching means at the time of data writing and reading only in the first memory cell column group; After between the third
2. The nonvolatile semiconductor memory device according to claim 1, wherein said switching means is turned off. 3. The voltage conversion / latch means according to claim 2, wherein:
3. The nonvolatile semiconductor memory device according to claim 1, wherein said signal is converted into a positive or negative voltage having an absolute value larger than an internal power supply voltage.