JP2004171753A - Semiconductor memory device having structure for making page length convertible, and conversion method of page length therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a structure to make page length convertible, and to provide its conversion method of the page length. <P>SOLUTION: A semiconductor memory device is provided with many banks, and respective banks have many memory cell array blocks, and respective blocks are provided with many sub-memory cell array blocks, and many word line drivers which activate the word lines of corresponding blocks, corresponding to the respective blocks. The blocks are further provided with a control circuit of the page length which makes one or more among the word line drivers activate selectively, by receiving the column block address and predetermined control signals and by responding to the column block address and control signals. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a structure capable of converting a page length and a method of converting the page length.

  The field of utilization of recent semiconductor memory devices is expanding compared to the past. Accordingly, semiconductor memory devices that support various operation modes have appeared. One of such examples is a synchronous semiconductor memory device that variously supports a CAS (Column Address Strobe Latency: CL) and a burst length (Burst Length: BL) by manipulating a mode register set (MRS). It is.

  In order for the semiconductor memory device to support such various modes, the semiconductor memory device has been applied to various electronic devices such as network, communication, control, multimedia, etc. in addition to past use as a main memory of a PC or a server. I have.

  1A to 1C are diagrams schematically illustrating a hierarchical structure of a semiconductor memory device. As shown in FIG. 1A, the semiconductor memory device 100 includes a plurality of banks 100A, 100B, 100C and 100D, and each of the banks 100A to 100D has a plurality of banks as shown in FIG. Of memory cell array blocks 100a, 100b, 100c, and 100d.

  A predetermined bank is selected from a number of banks 100A, 100B, 100C and 100D in response to a predetermined bank address (not shown), and the selected bank is selected in response to a predetermined row address (not shown). A memory access operation is performed by selecting one or more of the memory cell array blocks 100a, 100b, 100c, and 100d at the same time.

  The memory cell array block 100a shown in FIG. 1C includes a plurality of sub memory cell array blocks 110, 120, 130, 140, and word line drivers 111, 121, 131 corresponding to the sub memory cell array blocks 110, 120, 130, 140. , 141, a number of sub-decoders 112, 122, 132, 142 and a row decoder 150.

  In the memory cell array block 100a shown in FIG. 1C, one of a number of sub memory cell array blocks 110, 120, 130, and 140 is divided according to a combination of column block addresses (CBA). Selected. In FIG. 1, two CBAs were used.

  In a data write or read operation, if a second row address (not shown) is input, the row decoder 150 decodes the input second row address and outputs the second row address according to the decoding result. The normal word line enable line NWE corresponding to the row address is activated.

  The sub-decoders 112, 122, 132 and 142 enable an internal power signal of a predetermined boosting level in response to a first row address (not shown), and the internal power signal is activated in response to a second row address. The word lines WL0_0, WL0_1, WL0_2, and WL0_3 are activated through the normalized normal word line enable line NWE and a predetermined switching circuit (not shown).

  Here, the first row address is used to select one internal power supply signal among a plurality of boosting level internal power supply signals, and the second row address is used to select one of a plurality of normal word line enable lines NWE. Used to select one normal word line enable line NWE.

  In the memory cell array block 100a shown in FIG. 1C, when the total number of input addresses is n, the column address used to select a column selection line of each sub memory cell array block is n-2. This is because the two column addresses are used to select one of the four sub memory cell array blocks 110, 120, 130, and 140. Therefore, the page length corresponding to the word line activated per sub memory cell array block is 2n-2.

  However, in a general semiconductor memory device having a structure in which a plurality of sub memory cell array blocks are provided but the sub memory cell array blocks are not partially activated, the entire word line W / having the same second row address is used. L0-0, W / L0-1, W / L0-2, and W / L0-3 are simultaneously activated by switching to the enabled normal word line enable line NWE. Accordingly, in the case of FIG. 1C, the page length is 2n−2 × 22 = 2n.

  If the respective memory devices have different page lengths, they are not interchangeable, so a semiconductor memory device capable of dynamically adjusting the page length is required.

  A technical problem to be solved by the present invention is to provide a semiconductor memory device capable of selectively activating a sub memory cell array block and having a structure capable of converting a page length in response to a control signal. It is in.

  Another technical problem to be solved by the present invention is to provide a method for converting a page length in response to a control signal.

  One aspect of the present invention for achieving the technical object relates to a semiconductor memory device. The semiconductor memory device according to the present invention includes a plurality of banks, each of the banks includes a plurality of memory cell array blocks, each of the memory cell array blocks includes a plurality of sub-memory cell array blocks, and a plurality of the sub-memory cell array blocks. A plurality of word line drivers for activating the word lines of the corresponding sub-memory cell array blocks, receiving a column block address (CBA) and a predetermined control signal, and responding to the CBA and the control signal. A page length control circuit for selectively activating one or more of the word line drivers, wherein a word line of the sub memory cell array block is responsive to activation of the corresponding word line driver. Characterized by being activated .

  Preferably, the page length control circuit receives the CBA and outputs a plurality of output signals obtained by combining the CBA in response to the control signal, and a first row address and a plurality of control circuits of the control circuit. A plurality of sub-decoders receiving an output signal and selectively activating one or more of the word line drivers in response to the first row address and an output signal of the control circuit. Features.

  According to another embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device according to the present invention includes a plurality of banks, each of the banks includes a plurality of memory cell array blocks, each of the memory cell array blocks includes a plurality of sub-memory cell array blocks, and a plurality of the sub-memory cell array blocks. A plurality of word line drivers for activating word lines of the corresponding sub-memory cell array blocks, and a control signal for receiving a command and an address and outputting a predetermined control signal responsive to the command and the address A generation circuit for receiving a column block address (CBA) and a predetermined control signal, and responsive to the CBA and the control signal to selectively activate one or more of the word line drivers. A control circuit; Word lines of the cell array blocks characterized in that it is activated in response to activation of the corresponding word line driver.

  Preferably, when the control signal is inactivated, a word line driver corresponding to a sub memory cell array block selected by the combination of CBAs is activated.

  More preferably, when the control signal is activated, a word line driver corresponding to a sub memory cell array block selected by the control signal is activated regardless of the CBA.

  According to another embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device according to the present invention includes a plurality of banks, each of the banks includes a plurality of memory cell array blocks, and each of the memory cell array blocks includes a first sub memory cell array block to a fourth sub memory cell array block; A first word line driver corresponding to each of the first to fourth sub memory cell array blocks and activating a corresponding one of the first to fourth sub memory cell array blocks; A fourth word line driver, a control signal generation circuit for receiving a command and an address, and outputting a first control signal and a second control signal in response to the command and the address; a column block address (CBA); control And a page length for selectively activating one or more of the word line drivers in response to the CBA, the first control signal, and the second control signal in response to the signal and the second control signal. A control circuit is provided.

  According to another embodiment of the present invention, there is provided a semiconductor memory device. The semiconductor memory device according to the present invention includes a plurality of banks, each of the banks includes a plurality of memory cell array blocks, each of the memory cell array blocks includes a plurality of sub-memory cell array blocks, and a plurality of the sub-memory cell array blocks. A plurality of word line drivers for activating the word lines of the corresponding sub-memory cell array blocks, receiving a column block address (CBA) and a predetermined control signal, and responding to the CBA and the control signal. A page length control circuit for controlling a page length of the semiconductor memory device by selectively activating one or more of the word line drivers. Mode register set that controls the mode Characterized in that an output signal of the (MRS).

  According to another embodiment of the present invention, there is provided a method of converting a page length of a semiconductor memory device. A method of converting a page length of a semiconductor memory device according to the present invention includes the steps of inputting a command and an address from the outside, generating a predetermined control signal corresponding to the command and the address, and responding to a column block address (CBA) and the control signal. Generating a signal for controlling the page length of the semiconductor memory device, and converting the page length of the semiconductor memory device in response to the signal for controlling the page length. The step of selectively activating one or more word line drivers corresponding to one or more sub memory cell array blocks activated in the semiconductor memory device by the signal for controlling the page length is performed. It is characterized by.

  According to another embodiment of the present invention, there is provided a method of converting a page length of a semiconductor memory device. A method of converting a page length of a semiconductor memory device according to the present invention receives a column block address (CBA) and a predetermined control signal, and generates a signal for controlling a page length of the semiconductor memory device in response to the CBA and the control signal. And converting the page length of the semiconductor memory device in response to the signal for controlling the page length, wherein the converting is performed by the signal for controlling the page length of the semiconductor memory device. One or more word line drivers corresponding to one or more sub memory cell array blocks to be activated are selectively activated.

  A semiconductor memory device and a page length conversion method according to the present invention selectively select one or more sub-memory cell blocks existing in a memory cell array block in response to a first row address and a predetermined control signal. By activating, the page length of the semiconductor memory device can be converted.

  That is, there is an effect that the memory devices having different page lengths can be made compatible by making the page length convertible, and the existing semiconductor memory device can be used efficiently.

  Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the drawings. The same reference numerals provided in each figure indicate the same parts.

  FIG. 2 is a block diagram schematically illustrating a memory cell array block of a semiconductor memory device capable of converting a page length according to the present invention. The memory cell array block 200 shown in FIG. 2 includes a plurality of sub memory cell array blocks 110, 120, 130, 140, and a plurality of word line drivers 111, 121 corresponding to the sub memory cell array blocks 110, 120, 130, 140, respectively. , 131, 141, a number of sub-decoders 212, 222, 232, 242, a control circuit 250, and a row decoder 150.

  The sub memory cell array blocks 110, 120, 130, 140 are activated in response to activation of the corresponding word line drivers 111, 121, 131, 141. The control circuit 250 receives the column block address (CBA) and the control signal, and outputs a signal corresponding to the CBA and the control signal to the sub-decoders 212, 222, 232, and 242.

  The row decoder 150 receives the input second row address RAi (i = 2, 3,..., N), and activates the normal word line enable line NWE according to the decoded result. The sub-decoders 212, 222, 232, and 242 receive and decode the output signal of the control circuit 250 and the first row address RAi (i = 0, 1), and selectively select the word line drivers 111, 121, 131, and 141. Activate.

  The word line drivers 111, 121, 131, and 141 receive output signals of the corresponding sub-decoders 212, 222, 232, and 242, and receive normal word line enable lines NWE and word lines of the sub memory cell array blocks 110, 120, 130, and 140. Switching between WL0, WL1, WL2 and WL3.

  Preferably, the control signal is generated by a mode register set (MRS) of the semiconductor memory device. The output signal of the MRS is a signal that can be arbitrarily set and controlled by the user. Therefore, by adjusting the output signal of the MRS and using the output signal as a control signal, the page length of the semiconductor memory device can be adjusted. However, as described below, the control signal can be generated by various other methods.

  A control signal is generated, and the word line drivers 111, 121, 131, and 141 are selectively driven by a combination of the control signal and the CBA, thereby controlling the number of word lines having the same row address to be activated. Thus, the page length of the semiconductor memory device can be adjusted.

  FIG. 3 is a diagram illustrating a memory cell array block of a semiconductor memory device capable of converting a page length according to a preferred embodiment of the present invention. The memory cell array block 300 shown in FIG. 3 includes a plurality of sub memory cell array blocks 110, 120, 130, 140, word line drivers 111, 121, 131, 141, sub decoders 312, 322, 332, 342, a row decoder 150, A control signal generation circuit 350 and a control circuit 360 are provided.

  The memory cell array block 300 includes a predecoder 375, a number of column decoders 371, 372, 373, and 374 and a number of logic circuits 381, 382, 383, 384, 391, 392, 393, 394, 395, 396, 397, and 398. Have.

  The word line drivers 111, 121, 131, 141 correspond to the sub memory cell array blocks 110, 120, 130, 140, respectively, and the sub memory cell array blocks 110, 120, 130, 140 correspond to the corresponding word line drivers 111, 121, 131, It is activated in response to the activation of 141.

  The control signal generation circuit 350 includes a command buffer 351, an address buffer 352, and an MRS 353. The command buffer 351 receives and buffers a predetermined command, and the address buffer 352 receives and buffers an address. The MRS 353 receives the output signal of the command buffer 351 and the output signal of the address buffer 352, and outputs predetermined control signals PL0B and P01B corresponding to the command and the address.

  Control circuit 360 receives CBA CBA0, CBA1 and control signals PL0B, PL1B, and in response to these CBA CBA0, CBA1 and control signals PL0B, PL1B, outputs a number of output signals to a number of sub-decoders 312, 322, 332, 342. Output. The sub-decoders 312, 322, 332, and 342 receive the first row address RAi (i = 0, 1) and the output of the control circuit 360, and receive the first row address RAi (i = 0, 1) and the output of the control circuit 360. One or more of the word line drivers 111, 121, 131 and 141 are selectively activated in response to the signal.

  In this embodiment, the control circuit 360 includes a plurality of inverting circuits 361, 362, 365, 366 and a plurality of NAND circuits 363, 364, 367, 368. The inverting circuit 361 receives and inverts CBA CBA0B and outputs it, and the inverting circuit 362 receives and inverts CBA CBA0 and outputs it. The NAND circuit 363 receives the output signal of the inverting circuit 361 and the control signals PL0B and PL1B, performs a NAND operation on the signals, and outputs the result. NAND circuit 364 receives the output signal of inverting circuit 362 and control signals PL0B and PL1B, performs a NAND operation on the output signal, and outputs the result.

  The inverting circuit 365 receives and inverts CBA CBA1B and outputs it, and the inverting circuit 366 receives and inverts CBA CBA1 and outputs it. NAND circuit 367 receives the output signal of inverting circuit 365 and control signal PL1B, performs a NAND operation on the received signal, and outputs the result. NAND circuit 368 receives the output signal of inverting circuit 366 and control signal PL1B, performs a NAND operation on the received signal, and outputs the result.

  The predecoder 375 receives the column address and performs predecoding. Since the column address here is a column address excluding CBA, if the total number of addresses is n in the present embodiment, the address of (n−2) is input to the predecoder 375.

  Logic circuit 392 receives CBA CBA0B and CBA1B and performs a NAND operation and outputs the result. Logic circuit 394 receives CBA CBA0 and CBA1B and performs an AND operation and outputs the result. Logic circuit 396 outputs CBA CBA0B and CBA1. Is received and NANDed, and then output, and the logic circuit 398 receives CBA CBA0 and CBA1, performs NAND operation, and outputs the result.

  The logic circuit 391 receives and inverts the output signal of the logic circuit 392. The logic circuit 393 receives and inverts the output signal of the logic circuit 394. Logic circuit 395 receives and inverts the output signal of logic circuit 396. The logic circuit 397 receives and inverts the output signal of the logic circuit 398.

  The logic circuit 381 receives the output signal of the logic circuit 391 and the output signal of the predecoder 375, performs a NAND operation on the output, and outputs the result to the column decoder 371. The logic circuit 382 outputs the output signal of the logic circuit 393 and the output signal of the predecoder 375. Is received and NANDed, and then output to the column decoder 372. The logic circuit 383 receives the output signal of the logic circuit 395 and the output signal of the predecoder 375, performs a NAND operation on the output signal, and outputs the result to the column decoder 373. The logic circuit 384 outputs the output signal of the logic circuit 397 and the output of the predecoder 375. The signal is received, NANDed, and then output to the column decoder 374.

  FIG. 4A is a table showing the relationship between the CBA and the page length when the control signals PL0B and PL1B are deactivated. FIGS. 4B and 4C respectively show the control. 9 is a table showing a relationship between CBA and page length when a signal PL0B and a control signal PL1B are activated.

  The operation of the semiconductor memory device according to the present invention will be described with reference to FIGS. 3 and 4A to 4C. The control signal generation circuit 350 receives a command and an address, and generates predetermined control signals PL0B and PL1B responsive to the command and the address. The control signals PL0B and PL1B are generated by a combination of an input command and address.

  The control circuit 360 receives the CBA CBA0 and CBA1 and the control signals PL0B and PL1B, and in response to the CBA CBA0 and CBA1 and the control signals PL0B and PL1B, outputs a predetermined output signal to a number of sub-decoders 312, 322, 332, and 342. Output. Then, one or more of the word line drivers 111, 121, 131, and 141 are selectively activated.

  The sub-decoders 312, 322, 332, and 342 receive the output signal of the control circuit 360 and the first row address RAi (i = 0, 1) and send the output signal to the corresponding word line driver 111, 121, 131, 141. Output.

  The word line drivers 111, 121, 131, and 141 respond to the output signals of the corresponding sub-decoders 312, 322, 332, and 342 to switch between the normal word line enable line NWE and the activated word line. Activate the word line of the sub memory cell array block.

  If both of the control signals PL0B and PL1B are inactivated (for example, in the case of the logic high state in FIG. 3), the control circuit 360 may control the four sub-decoders 312, 322, and 322 according to the combination of CBA CBA0 and CBA1. One of the sub-decoders 332 and 342 is activated, and the activated sub-decoder activates a corresponding word line driver, and is activated with the normal word line enable line NWE by the activated word line driver. The word line is switched.

  FIG. 4A shows the logic states of CBA CBA0 and CBA1 and the activated sub memory cell array block when the control signals PL0B and PL1B are inactivated, and the page of the semiconductor memory device at this time. It is a table showing the length. As shown in FIG. 4A, when the control signals PL0B and PL1B are both inactive and CBA CBA0 and CBA1 are both logic low, the operation of the control circuit 360 and the sub-decoder 312 is performed. As a result, only the word line of sub memory cell array block 0110 is activated.

  As shown in FIG. 4A, when all of the control signals PL0B and PL1B are inactivated, only one of the sub memory cell array blocks 110, 120, 130, and 140 is used. Since the page is activated, the page length for an activated arbitrary row address is 2n-2 as shown in FIG.

  If the control signal PL0B is activated (for example, logic low) and the control signal PL1B is inactivated (for example, logic high), the NAND circuits 363 and 364 of the control circuit 360 to which the control signal PL0B is input are CBA Outputs a logic high logic state regardless of the logic states of CBA0B and CBA0. Therefore, at this time, two sub memory cell array blocks are activated corresponding to the logical states of CBA CBA1B and CBA1.

  FIG. 4B shows the respective logic states of CBA CBA0 and CBA1, the activated sub memory cell array block, and the page length of the semiconductor memory device at this time when the control signal PL0B is activated. It is a table. As shown in FIG. 4B, when CBA CBA1 has a logic low logic state, the word lines of the sub memory cell array block 0 110 and the sub memory cell array block 1 120 regardless of the logic state of CBA CBA0. Is activated.

  In this case, since the page length for an activated arbitrary row address is doubled as compared with the case of FIG. 4A, it becomes 2n−1. That is, if a user needs a semiconductor memory device having a page length of 2n-1, the control signal generation circuit 350 generates an activated control signal PL0B and inputs the generated control signal PL0B to the control circuit 360. Page length can be converted.

  Next, consider the case where control signal PL1B is activated. When the control signal PL1B is activated (for example, logic low), the NAND circuits 363, 364, 367, and 368 of the control circuit 360 receiving the control signal PL1B all change to the logic states of CBA CBA0B, CBA0, CBA1B, and CBA1. Outputs a logic high logic state regardless.

  FIG. 4C shows the logical states of CBA CBA0 and CBA1, the activated sub memory cell array block, and the page length of the semiconductor memory device at this time when the control signal PL1B is activated. It is a table. As shown in FIG. 4C, all four sub-memory cell array blocks 110, 120, 130, and 140 are activated regardless of the logical states of CBA CBA0B, CBA0, CBA1B, and CBA1. Therefore, the page length for the activated arbitrary row address becomes 2n as shown in FIG.

  The change of the page length corresponding to the control signals PL0B and PL1B in relation to the column decoders 371, 372, 373 and 374 of FIG. 3 will be described below with reference to FIGS. When both of the control signals PL0B and PL1B are inactivated, one of the column decoders 371, 372, 373, and 374 corresponds to the logic state of CBA CBA0 and CBA1 as shown in FIG. The column decoder is activated.

  For example, when CBA CBA0 and CBA1 are logic low, only the logic circuits 392, 391, and 381 operate to activate the column decoder 371. That is, the column decoder 371 receives the column address information of the predecoder 375 and selects one of the n−2 column addresses of the sub memory cell array block 0110. That is, since it corresponds to the activated sub memory cell array block 0110, it has a page length of 2n-2.

  If the control signal PL0B is activated, as shown in FIG. 4B, the control circuit 360 switches the sub memory cell array block according to the logical state of CBA CBA1B and CBA1 regardless of the logical state of CBA CBA0 and CBA0B. Activate. At this time, the sub memory cell array block activated in response to the logical states of CBA CBA1B and CBA1 is selected, and activated from among the sub memory cell array blocks activated in response to the logical states of CBA CBA0B and CBA0. The sub memory cell array block in which the column address to be located is determined.

  For example, if CBA1 is a logic low in FIG. 4A, the sub memory cell array block 0 110 and the sub memory cell array block 1 120 are activated. At this time, the column decoder 371 or the column decoder 372 is activated. Must be activated. This is possible by making CBA1 a logic low.

  Thereafter, whether the column address is activated in the sub memory cell array block 0 110 or the column address is activated in the sub memory cell array block 1 120 can be determined according to the logical state of CBA0. For example, in FIG. 3, when CBA0 is logic low, the column decoder 371 is activated in the sub memory cell array block 0 110 and the column address of the sub memory cell array block 0 110 in response to the output signal of the predecoder 375. One of the column addresses is selected.

  Therefore, when the control signal PL0B is activated, the page length doubles as compared with the case where the control signal PL0B is inactivated, so that the page length becomes 2n-1.

  Finally, when the control signal PL1B is activated, all the sub memory cell array blocks 110, 120, 130, 140 are activated irrespective of the logic state of CBA CBA0, CBA1. Therefore, in this case, the logical address of CBA CBA0 and CBA1 determines which of the activated sub memory cell array blocks should activate the column address in which block. Therefore, at this time, the semiconductor memory device has a page length of 2n.

  Preferably, the control signal generating circuit 350 is implemented by an MRS 353 of a semiconductor memory device. The MRS 353 outputs a signal for determining an operation mode of the semiconductor memory device, and the operation mode can be controlled by an address and a command.

  However, the present invention is not limited to the embodiment in which the control signal generation circuit 350 and the MRS 353 receive commands and addresses and generate the control signals PL0B and PL1B as shown in FIG. The control signal generated from the MRS 353 is not limited to a signal generated by a combination of a command and an address, but may be generated by another method. That is, the control signal can be generated in any other form. Other exemplary embodiments in this regard are described below.

  FIG. 5 is a circuit diagram showing one embodiment of the sub-decoder shown in FIG. 3, and FIG. 6 is a circuit diagram showing one embodiment of a word line driver corresponding to one word line. The sub-decoder 312 illustrated in FIG. 5 includes a NAND circuit 510, a first inversion circuit 520, and a second inversion circuit 530.

  The NAND circuit 510 performs a NAND operation on the first row address RAi (i = 0, 1) and the output signals of the NAND circuits 363 and 367 of FIG. 3 and outputs the result. The output signal of the NAND circuit 510 is the second gating signal PXIB. It becomes.

  The first inversion circuit 520 receives the output signal of the NAND circuit 510, and inverts the output signal of the NAND circuit 510 to generate a first gating signal PXIDG. The second inverting circuit 530 receives the output signal of the NAND circuit 510, and inverts the output signal of the NAND circuit 510 to generate an internal power supply signal PXI having a boosting level obtained by boosting an external power supply.

  As shown in FIG. 5, the sub-decoder 312 receives the first row address RAi (i = 0, 1) and the output signals of the NAND circuits 363 and 367 of FIG. 3, and receives the first gating signal PXIDG and the second gating signal PXIDG. It outputs a gating signal PXIB and an internal power supply signal PXI. The first gating signal PXIDG and the internal power supply signal PXI have the same phase, and the first gating signal PXIDG and the second gating signal PXIB have a phase difference of 180 degrees.

  The word line driver 600 shown in FIG. 6 includes a plurality of MOS transistors MN1, MN2, MN3, MN4. The power supply voltage VCC is connected to the gate of the MOS transistor MN1, the drain is connected to the drain of the MOS transistor MN3 as a normal word line enable line NWE, and the source is connected to the gate of the MOS transistor MN2.

  MOS transistor MN2 has a drain connected to internal power supply signal PXI, and a source connected to first node N1. MOS transistor MN3 has a gate connected to first gating signal PXIDG, and a source connected to first node N1. MOS transistor MN4 has a gate connected to second gating signal PXIB, a drain connected to first node 1N1, and a source connected to a ground power supply. Word line WL is connected to first node N1.

  The word line driver 111 shown in FIG. 3 includes the same number of word line drivers 600 as the number of word lines provided in each sub memory cell array block.

  The operation of the sub-decoder 312 and the word line driver 600 will now be described with reference to FIGS. The sub-decoder 312 receives the first row address RAi (i = 0, 1) and the output signals of the NAND circuits 363 and 367 of FIG. 3, and receives the first gating signal PXIDG, the second gating signal PXIB, and the internal power supply signal PXI. Generate

  Here, the first gating signal PXIDG and the internal power supply signal PXI indicate that the input first row address RAi (i = 0, 1) and the output signals of the NAND circuits 363 and 367 in FIG. The second gating signal PXIB has the opposite logic state only when it has a logic high state.

  In the case of the word line driver 600 of FIG. 6, the MOS transistor MN1 is always turned on because the power supply voltage VCC is applied to the gate, the normal word line enable line NWE is also activated, and the MOS transistor MN2 is also turned on. Has become. In FIG. 6, when the first gating signal PXIDG and the internal power supply signal PXI have a logic high logic state and the second gating signal PXIB has a logic low logic state, the MOS transistor MN3 is turned on and the MOS transistor MN3 is turned on. Transistor MN4 turns off. Therefore, in this case, the normal word line enable line NWE and the word line WL are interconnected, and the word line WL is activated.

  On the other hand, when the first gating signal PXIDG and the internal power supply signal PXI have a logic low logic state and the second gating signal PXIB has a logic high logic state, the MOS transistor MN3 is turned off and the MOS transistor MN4 is turned off. Turns on. Accordingly, in this case, the normal word line enable line NWE and the word line WL are not interconnected, and the word line WL is inactivated.

  That is, the sub-decoder 312 and the word line driver 600 activate the word line WL in response to the first row address RAi (i = 0, 1) and the output signal of the control circuit 360.

  FIG. 7 is a diagram showing another example of the control signal generation circuit according to the present invention. The control signal generating circuit 700 shown in FIG. 7 includes a plurality of bonding pads 710a, 710b, 710c, 720a, 720b, 720c and inverting circuits 711, 721.

  Bonding pads 710a and 720a are connected to power supply voltage VCC, and bonding pads 710b and 720b are connected to ground voltage. The input terminal of the inversion circuit 711 is connected to the bonding pad 710c, and the input terminal of the inversion circuit 721 is connected to the bonding pad 720c. Outputs of the inverting circuits 711 and 721 become a first control signal PL0B and a second control signal PL1B, respectively.

  Whether the bonding pads 710c and 720c are connected to the bonding pads 710a and 720a or connected to the bonding pads 710b and 720b is determined in advance during the manufacturing process of the semiconductor memory device. The logical state of the first control signal PL0B and the second control signal PL1B is determined by such a connection relationship.

  In FIG. 7, the bonding pad 710c is connected to the bonding pad 710b, and the bonding pad 720c is connected to the bonding pad 720a. Therefore, the first control signal PL0B has a logic state of a logic low and the second control signal PL1B has a logic high. Logic state. Therefore, referring to FIGS. 3 and 4, FIG. 7 shows a case where the page length of the semiconductor memory device is 2n-1. Of course, the control signal generation circuit 700 shown in FIG. 7 can generate a control signal having a different logic state depending on the connection state between the bonding pads.

  FIG. 8 is a diagram showing still another example of the control signal generation circuit according to the present invention. The control signal generating circuit 800 shown in FIG. 8 includes diode-coupled MOS transistors MP1 and MP2, laser fuses 812 and 822, and inverting circuits 813 and 823.

  MOS transistor MP1 has a diode-coupled form in which a gate and a drain are interconnected, and a source is connected to power supply voltage VCC. The laser fuse 812 is connected between the drain of the MOS transistor MP1 and the ground power supply, and the inversion circuit 813 inverts the signal at the drain terminal of the MOS transistor MP1 and outputs the second control signal PL1B.

  On the other hand, MOS transistor MP2 has a diode-coupled form in which a gate and a drain are interconnected, and a source is connected to power supply voltage VCC. The laser fuse 822 is connected between the drain of the MOS transistor MP2 and the ground power supply, and the inversion circuit 823 inverts the signal at the drain terminal of the MOS transistor MP2 and outputs the first control signal PL0B.

  The logic state of the first control signal PL0B and the second control signal PL1B depends on whether the laser fuses 822 and 812 are cut. That is, if the laser fuse 812 or 822 is blown, the control signal has a logic low logic state, and if the laser fuse 812 or 822 is not blown, the control signal has a logic high logic state.

  In FIG. 8, if the laser fuse 812 is not blown and the laser fuse 822 is blown, the first control signal PL0B becomes a logic low logic state and the second control signal PL1B becomes a logic high logic state, Referring to FIGS. 3 and 4, the page length of the semiconductor memory device is 2n-1. Of course, the control signal generation circuit 800 can generate a control signal having another logic state depending on whether the laser fuses 812 and 822 are cut.

  As described above, the control signal generation circuit can use not only the control signal generation circuit 350 shown in FIG. 3 but also the other example control signal generation circuits 700 and 800 described above.

  FIG. 9 is a flowchart illustrating a method of converting a page length of a semiconductor memory device according to the present invention. In the method of converting the page length of the semiconductor memory device shown in FIG. 9, a step of generating a control signal (step 910), a step of generating a signal for controlling the page length of the semiconductor memory device (step 920), A step of converting the page length in response to a control signal (step 930).

  The method of converting the page length of the semiconductor memory device according to the present invention will be described with reference to FIGS. First, a step of inputting a command and an address from the outside and generating a control signal corresponding to the command and the address is performed (step 910). These steps are performed by the control signal generation circuit 350 shown in FIG.

  After the control signal is generated, a step of generating a signal for controlling the page length of the semiconductor memory device in response to the CBA and the control signal is performed (step 920). These steps are performed by the control circuit 360 shown in FIG.

  After the signal for controlling the page length is generated, the step of converting the page length of the semiconductor memory device in response to the signal for controlling the page length is performed (operation 930). The converting is performed by selectively activating one or more of the plurality of sub-memory cell array blocks of the semiconductor memory device. The word line driver can be activated by activating it.

  In the method of converting the page length of the semiconductor memory device shown in FIG. 9, it is preferable that the control signal is generated by MRS. However, it is clear that the control signals can be generated by other routes without depending on commands and addresses. The MRS is not limited to generating a control signal by inputting a command and an address.

  FIG. 10 is a schematic block diagram illustrating a memory system in which the present invention can be implemented. The memory system 1000 includes a CPU 1001, a memory controller 1002, and a number of memory modules 1003. Each memory module 1003 includes a plurality of semiconductor memory devices 1004 implemented according to the present invention. The CPU 1001 may be a microprocessor unit MPU or a network processing unit NPU. The CPU 1001 is connected to the memory controller 1002 through a first bus system B1 (eg, control bus, data bus, address bus), and the memory controller 1002 is connected through a second bus system B2 (control bus, data bus, address bus). It is connected to the memory module 1003. In the exemplary configuration of FIG. 10, the CPU 1001 controls the memory controller 1002, and the memory controller 1002 controls the memory device 1004 (but the CPU can directly control the memory device without a separate memory controller). Can be embodied as such).

  In the exemplary embodiment of FIG. 10, each memory module 1003 can be represented as, for example, a memory bank, and each memory device 1004 provided to the memory module 1003 can be represented as a memory device embodied by the present invention. In this case, each memory device 1004 can be logically divided into a number of sub-memory blocks, and is controlled as described above to convert the page length. A control circuit for performing a memory access and / or for converting a page length may be located in the memory device 1004.

  In one preferred embodiment, a memory device of one memory module may have a x8 configuration, and a memory device of another memory module may have a x16 configuration. That is, other memory modules can operate with other bit configurations.

  In another preferred embodiment, the memory system comprises one or more separate semiconductor memory devices (instead of the memory module having multiple semiconductor memory devices shown in FIG. 10), a central processing unit (a memory controller is omitted). ). In this embodiment, the memory device is in direct communication with the central processing unit. In addition, one semiconductor memory device may have an x8 bit configuration and another semiconductor memory device may have an x16 bit configuration. That is, the two memory devices may have different bit configurations.

  In yet another embodiment, a memory system according to the present invention may include one or more separate semiconductor memory devices (such as a memory having multiple semiconductor memory devices shown in FIG. 10) in direct communication with a memory controller (not a CPU). Instead of modules). In this embodiment, one memory device may have a x8 bit configuration and another memory device may have a x16 bit configuration.

  The optimal embodiment of the present invention has been disclosed. Although specific terms have been used herein, they are merely used to describe the invention, not to limit the meaning or to limit the scope of the invention, which is set forth in the following claims. Not used. Accordingly, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible. Accordingly, the true technical scope of the present invention should be determined by the appended claims.

  The semiconductor memory device having a structure capable of converting the page length described in the above embodiment and having compatibility with other memory devices is a memory of a PDA, a memory device of a mobile phone, a storage device of a digital camera and an MP3 player, and Can be used for computer memory system.

FIG. 3 is a diagram schematically illustrating a hierarchical structure of a semiconductor memory device. FIG. 3 is a diagram schematically illustrating a hierarchical structure of a semiconductor memory device. FIG. 3 is a diagram schematically illustrating a hierarchical structure of a semiconductor memory device. FIG. 2 is a block diagram schematically illustrating a memory cell array block of a semiconductor memory device capable of converting a page length according to the present invention; FIG. 4 is a diagram illustrating a memory cell array block of a semiconductor memory device capable of converting a page length according to a preferred embodiment of the present invention; FIG. 4 is a diagram illustrating a relationship between CBA and page length when a control signal is deactivated. FIG. 9 is a diagram showing a relationship between CBA and a page length when a control signal PL0B is activated. FIG. 9 is a diagram showing a relationship between CBA and a page length when a control signal PL1B is activated. FIG. 4 is a circuit diagram illustrating one embodiment of a sub-decoder illustrated in FIG. 3. FIG. 3 is a circuit diagram illustrating one embodiment of a word line driver. FIG. 4 is a diagram illustrating another example of the control signal generation circuit according to the present invention. FIG. 9 is a diagram showing still another example of the control signal generation circuit according to the present invention. 4 is a flowchart illustrating a method of converting a page length of a semiconductor memory device according to the present invention. 1 is a schematic block diagram illustrating a memory system in which the present invention can be implemented.

Explanation of reference numerals

110, 120, 130, 140 Sub memory cell array block 111, 121, 131, 141 Word line driver 150 Row decoder 300 Memory cell array block 312, 322, 332, 342 Sub decoder 350 Control signal generation circuit 351 Command buffer 352 Address buffer 353 Mode Register set 360 Control circuit 361,362,365,366 Inverting circuit 363,364,367,368 NAND circuit 371,372,373,374 Column decoder 375 Predecoder 381,382,383,384,391,392,393,394 , 395, 396, 397, 398 Logic circuit CBA0, CBA1, CBA0B, CBA1B Column block address NWE Normal word line enable Rurain PL0B, PL1B control signal WL_0, WL_1, WL_2, WL_3 wordline

Claims (29)

A memory cell array logically divided into a number of memory blocks, each of the memory blocks being designated by a corresponding block address;
A number of word line control circuits, each word line control circuit corresponding to one of the memory blocks, for activating a word line of the corresponding memory block;
A control circuit for selectively controlling the word line control circuit by activating one or more corresponding word lines having the same row address to convert the page length of the semiconductor memory device. Semiconductor memory device.   The control circuit receives a column block address and a first control signal as input signals, and generates a second control signal for selectively activating one or more of the word line control circuits. Item 2. The semiconductor memory device according to item 1.   3. The device of claim 2, wherein the semiconductor memory device further comprises a control signal generation circuit receiving an external command and an external address, and generating the first control signal based on the external command and the external address. Semiconductor memory device. The control signal generation circuit,
An address buffer for receiving the external address and generating an internal address;
A command buffer for receiving the external command and generating an internal command;
4. The semiconductor memory device according to claim 3, further comprising: a mode register set for generating the first control signal based on the internal address and the internal command.   3. The semiconductor memory device according to claim 2, wherein each of the word line control circuits includes a sub-decoder circuit and a corresponding word line driver circuit.   6. The sub-decoder circuit according to claim 5, wherein the sub-decoder circuit receives the second control signal output from the control circuit to selectively activate a row address and the corresponding word line driver circuit. Semiconductor memory device.   2. The semiconductor memory device according to claim 1, wherein the block address includes a row address or a column address. The semiconductor memory device further includes a control signal generation circuit for generating the first control signal,
3. The semiconductor memory device according to claim 2, wherein the control signal generating circuit is configured to generate the first control signal through one of a wire bonding, a metal option, and a fuse option. When the first control signal is deactivated, one word line is enabled in one of the plurality of memory blocks,
3. The method of claim 2, wherein when the first control signal is activated, two or more word lines having the same row address are enabled in two or more of the plurality of memory blocks. The semiconductor memory device according to claim 1. A memory controller for generating a number of command and address signals;
A first memory module that receives the command and the address signal and includes a plurality of memory devices including a first memory device;
The first memory device includes:
A memory cell array logically divided into a number of memory blocks, each of the memory blocks being specified by a corresponding block address;
A number of word line control circuits, each word line control circuit corresponding to one of the memory blocks, for activating a word line of the corresponding memory block;
A control circuit for selectively controlling the word line control circuit by activating one or more corresponding word lines having the same row address to convert a page length of the first memory device. Characteristic memory system. The memory system further includes a second memory module that receives the command and the address signal generated by the memory controller,
The second memory module includes a plurality of memory devices including a second memory device, the second memory device includes a memory cell array logically divided into a plurality of memory blocks,
11. The device of claim 10, wherein the first memory device has a first bit configuration, and the second memory device has a second bit configuration, wherein the first bit configuration and the second bit configuration are different. A memory system according to claim 1.   The control circuit receives a column block address and a first control signal as input signals, and generates a second control signal for selectively activating one or more word line control circuits. 11. The memory system according to 10. The memory system further includes a control signal generation circuit,
The control signal generation circuit,
An address buffer for receiving an address signal generated from the memory controller and generating an internal address;
A command buffer for receiving a command generated from the memory controller and generating an internal command,
The memory system according to claim 12, further comprising: a mode register set for generating the first control signal based on the internal address and the internal command. When the first control signal is deactivated, one word line is enabled in one of the plurality of memory blocks,
14. The method of claim 13, wherein when the first control signal is activated, two or more word lines having the same row address are enabled in two or more of the plurality of memory blocks. A memory system as described. A central processing unit for generating a number of command and address signals;
A first memory module that receives the command and address signals and includes a plurality of memory devices including a first memory device;
The first memory device includes:
A memory cell array logically divided into a number of memory blocks, wherein each of the memory blocks is specified by a corresponding block address;
A number of word line control circuits, each word line control circuit corresponding to one of the memory blocks, for activating a word line of the corresponding memory block;
And a control circuit for selectively controlling the word line control circuit by activating one or more corresponding word lines having the same row address to convert the page length of the first memory device. Characteristic memory system. The memory system further includes a second memory module for receiving the command and address signals generated by the central processing unit,
The second memory module includes a plurality of memory devices including a second memory device, the second memory device includes a memory cell array logically divided into a plurality of memory blocks,
16. The device of claim 15, wherein the first memory device has a first bit configuration, and the second memory device has a second bit configuration, wherein the first bit configuration and the second bit configuration are different. A memory system according to claim 1. The first memory device further includes a control signal generation circuit,
The control signal generation circuit,
An address buffer for receiving an address signal generated from the central processing unit and generating an internal address;
A command buffer for receiving a command generated from the central processing unit and generating an internal command;
The memory system according to claim 15, further comprising: a mode register set for generating the first control signal based on the internal address and the internal command. When the first control signal is deactivated, one word line is enabled in one of the plurality of memory blocks,
18. The method of claim 17, wherein when the first control signal is activated, two or more word lines having the same row address are enabled in two or more memory blocks of the plurality of memory blocks. A memory system as described.   The memory system of claim 15, wherein the central processing unit is a network processing unit. A memory controller for generating a number of command and address signals;
A first memory device that receives the command and address signals;
The first memory device includes:
A memory cell array logically divided into a number of memory blocks, wherein each of the memory blocks is specified by a corresponding block address;
A number of word line control circuits, each word line control circuit corresponding to one of the memory blocks, for activating a word line of the corresponding memory block;
A control circuit for selectively controlling the word line control circuit by activating one or more corresponding word lines having the same row address to convert a page length of the first memory device. Characteristic memory system. The memory system further includes a second memory device receiving the command and address signals generated by the memory controller,
The second memory device includes a memory cell array logically divided into a plurality of memory blocks,
21. The device of claim 20, wherein the first memory device has a first bit configuration, and the second memory device has a second bit configuration, wherein the first bit configuration and the second bit configuration are different. A memory system according to claim 1. A central processing unit for generating a number of command and address signals;
A first memory device that receives the command and address signals;
The first memory device includes:
A memory cell array logically divided into a number of memory blocks, wherein each of the memory blocks is specified by a corresponding block address;
A number of word line control circuits, each word line control circuit corresponding to one of the memory blocks, for activating a word line of the corresponding memory block;
A control circuit for selectively controlling the word line control circuit by activating one or more corresponding word lines having the same row address to convert a page length of the first memory device. Characteristic memory system. The memory system further includes a second memory device receiving the command and address signals generated by the central processing unit,
The second memory device includes a memory cell array logically divided into a plurality of memory blocks,
23. The device of claim 22, wherein the first memory device has a first bit configuration, and the second memory device has a second bit configuration, wherein the first bit configuration and the second bit configuration are different. A memory system according to claim 1.   The memory system of claim 22, wherein the central processing unit is a network processing unit.   23. The memory system according to claim 22, wherein the central processing unit is a microprocessor unit. A method for converting a page length of a semiconductor memory device, comprising a memory cell array logically divided into a plurality of memory blocks, wherein each of the memory blocks is designated by a corresponding block address.
Generating a first control signal identifying one of a number of page length operation modes;
Generating a second control signal based on the first control signal and the block address;
In response to the second control signal, selectively providing one or more word lines of the memory block having the same row address to provide a page length of the semiconductor memory device corresponding to the operation mode of the specific page length. Activating. The first control signal generating step includes:
Receiving a command signal and an address signal;
27. The method of claim 26, further comprising: generating the first control signal based on the command signal and the address signal.   The method of claim 27, wherein the first control signal is generated by a mode register set. Activating one or more word lines, such as the memory block, comprises:
Inputting the second control signal and the row address to a plurality of sub-decoders;
27. The method of claim 26, further comprising: activating one or more word line drivers corresponding to the memory block based on a word line power supply signal generated by the sub-decoder.

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