JP2002074948A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which a memory circuit which can be mounted mixedly with a logic circuit, is mounted while utilizing accumulated design data for the logic circuit. SOLUTION: The logic circuit 102 performs operation processing of data in accordance with externally given data and a control signal, and generates a control signal corresponding to a one operation mode out of a SDRAM operation mode and an EDO-DRAM operation mode. A controller 103 receives a control signal from the logic circuit 102, generates a generate purpose SDRAM control signal, and gives it to a DRAM core 104. The DRAM core 104 is provided with decoding circuits 125, 126 which are provided corresponding respectively to the operation modes, decode corresponding control signals, and generate an internal control signal for a memory cell array 121.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a configuration of a semiconductor integrated circuit device in which a memory core and a logic circuit are mounted on a single chip.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor integrated circuit technology, a circuit configuration aiming at higher integration and higher speed has been put into practical use for further technological innovation. That is, in order to reduce the manufacturing cost and increase the speed of the semiconductor integrated circuit device, the technical development of a semiconductor integrated circuit device in which a semiconductor memory device and a semiconductor logic circuit device are mixedly mounted on a single chip is being promoted.

FIG. 24 shows a semiconductor integrated circuit device in which such a conventional semiconductor memory device and semiconductor logic circuit device are mixedly mounted. The configuration of a semiconductor integrated circuit device 8000 disclosed in Japanese Patent Application Laid-Open No. 10-283777 is disclosed. It is a schematic block diagram shown.

Referring to FIG. 24, in a conventional semiconductor integrated circuit device 8000, a semiconductor memory device, for example, a synchronous dynamic random access memory core (hereinafter referred to as an SDRAM core) 104 and a logic circuit 1
The SDRAM controller 103, which is a high-speed interface, is provided between the logic circuit 102 and the SDRAM core 104 in order to operate a circuit including the H.02 at a high speed.

More specifically, the semiconductor integrated circuit device 8000 includes a terminal group 110 for supplying control signals and data to the logic circuit 102 as an external terminal group 101 for receiving a control signal from the outside, and a clock generation circuit 106. And an external clock input terminal 105 for supplying a clock signal from the outside.

[0006] The SDRAM controller 103 operates in response to a clock signal CLK supplied from a clock generation circuit 106, and operates under the control of a logic circuit 102 to generate an SDRAM.
An activation signal ACT (114), which is an internal control signal, and a precharge signal PRC (11
5), write signal WRITE (116), read signal R
EAD (117), refresh signal REF (118)
And so on.

The input synchronizing latch circuit 8122
The signal input to the AM core 104 is latched, and the timing generation circuit 8123
An internal operation signal applied to memory array 8121 is generated according to the output from 122. The input synchronization latch circuit 8122 operates in synchronization with the clock signal CLK from the clock generation circuit 106.

The output control circuit 8124 is connected to the memory array 8
Synchronizing the output of C.121 with the internal clock signal CLK,
Output to SDRAM controller 103.

That is, a signal input to the external terminal group 101 is transmitted to the logic circuit 102 and the SDRAM controller 10.
3. The signal is sequentially converted through an input synchronization latch circuit 8122 and a timing generation circuit 8123 and provided to a memory array 8121.

Internal operation signals applied to memory array 8121 include a signal for designating the activation time of a word line, a signal for instructing start and stop of a precharge operation of a bit line pair, and a signal for a sense amplifier. A signal for instructing start and stop of operation, a memory cell column select signal for selectively reading data from a bit line pair, and a read amplifier for reading data from a bit line pair are activated. Driver activation signal for driving a write driver for transmitting write data to a bit line pair.

Here, an internal control signal given from the SDRAM controller 103 to the SDRAM core 104 is as follows:
It has already been converted to an internal control signal for operating the timing generation circuit 8123.

That is, the SDRAM is a one-chip SDR
In the case of an AM memory, an external control signal is supplied from an external terminal to the SDRAM memory, and the SDRAM memory operates according to the external control signal.
Since the number of external terminals is limited in a DRAM, it is common to provide a decoder for decoding such an external control signal inside.

If such a command decoder for decoding a command based on an externally applied control signal is provided also in SDRAM core 104 shown in FIG. 24, the SDRAM core 104 may be provided due to the delay time in the command register. The operation of 104 will be delayed.

In the configuration shown in FIG. 24, since such a command decoder is omitted, it is possible to operate at a correspondingly high speed.

FIG. 25 is a timing chart for explaining the operation of semiconductor integrated circuit device 8000 shown in FIG.

For example, internal control signal ACT (114)
Is generated inside the SDRAM controller 103 in synchronization with the rising edge timing of the internal clock signal CLK at time t0. Therefore, after delaying by t (control) time from the rising edge of internal clock signal CLK at time t0, SDRA
Output from the M controller 103.

Assuming that the setup time in the input synchronization latch circuit 8122 is t (setup), the input synchronization latch circuit 8122 starts the signal ACT (114) from the rising edge of the signal CLK (107) at time t0.
At the time t1 after one cycle of t (CLK) from the time t0, the following expression needs to be satisfied.

T (CLK)> t (control) + t
(Setup) Other internal control signals PRC (115), W
The same applies to RITE (116), READ (117), and the like.

As described above, since the decoding time in the SDRAM core 104 is not required for the minimum cycle of the internal clock signal CLK, the operation speed can be improved by this amount.

[0020]

With the configuration of the semiconductor integrated circuit device 8000 as described above, although the operation speed can be improved, there are the following problems.

That is, generally, the semiconductor integrated circuit device 8
When the design of 000 is performed, it is desirable that the circuit configuration of the SDRAM core 104 be used even if the logic circuit 102 is different.

On the other hand, it is desirable that the logic circuit 102 is also designed in the past and has a proven circuit configuration as it is.

However, the logic circuit 102 is a general-purpose SDRA
When designed to output a control signal for the M chip, the SDRAM core 104 is configured to receive an internal control signal obtained by decoding a general-purpose SDRAM control signal from an interface. For this reason, the SDRAM controller 103
It is necessary to have a function of converting the SDRAM control signal from the IC to the internal control signal.

However, the conventionally stored logic circuit 1
The design data 02 is used not only when the external control signal for the specific general-purpose SDRAM is output to the interface but also when the external control signal for the clock synchronous EDO-DRAM (Extended Data Out-DRAM) is output. In some cases, an external command system given to the interface is adopted.

Therefore, in the conventional logic circuit in which design data is stored, each time the interface specification of the memory that exchanges the data is different, in other words, every time the external command system is changed, the design of the interface is changed. It is necessary to do again. This is because the SDRAM controller 103 is
This means that it is necessary to redesign each time according to the interface specification of the SDRAM core 104 corresponding thereto, and there is a problem that the design efficiency is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to utilize a design data stored in a logic circuit and efficiently interface with the design data. It is an object of the present invention to provide a semiconductor integrated circuit device in which a memory circuit capable of performing the same is mounted.

Another object of the present invention is to provide an existing general-purpose SDR.
An object of the present invention is to provide a semiconductor storage device library for an embedded semiconductor that can support various interfaces such as an AM and a clock synchronous EDO-DRAM.

Still another object of the present invention is to provide a semiconductor integrated circuit device capable of directly testing a semiconductor memory in a semiconductor integrated circuit device in which a semiconductor memory and a semiconductor logic circuit are mixed.

[0029]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device which performs arithmetic processing on data in accordance with externally applied data and a control signal, and performs one of a plurality of operation modes. A logic circuit that generates a control signal corresponding to one operation mode, a control circuit that receives a control signal from the logic circuit and generates a memory control signal group having a plurality of memory control signals, and a logic circuit. A memory circuit for transmitting and receiving storage data and storing the storage data, wherein the memory circuit includes a memory cell array having a plurality of memory cells for storing the storage data, and a plurality of memory cells respectively corresponding to a plurality of operation modes. Control signal input nodes that can receive the memory control signal group of Is, decodes the memory control signal group applied to the corresponding control signal input nodes,
And a plurality of decode circuits for generating internal control signals for the memory cell array, for transmitting a memory control signal group from the control circuit to one control signal input node group of the plurality of control signal input nodes. Further provided.

According to a second aspect of the present invention, in addition to the configuration of the semiconductor integrated circuit device according to the first aspect, the memory circuit is designated from among the plurality of decode circuits in response to an external instruction. A selection circuit for selecting an internal control signal from the decoded circuit.

According to a third aspect of the present invention, in addition to the configuration of the semiconductor integrated circuit device according to the second aspect, the semiconductor integrated circuit device further comprises a clock for generating an internal clock signal based on an external clock signal. The memory circuit further includes a generation circuit, wherein the memory circuit holds the internal control signal from the selection circuit in synchronization with the internal clock signal, and performs an operation of selecting a memory cell in the memory cell array in accordance with an output from the latch circuit. A memory cell array control circuit for generating a memory cell array control signal for controlling.

In the semiconductor integrated circuit device according to a fourth aspect, in addition to the configuration of the semiconductor integrated circuit device according to the third aspect, the plurality of operation modes include an operation mode as a synchronous dynamic semiconductor memory device and a clock synchronization mode. EDO—operation mode as a dynamic type semiconductor memory device.

According to a fifth aspect of the present invention, in addition to the configuration of the semiconductor integrated circuit device of the first aspect, a memory circuit is provided corresponding to each of the plurality of decode circuits and receives a test control signal. A plurality of test signal input terminal groups, a plurality of control signal input node groups, and a plurality of test signal input terminal groups. And a plurality of switching circuits for supplying one of them to the plurality of decoding circuits in accordance with an instruction from the outside, and a designated one of the plurality of decoding circuits in response to the instruction from the outside. A selection circuit for selecting an internal control signal from the decoded circuit, and a plurality of test data input / output terminals for exchanging data with the outside,
The test operation mode further includes an input / output control circuit for controlling data transmission between the memory cell array and the plurality of test data input / output terminals.

According to a sixth aspect of the present invention, in addition to the configuration of the semiconductor integrated circuit device of the first aspect, the memory circuit further includes a test signal input terminal group for receiving a test control signal, A selection circuit for selecting any of an internal control signal from a plurality of decoding circuits and a signal from a test signal input terminal group according to an instruction;
A plurality of test data input / output terminals for exchanging data with the outside, and an input / output control circuit for controlling data transmission between the memory cell array and the plurality of test data input / output terminals in a test operation mode Further included.

According to a seventh aspect of the present invention, in addition to the configuration of the semiconductor integrated circuit device according to the fifth or sixth aspect, the semiconductor integrated circuit device generates an internal clock signal based on an external clock signal. A latch circuit for holding an internal control signal from the selection circuit in synchronization with the internal clock signal; and selecting a memory cell in the memory cell array in accordance with an output from the latch circuit. A memory cell array control circuit for generating a memory cell array control signal for controlling the operation.

In the semiconductor integrated circuit device according to the eighth aspect, in addition to the configuration of the semiconductor integrated circuit device according to the seventh aspect, the plurality of operation modes include an operation mode as a synchronous dynamic type semiconductor memory device and a clock synchronization mode. EDO—operation mode as a dynamic type semiconductor memory device.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a schematic block diagram showing a configuration of a semiconductor integrated circuit device 1000 according to a first embodiment of the present invention.

Referring to FIG. 1, semiconductor integrated circuit device 10
Reference numeral 00 denotes an external terminal group 101 for receiving a control signal from the outside and exchanging data with the outside, an external clock input terminal 105 for receiving a clock signal from the outside, and an external clock input terminal 105. A clock generation circuit 106 for receiving an external clock signal received from a terminal 105 to generate an internal clock signal CLK, and operating in response to the internal clock signal CLK from the clock generation circuit 106 and controlling from an external terminal group 101 A logic circuit 102 for performing a logical operation on signals and input data;
The logic circuit 10 operates in response to the internal clock signal CLK, and
A command input switching signal S for switching a mode of an operation command from outside to a general-purpose SDRAM controller 103 for outputting a general-purpose SDRAM control signal in accordance with a signal given from
Controlled by a switching signal input terminal 108 receiving CS, a signal SCS from the switching signal input terminal 108, and a signal provided from the general-purpose SDRAM controller 103 via the wiring 111, data from the logic circuit 102 is designated. DRAM core 104 for storing data in an address area or outputting data stored in a specified address area to general-purpose SDRAM controller 103
And

The DRAM core 104 receives a general-purpose SDRAM control signal / CS from the general-purpose SDRAM controller 103.
_S, / RAS_S, / CAS_S, / WE_S, and the address signal input, the internal control signals ACT, P
RC, WRITE, READ, REF and internal decode address signal int. First to convert to DAdd
Command decoder circuit 125 and a general-purpose EDO-DRA
M control signals / CS_E, / RAS_E, / CAS_E,
/ WE_E, / RAUT, and the address signal input to E
When received from DODRAM command input node 109, second command decoder circuit 12 outputs an internal control signal converted from the EDO-DRAM control signal.
6 and outputs from the first command decoder circuit 125 and the second command decoder circuit 126, and selectively outputs one of them according to the command input switching signal SCS provided from the switching signal input terminal 108. Input select circuit 127 for performing the
7, an input synchronization latch circuit 122 for latching the internal control signal from the internal control signal 7 in synchronization with the internal clock signal CLK;
A memory cell array control circuit 123 for receiving an internal control signal supplied from the input synchronization latch circuit 122 and generating an internal operation signal for the memory cell array 121;
A memory cell array 121 in which memory cells MC for storing data are arranged in a matrix;
And an output circuit 124 for outputting the output from the general-purpose SDRAM controller 103 in synchronization with the internal clock signal CLK.

The memory cell MC included in the memory cell array 121 includes a memory cell transistor MT and a memory cell capacitor MC.

The data input DataIN to be written to the memory cell array 121 is also supplied from the general-purpose SDRAM controller 103 to the input synchronization latch 122, and this input data DataIN is supplied from the input synchronization latch circuit 122 via the memory cell array control circuit 123. Is given to the memory cell array 121.

That is, the signals input to the external terminal group 101 are transmitted to the logic circuit 102, the general-purpose SDRAM controller 103, the general-purpose SDRAM command decoder circuit 125,
The signal is converted through the input select circuit 127, the input synchronization latch 122, and the memory cell array control circuit 123, and is input to the memory array 121. At this time, for example, command input switching signal SCS is fixed at “H” level.

FIG. 2 shows the input select circuit 1 shown in FIG.
27, receives an internal control signal output from the first command decoder circuit 125 and an internal control signal ACT corresponding to the internal control signal output from the second command decoder circuit 126. FIG. 4 is a circuit diagram showing a configuration of a switching circuit 200 for selectively outputting in response to an input switching signal SCS.

It is assumed that a similar switching circuit is provided for other internal control signals. Switching circuit 200 receives signal ACT from first command decoder circuit 125, receives first drive circuit 1001 activated in response to the command switching signal, and receives and inverts command switching signal SCS for output. Inverter 1002 for the second
And a drive circuit 1003 that receives signal ACT from command decoder circuit 126 of FIG.

A signal output from drive circuit 1001 or 1003 is supplied from input select circuit 127 to input synchronization latch circuit 122 as internal control signal ACT.

FIG. 3 is a diagram showing the correspondence between general-purpose SDRAM commands and internal control signals. In the first command decoder circuit 125 shown in FIG.
The conversion from the RAM command to the internal control signal is performed.

For example, chip select signal / CS =
"L", row address strobe signal / RAS = "L",
When the column address strobe signal / CAS = "H" and the write enable signal / WE = "H" level,
Of the internal control signals output from the first command decoder circuit 125, only the signal ACT is at "H" level.

Other internal control signals PRC, WRITE, R
For EAD and REF, general-purpose SDRA
The combination of the activation levels of the M command signal is decoded, and one of them is activated.

FIG. 4 is a timing chart for explaining the operation of semiconductor integrated circuit device 1000 shown in FIG.

Referring to FIG. 4, at time t1, at the rising edge of internal clock signal CLK, general-purpose SD
General-purpose SDRAM control signal / CS applied from RAM controller 103 to first command decoder circuit 125
In response to both _S and / RAS_S being active (“L” level), first command decoder circuit 125 drives signal ACT, which is an internal control signal, to an active state (“H” level). .

At time t1, signal / RAS_S
Is active, general-purpose SDRAM controller 103 outputs a row address signal Xa.

In response, an address signal is output from first command decoder circuit 125 to input select circuit 127.

Similarly, at the rising edge of internal clock signal CLK at time t3, general-purpose SDR
AM control signals / CS_S and / CAS_S, / WE_
A write mode is designated in response to S being active. At this time, a column address signal Ya for writing data from the general-purpose SDRAM controller 103 is simultaneously output.
It is provided to the first command decoder circuit 125.

In response, the command decoder circuit 12
5 makes the internal control signal WRITE active ("H" level) and outputs the address signal Ya to the input select circuit 127.

Further, the general-purpose SDRAM controller 10
3, the write data D is supplied to the input synchronization latch circuit 122.

Internal clock signal CLK at time t5
At the rising edge of, the read mode is designated in response to general-purpose SDRAM control signals / CS_S and / CAS_S being active. At this time,
A column address signal Yb for reading data from general-purpose SDRAM controller 103 is applied to second command decoder circuit 125.

In response, the command decoder circuit 12
5 makes the internal control signal READ active ("H" level) and outputs the address signal Yb to the input select circuit 127.

Further, data D read from the memory cell selected according to address signal Yb is supplied at time t6.
, Is output from the output circuit 124 to the general-purpose SDRAM controller 103.

Internal clock signal CLK at time t7
At the rising edge of the general-purpose SDRAM controller 103, the general-purpose SDRAM controller 103 is in the active state ("L" level).
Outputs DRAM control signals / CS_S and / WE_S.

In response, first command decoder circuit 125 drives internal control signal PRC to an active state (“H” level) and supplies it to input select circuit 127.
From the input select circuit 127 to the input synchronization latch circuit 12
By applying internal control signal PRC to memory cell array control circuit 123 through memory cell array 2, memory cell array 121 performs a precharge operation.

That is, in the semiconductor integrated circuit device 1000 shown in FIG. 1, in response to the command input switching signal SCS provided from the switching signal input terminal 108, the input select circuit 127 causes the first command decoder circuit 12
5 is selectively supplied to the input synchronization latch circuit 122. As a result, the general-purpose SDRAM controller 10
3 to control the operation of the SDRAM.

FIG. 5 shows D in Embodiment 1 of the present invention.
A RAM core 104 is used as an EDO-DRAM for clock synchronization.
Semiconductor integrated circuit device 1000 'when operated as
FIG. 2 is a schematic block diagram for explaining the configuration of FIG.

The semiconductor integrated circuit device 1000 shown in FIG.
Are different from the configuration of the first embodiment in that the logic circuit 502 is a circuit for generating and outputting a control signal for the clock synchronous EDO-DRAM.
03 is provided, and the clock synchronous ED
The output of the O-DRAM controller 503 is provided to the second command decoder circuit 126 instead of the first command decoder circuit 125.

Further, in semiconductor integrated circuit device 1000 ′, command input switching signal SCS applied from switching signal input terminal 108 is at “L” level, and input select circuit 127 is connected to second command decoder circuit 1.
26 is selectively used as an input synchronization latch circuit 122.
This is the configuration that is given to

Since the other structure is the same as that of semiconductor integrated circuit device 1000 shown in FIG. 1, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 6 is a diagram showing the correspondence between the contents of general-purpose commands of the clock synchronous EDO-DRAM and the corresponding internal control signals output from the second command decoder circuit 126.

For example, if the general-purpose EDO-DRAM control signals / CS_E and / RAS_E are both at the "L" level and the general-purpose EDO-DRAM command signal / CA
When both S_E and signal RAUT are at “H” level, second command decoder circuit 126 that operates in response to this drives only signal ACT to “H” level. In FIG. 6, the symbol X indicates that the value is not considered when decoding the internal control signal (command).

In response to another combination of the general-purpose clock synchronous EDO-DRAM command signal, the second command decoder circuit 126 outputs one of the internal control signals PRC, WRITE, READ, and REF corresponding to the decoding result. Activated state.

FIG. 7 is a timing chart for explaining the operation of semiconductor integrated circuit device 1000 'shown in FIG. 5, and is a diagram compared with FIG.

The difference from the general SDRAM command shown in FIG. 4 is that at time t3 and time t5, the signal / CAS_E of the general clock synchronous EDO-DRAM command is output.
Is activated, the signal / RAS_E also needs to be activated ("L" level).

Other points are the same as those of DRAM core 104 shown in FIG. 4, and therefore, description thereof will not be repeated.

[Comparison of Configuration of DRAM Core 104 with Configuration of One-Chip SDRAM] As described with reference to FIGS. 1 and 5, the DRAM core is a first command decoder for operating in response to a general-purpose SDRAM control command. Circuit 1
25, and a second command decoder circuit 12 for operating in response to a general-purpose clock synchronous EDO-DRAM command.
6 is provided.

For example, even when operating in response to a general-purpose SDRAM control command, the configuration of DRAM core 104 differs from the configuration of a general one-chip general-purpose SDRAM in the transmission path of command signals from the viewpoint of improving the operation speed. . Hereinafter, the difference will be described.

[Transmission Path of Control Signal of One-Chip General-Purpose SDRAM] First, a transmission path of a control signal of one-chip general-purpose SDRAM will be described. FIG. 8 shows an externally applied control signal / C in a one-chip general-purpose SDRAM.
S, / RAS, / CAS, / WE and the address input are converted into internal control signals, and
FIG. 2 is a schematic block diagram for explaining a path provided to the path No. 1;

Referring to FIG. 8, external control signal input terminal 1
01, control signals / CS, / RAS, /
CAS, / WE and the address input are connected to the clock signal C
It is taken in by an input synchronization latch circuit 122 that operates in synchronization with LK. From the input synchronization latch circuit 122,
The externally applied control signal is the internal control signal int. C
S, int. RAS, int. CAS and int. W
E and the address input is the internal address signal i
nt. It is converted to Add and output.

Command decoder 125.1 has an internal control signal int. CS, int. RAS, int. CAS and int. In response to WE, internal control signals ACT, PR
Convert to C, REF, WRITE and READ. On the other hand, address decoder 125.2 provides internal address signal int. Add, the decoded address signal int. DADD is output.

The row-related timing control circuit 123.1 includes:
In response to internal control signals ACT, PRC and REF, word line activation signal WDACT is supplied to memory cell array 121.
Give to.

On the other hand, column related timing control circuit 123.2
Receives internal control signals WRITE and READ, and performs a write driver activation signal WDE or a read amplifier activation signal P depending on whether a write operation or a read operation is performed.
AE is applied to the memory cell array 121.

Decode address int. Provided from address decoder 125.2. In accordance with DAdd, data is read from a selected memory cell in memory cell array 121, or data is written to the selected memory cell. The input data to be written is the data supplied to the input synchronization latch circuit 122.
IN is converted into an internal write signal int-D and applied to memory cell array 121, and internal read data int-Q read from memory cell array 121 is output to the outside as output data DataOUT via output synchronizing circuit 124. You.

FIG. 9 is a diagram showing one-chip SDRA shown in FIG.
6 is a timing chart for explaining the operation of M.

At the rising edge of clock signal CLK at time t1, activation of SDRAM is instructed in response to both the internally applied control signals / CS and / RAS being active ("L" level). You. At the same time, at time t1, the row address signal Xa
Is applied to the input synchronization latch circuit 122.

From input synchronizing latch circuit 122, in response to signals / CS and / RAS being active,
Active internal control signal int. CS and int. RAS
Is output, and internal row address signal int. Add is also output.

The signal int. CS and int. Active control signal ACT is output from command decoder 125.1 in response to the activation of RAS ("L" level), and row-related timing control circuit 123.1 accordingly.
Outputs an active word line activation signal WDACT.

In memory cell array 121, an address decoder 125.2 is provided by a row decoder (not shown).
The word line is selected at the timing of activation of signal WDACT according to the decode address from.

Subsequently, at the activation edge of clock signal CLK at time t3, externally applied signal / C
A data write operation is designated according to the fact that S, / CAS and / WE are all in the active state ("L" level). At this time, at time t3, a column address signal Ya for performing data writing is externally applied.

From the address synchronization latch circuit 122,
In response to activation of external control signals / CS, / CAS and / WE, internal control signals int. CS, i
nt. CAS, int. WE is output and the internal address signal int. Add is also output. Command decoder 125.1 receives signal int. CS, int. C
AS and int. The internal control signal WRITE is activated in response to the activation of WE. Column-related timing control circuit 123.2 is activated in response to the activation of signal WRITE, and performs an input synchronization latch for a column of a memory cell array selected by a decode address output from address decoder 125.2. Internal write data int-D output from circuit 122 is written to a memory cell selected in response to activation of signal WDE.

Subsequently, the clock signal CL at time t5
At the activation edge of K, a data read mode is designated in response to the activation of externally applied control signals / CS and / CAS. At time t5, input synchronization latch circuit 122 is supplied with column address signal Yb for data reading.

The input synchronizing latch circuit 122 outputs the signal / C
S and / CAS are activated in response to activation of internal control signal int. CS and int. Output CAS.
Further, input synchronization latch circuit 122 responds to column address signal Yb applied at time t5 to generate internal address signal int. Add to the address decoder 125.2
Give to.

Signal int. CS and int. In response to the activation of CAS, command decoder 125.1 activates internal control signal READ, and in response, column related timing control circuit 123.2 activates read amplifier activation signal PAE. In response to activation of signal PAE, data is read from the memory cell selected by the decode address output from address decoder 125.2, and applied to output circuit 124 as internal read data int-Q. At t6, the data is output to the outside as output data DataOUT.

Further, the clock signal C at time t7
At the rising edge of LK, input synchronization latch circuit 122 responds to the activation of both externally applied control signals / CS and / WE in response to signal in.
t. CS and int. WE is activated. Command decoder 125.1 receives signal int. CS and in
t. The precharge signal PRC is activated in response to the activation of WE. Row related timing control circuit 123.1
Drives word line activation signal WDACT to an inactive state ("L" level) in response to activation of signal PRC.

With the above operation, one-chip SD
In the RAM, after the combination of the levels of the general-purpose SDRAM control signal is taken into the input synchronization latch circuit 122 in response to the activation edge of the clock signal CLK, according to the output means from the input synchronization latch circuit 122, An internal control signal is output from command decoder 125.1, and a read operation or a write operation for memory cell array 121 is controlled accordingly.

FIG. 10 shows a first command decoder circuit 125 operating in response to a general-purpose SDRAM control signal provided from general-purpose SDRAM controller 103, and an input synchronization latch in the configuration of semiconductor integrated circuit device 1000 shown in FIG. Circuit 122 and memory cell array control circuit 1
23 is a schematic block diagram showing a configuration of an output circuit 124 part.

In FIG. 10, input select circuit 127 shown in FIG. 1 is omitted for simplicity of description.

Compared with FIG. 8, the general-purpose SDRAM control signal supplied from general-purpose SDRAM controller 103 is firstly composed of command decoder 125.1 and address decoder 125.1 in first command decoder circuit 125.
2 is latched by an internal control signal latch circuit 122.1 operating in synchronization with the clock CLK in the input synchronization latch circuit 122 after being supplied to the latch circuit 122.

The general-purpose SDRAM controller 103
Is latched by the data latch circuit 122.2 operating in synchronization with the clock CLK in the input synchronization latch circuit 122, and the data int
−D is given to the memory cell array 121. In response to internal control signals ACT, PRC and REF from internal control signal latch circuit 122.1, row-related timing control circuit 123.1 provides word line activation signal WD.
ACT is applied to the memory cell array 121. On the other hand, column-related timing control circuit 123.2 includes internal control signal WRITE from internal control signal latch circuit 122.1.
And READ, the write driver activation signal WDE or the read amplifier activation signal PAE is applied to the memory cell array 121 according to whether the operation is a write operation or a read operation.
Give to. The read data int-Q from the memory cell array 121 is included in the output circuit 124 and is latched by the output synchronizing circuit 124.1 operating in synchronization with the clock CLK, and is sent to the general-purpose SDRAM controller 103 as data DataOut. Is output.

FIG. 11 shows the DRAM core 1 shown in FIG.
4 is a timing chart for explaining the operation of the circuit No. 04.

First, at time t0, the general-purpose SDRAM
When signals / CS and / RAS of the general-purpose SDRAM control signals applied from controller 103 are activated, internal control signal int. ACT changes to the active state. Further, at time t0, row address signal Xa is applied to address decoder 125.2, and decoded internal decode address signal int. DAdd is output from the address decoder 125.2.

Subsequently, the clock signal C at time t1
LK at the rising edge of the latch circuit 122.
1 is a signal int. When ACT is active, internal control signal ACT is activated.
To an active state. In response, row related timing control circuit 123.1 provides word line activation signal WDA.
Change CT to active state.

That is, as is apparent from comparison with FIG. 9, in the operation shown in FIG.
It can be seen that the time delay from the rising edge of K to the activation of the word line activation signal is shorter than in the case of FIG.

Similarly, at time t2 ', general-purpose S
Signal / C provided from DRAM controller 103
S, signals / CAS and / WE are activated, and command decoder 125.1 issues signal int.
WRITE is activated.

On the other hand, at time t2 ', general-purpose SDRA
When an address signal is applied from M controller 103 to address decoder 125.2, address decoder 125.2 responds to this and internal decoder address signal int.
-Output DAdd.

At time t3, clock signal CLK
Is activated, the latch circuit 122.1 outputs the signal in.
t. In response to WRITE being active,
The internal control signal WRITE is activated. In response, column related timing control circuit 123.2 drives write driver activation signal WDE to an active state ("H" level).

On the other hand, the input synchronization latch circuit 122 receives the internal decode address signal int. In response to DAdd, a decoding operation is started at time t3, and a decode address Ca is output. Write data DataIN provided to latch circuit 122.2 from general-purpose SDRAM controller 103 is converted to internal write signal int-D in response to the activation edge of clock signal CLK at time t3, and is selected by decode address Ca. Is written in response to the activation of signal WDE.

At time t4 ', general-purpose SDR
The command decoder 125.
1 in response to signal / CS and signal / CAS applied to signal decoder 12 being active.
5.1 is the internal control signal int. READ is changed to the active state.

On the other hand, in response to address input Yb being applied to address decoder 125.2 at time t4 ', address decoder 125.2 outputs internal decode address int-DAdd.

At the activation edge of signal CLK at time t5, latch circuit 122.1 outputs signal int. R
Internal control signal R in response to EAD being active
Activate EAD. In response, column related timing control circuit 123.2 provides read amplifier activation signal PA
E is activated. In response to activation of signal PAE, internal read data int-Q is read from a memory cell column selected by decode address Cb output from latch circuit 122.1, and signal DataOUT is output from output synchronizing circuit 124.1. Is output as

As described above, in semiconductor integrated circuit device 1000 shown in FIG. 1, a general-purpose SDRAM control signal applied from a general-purpose SDRAM controller is first applied to command decoder circuit 125, and decoding operation in command decoder circuit 125 is performed. Is performed prior to the latch operation in input synchronization latch circuit 122, so that the operation margin increases in both the write operation and the read operation. In other words, it is possible to adapt to a higher speed operation.

[Second Embodiment] FIG. 12 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 2000 according to a second embodiment of the present invention.

Semiconductor integrated circuit device 200 shown in FIG.
0 corresponds to the semiconductor integrated circuit device 1000 shown in FIG.
The point different from the configuration is as follows.

First, in the semiconductor integrated circuit device 2000, an input switching circuit 730 is provided between the general-purpose SDRAM controller 103 and the first command decoder circuit 125.
Is provided, and input switching circuit 730 receives a signal from test command input terminal group 733 and a signal from general-purpose SDRAM controller 103, and receives switching signal input terminal 7
In response to the test input switching signal STC given from the control signal 36, one of the two is selected and given to the first command decoder circuit 125.

Further, in semiconductor integrated circuit device 2000, a signal supplied from test command input terminal group 734 or EDO-DRAM command input node 1
09 and the test input switching signal STC supplied to the switching signal input terminal 736
, An input switching circuit 731 to be provided to the second command decoder circuit 126 according to.

Further, in semiconductor integrated circuit device 2000, an input / output control circuit 732 is provided between general-purpose SDRAM controller 103, input synchronization latch circuit 122 and output circuit 124, and input / output control circuit 732 is provided.
Corresponds to a test data input / output terminal group 7 according to a test input switching signal STC given from a switching signal input terminal 736.
Test data or general-purpose SDRA
One of the input data supplied from the M controller 103 is selectively supplied to the input synchronization latch circuit 122.
Further, the input / output control circuit 732 outputs the data output from the output circuit 124 to the general-purpose SDR in accordance with the switching signal STC.
The signal is output to either the AM controller 103 or the test data input / output terminal group 735.

Since the other points are the same as those of semiconductor integrated circuit device 1000 shown in FIG. 1, the same portions are denoted by the same reference characters and description thereof will not be repeated.

Referring to FIG. 12, command input switching signal SCS is fixed at "H" level, and input select circuit 1
In 27, the setting is made so that the signal from the first command decoder circuit 125 is selectively supplied to the input synchronization latch circuit 122.

In the test operation, the test input switching signal is also fixed at "H" level, and input switching circuit 73
0 is set so that the signal from the test command input terminal group 733 is selectively supplied to the first command decoder circuit 125.

Therefore, during a test, a signal input from test command input terminal group 733 is supplied to input switching circuit 730, first command decoder circuit 125,
Input select circuit 127, input synchronization latch circuit 122
The signal is converted and supplied to the memory cell array 121 via the memory cell array control circuit 123.

Further, in the test operation, data is input from test data input / output terminal 735, applied to input / output latch circuit 122 through input / output control circuit 732 to memory cell array 121, and read from memory cell array 121. The input data is supplied from the output circuit 124 to the input / output control circuit 732, and is output from the test data input / output terminal 735.

With the above configuration, during the test operation period, it is possible to verify only the operation of the DRAM core 104 independently of the logic circuit 102 and the general-purpose SDRAM controller circuit 103.

FIG. 13 shows the input / output control circuit 732, the input synchronization latch circuit 122 and the output circuit 1 shown in FIG.
FIG. 24 is a schematic block diagram showing only a portion related to data input / output of the configuration in FIG. 24;

That is, the input / output control circuit 732 is supplied with 128-bit DataIN <127: 0> as input data from the general-purpose SDRAM controller 103, and is supplied to the memory cell array 121 via the input synchronization latch circuit 122.1. It is provided as internal write data int-D.

On the other hand, internal read data int-Q read from memory cell array 121 is supplied to input / output control circuit 7 through output synchronizing circuit 124.1 in output circuit 124.
32, and in a normal operation, the general-purpose S is output as 128-bit output data DataOUT <127: 0>.
It is provided to the DRAM controller 103.

On the other hand, the input / output control circuit 732 has a test input switching signal S
TC, an output selection signal DQAD <3: 0> and a test input signal TDI <7: 0> provided from a test data input / output terminal 735, and test read data from the input / output control circuit 732 during a test period. TDO <
7: 0> is applied to a test data input / output terminal 735.

FIG. 14 is a schematic block diagram for describing in more detail the configuration of input / output control circuit 732 shown in FIG.

An input / output control circuit 732 is controlled by a test input switching signal STC, and receives 16-bit data DataI supplied from the general-purpose SDRAM controller 103.
In response to N <15: 0> and test data TDI <0> provided from test data input / output terminal 735, input data DI <15: 0> is latched based on any of the data. Switching circuit 21 applied to
00.0. Other 16-bit data DataIN
<31:16> to DataIN <127: 112> and their corresponding test data TDI <1> to TDI
In response to DI <7>, DI switching circuits 2100.1 to D
An I switching circuit 2100.7 is provided.

DI switching circuits 2100.1 to 2100.7 are also controlled by test input switching signal STC, respectively, and input data DI <31:16> to DI <
127: 112> to the input synchronization latch circuit 122.

Further, input / output control circuit 732 receives read data DO <15: 0> from memory cell array 121, and transmits data selected by signal DQAD <3: 0> to test data input / output terminal 735. TDO <0>
Or read data DataOU
A DO selection circuit 2200.0 for providing T <15: 0> to the general-purpose SDRAM controller 103 is included.

Other 16-bit data DO <31:16
> To DO <127: 112>, the DO switching circuit 2
20.1 to DI switching circuit 2200.7 are provided.

DO switching circuit 2200.1 to DO switching circuit 2
200.7 also outputs the data selected by the signals DQAD <3: 0> to the test data input / output terminal 735 as the signals TDO <1> to TDO <7> or the read data DataOut <31: 16> ~ D
dataOut <127: 112> is given to the general-purpose SDRAM controller 103.

FIG. 15 is a circuit diagram of the DI switching circuit 2 shown in FIG.
It is a schematic block diagram for demonstrating the structure of 100.0.

DI switching circuit 2100.0 is controlled by test input / output switching signal STC, and outputs data TDI <0> from test data input / output terminal 735 and general-purpose SDRAM.
Receiving data DataIn <0> from controller 103, selects one and outputs as DI <0> 1
/ 2 selection circuit 2110.0.

DI switching circuit 2100.0 further has a configuration similar to that of 1/2 selection circuit 2110.0, corresponding to input data DataIn <1> to DataIn <15>. 1-2 selection circuit 2
110.15.

The other DI switching circuits 2100.1 to 2100.1-2
The configuration of 100.7 is basically the same as the DI switching circuit 2100.0.
The configuration is the same as that described above.

FIG. 16 is a circuit diagram for describing a configuration of 1/2 selection circuit 2110.0 shown in FIG.

The 1/2 selection circuit 2110.0 receives the data T
In response to DI <0>, driver circuit 2120 activated in response to test input switching signal STC, and inverter 21 receiving and inverting and outputting test input switching signal STC
22 is activated by the output of the inverter 2122 and receives the signal DataIN <0> to receive the data DI <0>.
And a driver circuit 2124 for outputting as>.

That is, when test input switching signal STC is active, the output from driver circuit 2120 is output as data DI <0>, and when the test input switching signal is inactive, the output from driver circuit 2124 is data DI <0>. Output as DI <0>.

FIG. 17 shows the structure of DO selection circuit 2 shown in FIG.
It is a schematic block diagram for demonstrating the structure of 200.0.

Referring to FIG. 17, DO selection circuit 220
0.0 is a signal DQSEL <1: 0 for receiving and decoding the signal DQAD <3: 0> and selecting output data.
5: 0> and 16-bit data DO <15: 0> of the output from the output synchronizing circuit 124.1 and receive a signal DQSEL <15: 0>.
1/16 selection circuit 2220 controlled by <1> and applied to test data input / output terminal 735 as signal TDO <0>
And

FIG. 18 shows the decoder circuit 2 shown in FIG.
FIG. 3 is a diagram for explaining a decoding operation of a decoding unit 210.

According to the value of 4-bit data DQAD <3: 0>, one of bit data of DQSEL <15: 0> is selectively activated ("H" level)
It is said.

FIG. 19 is a circuit diagram for describing a configuration of 1/16 selection circuit 2210 shown in FIG.

The 1/16 selection circuit 2210 outputs the data DO
Bit data DO <0> to D of <15: 0>
Driver circuit 2230.0 to 223 receiving O <15>
0.15. Driver circuit 2230.0-223
0.15 is activated in response to activation of each bit data of the signal DQSEL <15: 0>.

Driver circuits 2230.0 to 2230.1
5 is supplied to the test data input / output terminal 735 as test data TD0.

FIG. 20 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 2000 'according to the second embodiment of the present invention.

Semiconductor integrated circuit device 200 shown in FIG.
The configuration of the semiconductor integrated circuit device 20 shown in FIG.
The configuration differs from the configuration of FIG. 00 in that a logic circuit 502 is provided in place of the logic circuit 102, a general-purpose EDO-DRAM controller 503 is provided in place of the general-purpose SDRAM controller 103, and an output of the general-purpose EDO-DRAM controller 503 is provided. , An input switching circuit 731.

Since the other structure is the same as that of semiconductor integrated circuit device 2000 shown in FIG. 12, the same portions are denoted by the same reference characters and description thereof will not be repeated.

With the configuration shown in FIG. 20, DRA
It is not necessary to change the design data for the M core 104 at all, and this DRAM core 104 can be operated as a clock synchronous EDO-DRAM core. At this time, the circuit configuration of the clock synchronous EDO-DRAM controller 503 can be designed in advance corresponding to the EDO-DRAM core.
2 is a logic circuit designed to operate a general-purpose clock synchronous EDO-DRAM as a memory, the logic circuit portion and the DRAM controller portion are registered in advance as design libraries, respectively. With this arrangement, the configuration shown in FIG. 12 can be easily changed to the configuration shown in FIG.

[Third Embodiment] FIG. 21 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 3000 according to a third embodiment of the present invention.

Semiconductor Integrated Circuit Device 300 of Third Embodiment
0 is different from the configuration of the semiconductor integrated circuit device 2000 of the second embodiment shown in FIG.
Instead of deleting 30 and 731, a test control signal provided from test command input terminal group 733 is provided directly to input select circuit 827, and test input switching signal STC and command input switching signal SCS are provided. And an input / output path switching control circuit 830 for controlling the input select circuit 827 and the input / output control circuit 832 in accordance with the input / output control circuit 832. That is the point.

Here, the input / output control circuit 7 of the second embodiment
32 switches the data input / output path in response to the test input switching signal STC. However, the input / output control circuit 832 of the third embodiment has an input / output path switching control circuit 830 as described later. It operates in response to a selection signal SD from.

Since the other structure is the same as that of semiconductor integrated circuit device 2000 of the second embodiment, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 22 is a schematic block diagram for describing a configuration of input / output path switching control circuit and input select circuit 827 shown in FIG.

FIG. 22 specifically shows only a portion related to internal control signal ACT in the configuration of input select circuit 827. It is assumed that a similar configuration is provided for other internal control signals.

Switching signal decoder 3101 provided in input / output path switching control circuit 830 provides selection signals SA and S in accordance with the levels of the command switching signal and the test switching signal.
Output B, SC and SD.

The signal AC is provided in the input select circuit 827.
In response to T, a signal ACT_T supplied from the test command input terminal group 733 is received, a driver circuit 3111 activated by the signal SA, and a signal ACT_S supplied from the first command decoder circuit 125 are received. Driver circuit 3112 activated by SB
And a driver circuit 3113 which receives signal ACT_E provided from second command decoder circuit 126 and is activated by signal SC. Driver circuit 3111
3113 is supplied to the input synchronization latch circuit 122 as the internal control signal ACT.

FIG. 23 is a diagram illustrating the operation of switching signal decoder 3101 shown in FIG.

The levels of signals SA to SD are selectively activated according to the combination of the levels of the command switching signal and the test switching signal.

With the above configuration, during the test operation period, it is possible to verify only the operation of the DRAM core 104 independently of the logic circuit 102 and the general-purpose SDRAM controller circuit 103.

In addition, as in the second embodiment, with the configuration shown in FIG. 21, there is no need to change the design data for DRAM core 104 at all, and this DRA
The M core 104 can be operated as a clock synchronous EDO-DRAM core.

In the above description, the DRAM core 10
Four operation modes have been described, namely, a mode of operation with a general-purpose SDRAM control signal and a mode of operation with a general-purpose clock synchronous EDO-DRAM control signal. However, the present invention is limited to such a case. Instead, if only the command decoder circuit is replaced with another mode, any operation mode in which the DRAM core 104 can operate can be applied. Therefore, the operation mode does not need to be limited to two, and the design data of the DRAM core 104 can be shared for more operation modes.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0161]

According to the semiconductor integrated circuit device of the present invention, it is not necessary to change the design data for the memory circuit portion at all, and the memory circuit can be operated in any of a plurality of operation modes. Becomes At this time, the configuration of the control circuit corresponding to each operation mode can also be designed in advance corresponding to each operation mode, and the logic circuit portion and the control circuit are registered in advance as design libraries, respectively. This makes it possible to easily change the configuration from one operation mode to another operation mode.

In the semiconductor integrated circuit device according to the fifth to eighth aspects, in addition to the effect of the semiconductor integrated circuit device according to the first aspect, the semiconductor integrated circuit device is independent of the logic circuit and the control circuit.
Only the operation of the memory circuit can be verified.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 1000 according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a switching circuit 200.

FIG. 3 is a diagram showing correspondence between general-purpose SDRAM commands and internal control signals.

FIG. 4 is a timing chart for explaining an operation of the semiconductor integrated circuit device 1000 shown in FIG.

FIG. 5 is a schematic block diagram for describing a configuration of a semiconductor integrated circuit device 1000 ′.

FIG. 6 is a diagram showing contents of general-purpose commands of a clock synchronous EDO-DRAM and internal control signals corresponding thereto.

FIG. 7 is a semiconductor integrated circuit device 1000 ′ shown in FIG. 5;
3 is a timing chart for explaining the operation of FIG.

FIG. 8 is a schematic block diagram for explaining a path in which a control signal supplied from the outside is converted into an internal control signal in a one-chip general-purpose SDRAM and is supplied to a memory cell array 121.

FIG. 9 is a timing chart for explaining the operation of the one-chip SDRAM shown in FIG. 8;

FIG. 10 is a schematic block diagram showing a configuration of a portion of the configuration of the semiconductor integrated circuit device 1000 that operates according to a general-purpose SDRAM control signal.

11 is a timing chart for explaining the operation of the DRAM core 104 shown in FIG.

FIG. 12 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 2000 according to a second embodiment of the present invention.

FIG. 13 is a schematic block diagram showing only a portion related to data input / output;

14 is a schematic block diagram for describing a configuration of an input / output control circuit 732 shown in FIG. 13 in more detail.

FIG. 15 shows DI switching circuit 2100.0 shown in FIG.
FIG. 2 is a schematic block diagram for explaining the configuration of FIG.

FIG. 16 shows the 1/2 selection circuit 2110.
FIG. 3 is a circuit diagram for explaining a configuration of a zero.

17 is a diagram illustrating a DO selection circuit 2200.0 illustrated in FIG. 14;
FIG. 2 is a schematic block diagram for explaining the configuration of FIG.

18 is a diagram illustrating a decoding operation of the decoder circuit 2210 illustrated in FIG.

FIG. 19 is a 1/16 selection circuit 2210 shown in FIG.
FIG. 3 is a circuit diagram for explaining the configuration of FIG.

FIG. 20 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 2000 ′ according to a second embodiment of the present invention.

FIG. 21 is a schematic block diagram illustrating a configuration of a semiconductor integrated circuit device 3000 according to a third embodiment of the present invention.

FIG. 22 is a schematic block diagram illustrating a configuration of an input / output path switching control circuit and an input select circuit 827 shown in FIG. 21;

23 is a diagram for describing an operation of switching signal decoder 3101 shown in FIG.

FIG. 24 is a schematic block diagram showing a configuration of a conventional semiconductor integrated circuit device 8000.

FIG. 25 is a semiconductor integrated circuit device 800 shown in FIG. 24;
6 is a timing chart for explaining the operation of the "0".

[Explanation of symbols]

101 external terminal group, 102, 502 logic circuit, 10
3 General-purpose SDRAM controller, 104 DRAM core, 105 clock signal input terminal, 106 clock generation circuit, 108 input switching signal input terminal, 109 ED
ODRAM command input node, 121 memory cell array, 122 input synchronization latch circuit, 123 memory cell array control circuit, 124 output circuit, 125 first
Command decoder circuit, 126 second command decoder circuit, 127 input select circuit, 503 clock synchronous EDODRAM controller, 1000, 100
0 ', 2000,2000', 3000 Semiconductor integrated circuit device.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toshiaki Kawasaki 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference) 2G032 AA01 AA07 AB01 AG02 AG07 AH04 AK14 5B024 AA15 BA21 BA29 CA07 EA04 5L106 AA01 DD11 GG05 GG07

Claims (8)

[Claims] 1. A semiconductor integrated circuit device, which performs arithmetic processing on data in accordance with externally supplied data and a control signal, and corresponds to one of a plurality of operation modes. A logic circuit for generating a control signal, a control circuit for receiving a control signal from the logic circuit, and generating a memory control signal group having a plurality of memory control signals, and storing data between the logic circuit. A memory circuit for transmitting and receiving, and storing the storage data, the memory circuit comprising: a memory cell array having a plurality of memory cells for storing the storage data; and a plurality of memory cells respectively corresponding to the plurality of operation modes. A plurality of control signal input nodes capable of receiving the memory control signal group of A plurality of decode circuits provided correspondingly, for decoding a memory control signal group applied to a corresponding control signal input node group, and generating an internal control signal for the memory cell array; A wiring for transmitting the memory control signal group to one control signal input node group of the plurality of control signal input node groups. 2. The memory circuit according to claim 2, further comprising a selection circuit for selecting said internal control signal from a designated one of said plurality of decoding circuits in response to an external instruction. 2. The semiconductor integrated circuit device according to 1. 3. The semiconductor integrated circuit device further includes a clock generation circuit for generating an internal clock signal based on an external clock signal, wherein the memory circuit transmits the internal control signal from the selection circuit to the internal circuit. A latch circuit that holds in synchronization with a clock signal; and a memory cell array control circuit that generates a memory cell array control signal for controlling an operation of selecting the memory cell in the memory cell array in accordance with an output from the latch circuit. 3. The semiconductor integrated circuit device according to claim 2, further comprising: 4. The semiconductor integrated circuit device according to claim 3, wherein the plurality of operation modes include an operation mode as a synchronous dynamic semiconductor memory device and an operation mode as a clock synchronous EDO-dynamic semiconductor memory device. . 5. The memory circuit is provided corresponding to each of the plurality of decode circuits.
A plurality of test signal input terminal groups for receiving a test control signal; and a plurality of test signal input terminal groups provided between the plurality of control signal input node groups and the plurality of decode circuits; and a signal from the plurality of control signal input node groups. A plurality of switching circuits for receiving signals from the plurality of test signal input terminal groups and providing one of them to the plurality of decoding circuits in response to an external instruction; and A selecting circuit for selecting the internal control signal from a designated decoding circuit among the plurality of decoding circuits, a plurality of test data input / output terminals for transmitting / receiving data to / from the outside, In the operation mode, further includes an input / output control circuit for controlling data transmission between the memory cell array and the plurality of test data input / output terminals, Claim 1
13. The semiconductor integrated circuit device according to claim 1. 6. The memory circuit includes: a test signal input terminal group for receiving a test control signal; and an internal control signal from the plurality of decode circuits and the test signal input terminal group in response to an external instruction. And a plurality of test data input / output terminals for exchanging data with the outside, and a memory cell array and a plurality of test data input / output terminals in a test operation mode. 2. The input / output control circuit for controlling data transmission to / from a test data input / output terminal.
13. The semiconductor integrated circuit device according to claim 1. 7. The semiconductor integrated circuit device further includes a clock generation circuit for generating an internal clock signal based on an external clock signal, and the memory circuit transmits the internal control signal from the selection circuit to the internal circuit. A latch circuit that holds in synchronization with a clock signal; and a memory cell array control circuit that generates a memory cell array control signal for controlling an operation of selecting the memory cell in the memory cell array in accordance with an output from the latch circuit. 7. The semiconductor integrated circuit device according to claim 5, further comprising: 8. The semiconductor integrated circuit device according to claim 7, wherein the plurality of operation modes include an operation mode as a synchronous dynamic semiconductor memory device and an operation mode as a clock synchronous EDO-dynamic semiconductor memory device. .