CN110910923A - Word line decoding method and nonvolatile memory system - Google Patents
Word line decoding method and nonvolatile memory system Download PDFInfo
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- CN110910923A CN110910923A CN201811076862.7A CN201811076862A CN110910923A CN 110910923 A CN110910923 A CN 110910923A CN 201811076862 A CN201811076862 A CN 201811076862A CN 110910923 A CN110910923 A CN 110910923A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Abstract
The embodiment of the invention provides a word line decoding method and a nonvolatile memory system, wherein the method comprises the following steps: receiving source address information through the address data input module; determining a target latch address in the data latch module according to the decoding of the address decoding module on the source address information; receiving, by the address data input module, word line selection data; and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address. The embodiment of the invention can flexibly set the word line selection data according to the requirement, and further realizes convenient and flexible selection of the word line in the block through the word line selection data.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a word line decoding method and a nonvolatile memory system.
Background
In a nonvolatile memory system, a read operation, an erase operation, a program operation, or the like is required by decoding a word line.
In the prior art, during a read operation, it is common practice to select one wordline by full decoding with an N-bit address (the value of N depends on how many wordlines there are). During erasing or writing operation, the decoding of the word line generally selects a word line according to the decoding mode of the read operation, or selects all word lines in a certain block (memory block) for erasing or writing operation by certain setting (such as certain address of N-bit address is set to be constantly equal to 1) in the decoding process.
However, the applicant finds that the decoding method in the prior art is effective for selecting one word line or all word lines in a block, but a complicated decoding circuit is required, for example, one of 8192 word lines is selected through a 13-bit address, and a large decoding circuit is required for selecting according to the conventional decoding method, which wastes area and is not high in decoding efficiency. If a block or a plurality of word lines of the whole memory are randomly selected, the traditional decoding mode is difficult to realize.
Disclosure of Invention
In view of the above problems, a word line decoding method and a non-volatile memory system according to embodiments of the present invention are provided to solve the above problems of high difficulty and insufficient flexibility in word line decoding.
According to a first aspect of the present invention, there is provided a word line decoding method applied to a nonvolatile memory system, the nonvolatile memory system including: the device comprises an address data input module, an address decoding module and a data latch module, wherein at least one latch address is arranged in the data latch module, and each latch address corresponds to a storage block;
the method comprises the following steps:
receiving source address information through the address data input module;
after the address decoding module decodes the source address information, a target latch address is determined in at least one latch address of the data latch module;
receiving, by the address data input module, word line selection data;
and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address.
According to a second aspect of the present invention, there is provided a nonvolatile memory system including:
the device comprises an address data input module, an address decoding module, a data latch module, a determining module and a setting module, wherein at least one latch address is arranged in the data latch module, and each latch address corresponds to a storage block;
the address data input module is used for receiving source address information;
the determining module is configured to determine a target latch address from at least one latch address of the data latch module according to the decoding of the source address information by the address decoding module;
the address data input module is also used for receiving word line selection data;
the setting module is used for setting the word line selection data at the target latch address so as to realize the word line selection of the block corresponding to the target latch address.
In the embodiment of the invention, source address information is received through an address data input module; determining a target latch address in the data latch module according to the decoding of the source address information; receiving word line selection data through an address data input module; and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address. In the embodiment of the invention, the word line selection data can be flexibly set according to requirements, and the word line can be conveniently and flexibly selected in the block through the word line selection data.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flowchart of a word line decoding method according to an embodiment of the present invention;
FIG. 2 is a block diagram of a non-volatile memory system according to an embodiment of the present invention;
FIG. 3 is a block diagram of a non-volatile memory system provided by an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 1, there is shown a flow chart of a wordline decoding method that may be applied in a non-volatile memory system comprising: the memory comprises an address data input module, an address decoding module and a data latch module, wherein at least one latch address is arranged in the data latch module, and each latch address corresponds to one memory block.
In the embodiment of the present invention, as shown in fig. 2, a schematic structural diagram of a nonvolatile memory system is shown, which includes an address Data input module (Addr and Data input block)210, an address decoding module (Addr Decoder)220, and a Data Latch module (Data Latch) 230. The address data INPUT module 210 receives address information and data information mainly through the INPUT port INPUT. The address decoding module (Addr Decoder) is responsible for inputting the address A<n-1:0>The corresponding Latch unit (Latch) can be selected to be enabled by the fully decoded address information. In a specific application, preferably, when the source address information includes an n-bit input address, the source address information may include at least 2 bits in the data latch modulenA set of latches obtained by fully decoding n-bit input addresses, n being a natural number, each set of latches representing a Block of memory (Block), the memory then comprising 2nAnd each Block. Each set of Latch stores m bit data (e.g., LAT 0)<m:0>Corresponding to m +1 word lines), m is 0, 1, 2 … …, and includes (m +1) × 2nData information (WL)<r:0>). Each 1bit of data in each set Latch represents a wordline, a bit of data of 1 indicating that the wordline is selected and a data of 0 indicating that the wordline is not selected.
The method specifically comprises the following steps:
step 101: and receiving source address information through the address data input module.
In an embodiment of the present invention, the address data input module may be configured to receive address information and word line selection data; the source address information may be denoted as A < n-1:0 >.
In specific application, when word line decoding is needed, source address information is received through an address data input module, and blocks needing word line selection can be determined through the source address information.
Step 102: and after the source address information is decoded by the address decoding module, determining a target latch address in at least one latch address of the data latch module.
In the embodiment of the invention, the address decoding module can fully decode the source address information A < n-1:0>, the source address information A < n-1:0> can be matched with the Latch address in the data Latch module after being fully decoded, the matched Latch address is determined as the target Latch address, and the Latch enable of the target Latch address is effective.
Step 103: word line selection data is received by the address data input module.
In the embodiment of the invention, after the target latch address is determined, the address data input module receives word line selection data. Each set of word line selection Data may be represented as Data < m:0>, m being 0, 1, 2 … …, with (m +1) bits.
Step 104: and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address.
In the embodiment of the present invention, after receiving the word line selection data, the word line selection data may be loaded to Latch of the target Latch address, preferably, the (m +1) bit word line selection data includes 0 data and/or 1 data, a bit corresponding to data 1 corresponds to a word line to be selected, and a data bit corresponding to 0 corresponds to an unselected word line. In the block corresponding to the target latch address, the word line corresponding to the 0 data in the word line selection data may be set to an unselected state, and/or the word line corresponding to the 1 data in the word line selection data may be set to a selected state.
In the embodiment of the invention, as the (m +1) bit word line selection data can correspondingly set some bit bits as 1 and some bit bits as 0 according to the actual word line selection requirement, the corresponding word line can be flexibly selected. For example, at address 0, the corresponding Latch load 12bit count, LAT0<11:0> -011000100010, selects word lines WL <10>, WL <9>, WL <5>, WL <1 >.
In specific application, if any word line in all blocks needs to be selected, the address data input module can input the nbit address A<n-1:0>000000, INPUT port INPUTs 2 in sequencenA set of word line selection data, each set of word line selection data representing the set of LATs<m:0>DATA to be loaded, each set of DATA DATA<m:0>Bit of 1, namely the LAT<m:0>The method can select any word line in any Block according to the selected word line in the corresponding Block.
As a preferred implementation manner of the embodiment of the present invention, before step 101, the method may further include: and resetting at least one latch address in the data latch module.
In a specific application, before the word line starts to decode, all Latch data may be cleared by a Reset setting (Reset), that is, the word line of the block corresponding to the Latch address is in an unselected state by the Reset. Therefore, the interference of the previous Latch data on the decoding is avoided during the subsequent decoding.
In the embodiment of the invention, source address information is received through an address data input module; determining a target latch address in the data latch module according to the decoding of the source address information; receiving word line selection data through an address data input module; and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address. In the embodiment of the invention, the word line selection data can be flexibly set according to requirements, and the word line can be conveniently and flexibly selected in the block through the word line selection data.
Example two
Referring to FIG. 3, a block diagram of a non-volatile memory system is shown that may include, in particular:
the memory comprises an address data input module 310, an address decoding module 320, a data latch module 340, a determining module 330 and a setting module 350, wherein at least one latch address is arranged in the data latch module 340, and each latch address corresponds to one memory block;
the address data input module 310 is configured to receive source address information;
the determining module 330 is configured to determine a target latch address from at least one latch address of the data latch module 340 after decoding the source address information according to the address decoding module 320;
the address data input module 310 is further configured to receive word line selection data;
the setting module 350 is configured to set the word line selection data at the target latch address, so as to implement word line selection of block corresponding to the target latch address.
Preferably, the method further comprises the following steps:
and the reset module is used for resetting at least one latch address in the data latch module.
Preferably, the reset module includes:
and the reset submodule is used for setting the word line of the block corresponding to the at least one latch address to be in an unselected state.
Preferably, the word line selection data includes 0 data, and/or, 1 data; the setting module includes:
a first setting submodule for setting the word line selection data at the target latch address;
and the second setting submodule is used for setting the word line corresponding to the 0 data in the word line selection data to be in an unselected state and/or setting the word line corresponding to the 1 data in the word line selection data to be in a selected state in the block corresponding to the target latch address.
Preferably, the source address information comprises an n-bit input address, and at least 2 are provided in the data latch modulenAnd n is a natural number.
In the embodiment of the invention, source address information is received through an address data input module; determining a target latch address in the data latch module according to the decoding of the source address information; receiving word line selection data through an address data input module; and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address. In the embodiment of the invention, the word line selection data can be flexibly set according to requirements, and the word line can be conveniently and flexibly selected in the block through the word line selection data.
For the embodiment of the nonvolatile memory system, since it is basically similar to the embodiment of the method, the description is simple, and for the relevant points, refer to the partial description of the embodiment of the method.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It should be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, non-volatile memory system, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), electrically-processable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (fransitory media), such as modulated data signals and carrier waves.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable word line decoding end device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable word line decoding end device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable word line decoding terminal device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction non-volatile memory system which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable word line decoding terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The word line decoding method and the nonvolatile memory system provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A word line decoding method is applied to a nonvolatile memory system, and the nonvolatile memory system comprises the following steps: the device comprises an address data input module, an address decoding module and a data latch module, wherein at least one latch address is arranged in the data latch module, and each latch address corresponds to a storage block;
the method comprises the following steps:
receiving source address information through the address data input module;
after the address decoding module decodes the source address information, a target latch address is determined in at least one latch address of the data latch module;
receiving, by the address data input module, word line selection data;
and setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address.
2. The method of claim 1, wherein before receiving source address information via the address data input module, further comprising:
and resetting at least one latch address in the data latch module.
3. The method of claim 2, wherein said resetting at least one latch address in said data latch module comprises:
and setting the word line of the block corresponding to the at least one latch address to be in an unselected state.
4. The method of claim 1, wherein the word line selection data comprises 0 data, and/or, 1 data; the setting the word line selection data at the target latch address to realize the word line selection of the block corresponding to the target latch address includes:
setting the word line selection data at the target latch address;
and in the block corresponding to the target latch address, setting the word line corresponding to the data 0 in the word line selection data to be in an unselected state, and/or setting the word line corresponding to the data 1 in the word line selection data to be in a selected state.
5. The method of any of claims 1-4, wherein the source address information comprises an n-bit input address, and wherein at least 2 bits are provided in the data latch modulenAnd n is a natural number.
6. A non-volatile memory system, the non-volatile memory system comprising: the device comprises an address data input module, an address decoding module, a data latch module, a determining module and a setting module, wherein at least one latch address is arranged in the data latch module, and each latch address corresponds to a storage block;
the address data input module is used for receiving source address information;
the determining module is configured to determine a target latch address from at least one latch address of the data latch module after the address decoding module decodes the source address information;
the address data input module is also used for receiving word line selection data;
the setting module is used for setting the word line selection data at the target latch address so as to realize the word line selection of the block corresponding to the target latch address.
7. The non-volatile memory system of claim 6, further comprising:
and the reset module is used for resetting at least one latch address in the data latch module.
8. The non-volatile memory system of claim 7, wherein the reset module comprises:
and the reset submodule is used for setting the word line of the block corresponding to the at least one latch address to be in an unselected state.
9. The nonvolatile memory system according to claim 6, wherein the word line selection data includes 0 data, and/or 1 data; the setting module includes:
a first setting submodule for setting the word line selection data at the target latch address;
and the second setting submodule is used for setting the word line corresponding to the 0 data in the word line selection data to be in an unselected state and/or setting the word line corresponding to the 1 data in the word line selection data to be in a selected state in the block corresponding to the target latch address.
10. The non-volatile memory system of any of claims 6-9, wherein the source address information comprises an n-bit input address, and wherein at least 2 bits are provided in the data latch modulenAnd n is a natural number.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1503272A (en) * | 2002-11-19 | 2004-06-09 | 三星电子株式会社 | Circuit and method for changing page length in semiconductor memory |
| CN101154456A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | Flash memory device and erase method using the same |
| CN101432818A (en) * | 2006-04-28 | 2009-05-13 | 莫塞德技术公司 | Dynamic random access memory with fully independent partial array refresh function |
| CN101636790A (en) * | 2007-02-27 | 2010-01-27 | 莫塞德技术公司 | Decoding control with address transition detection in page erase function |
| US20110085405A1 (en) * | 2003-12-29 | 2011-04-14 | Sang-Hoon Hong | Semiconductor memory device having advanced tag block |
| CN103489472A (en) * | 2012-06-08 | 2014-01-01 | 飞思卡尔半导体公司 | Clocked memory with latching predecoder circuitry |
| US20150043293A1 (en) * | 2013-08-09 | 2015-02-12 | SK Hynix Inc. | Semiconductor memory device |
-
2018
- 2018-09-14 CN CN201811076862.7A patent/CN110910923A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1503272A (en) * | 2002-11-19 | 2004-06-09 | 三星电子株式会社 | Circuit and method for changing page length in semiconductor memory |
| US20110085405A1 (en) * | 2003-12-29 | 2011-04-14 | Sang-Hoon Hong | Semiconductor memory device having advanced tag block |
| CN101432818A (en) * | 2006-04-28 | 2009-05-13 | 莫塞德技术公司 | Dynamic random access memory with fully independent partial array refresh function |
| CN101154456A (en) * | 2006-09-29 | 2008-04-02 | 海力士半导体有限公司 | Flash memory device and erase method using the same |
| CN101636790A (en) * | 2007-02-27 | 2010-01-27 | 莫塞德技术公司 | Decoding control with address transition detection in page erase function |
| CN103489472A (en) * | 2012-06-08 | 2014-01-01 | 飞思卡尔半导体公司 | Clocked memory with latching predecoder circuitry |
| US20150043293A1 (en) * | 2013-08-09 | 2015-02-12 | SK Hynix Inc. | Semiconductor memory device |
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Application publication date: 20200324 |