CN111951860B - Nonvolatile memory write processing method and device - Google Patents
Nonvolatile memory write processing method and device Download PDFInfo
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- CN111951860B CN111951860B CN201910402323.6A CN201910402323A CN111951860B CN 111951860 B CN111951860 B CN 111951860B CN 201910402323 A CN201910402323 A CN 201910402323A CN 111951860 B CN111951860 B CN 111951860B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
Abstract
The embodiment of the invention provides a method and a device for writing processing of a nonvolatile memory, wherein the method comprises the following steps: determining a target programming word line of a memory block to be processed when the memory block to be processed executes a write operation; determining a program voltage compensation amount of the target program word line; applying a first programming voltage to the target programming word line; the first programming voltage is: presetting the difference between a programming voltage and the compensation quantity of the programming voltage; applying a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment. The distribution of the VT0 in the embodiment of the present invention is similar to the distribution of the VT1, so that a logic error caused by an excessively large difference between the turn-on threshold voltages of the VT0 and other word lines is avoided, and further, a phenomenon that the written data in the initial word line WL0 cannot be correctly read can be avoided.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for processing a write in a nonvolatile memory.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices have been developed. For example, a non-volatile Memory NAND Flash Memory (NAND Flash Memory) is taken as an example, the NAND Flash Memory stores data by performing read-write operation on a Memory cell (Memory cell), has the advantages of high rewriting speed, large storage capacity and the like, and is widely used in electronic products. In each Block of the nonvolatile memory, there are a plurality of WL (Word line) s.
In the prior art, when writing to the NAND flash memory, a conventional initial programming voltage is usually applied to each selected WL to be programmed, and then the initial programming voltage is increased continuously until the writing to the WL is realized. For example, as shown in fig. 1, a larger programming voltage VPGM _ INI is applied to WL0, and if the write operation is not completed, a voltage of VPGM _ INI plus VPGM _ STEP is applied to WL0, where VPGM _ STEP is a STEP voltage increment, and if the write operation is not completed, a voltage of VPGM _ INI plus two VPGM _ STEPs is applied to WL0, and so on, thereby implementing the write operation.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: in the write operation, a phenomenon often occurs in the initial word line WL0 that the written data cannot be correctly read.
Disclosure of Invention
In view of the above problems, a method and an apparatus for processing writing in a nonvolatile memory according to embodiments of the present invention are provided to avoid the phenomenon that the written data in the initial word line WL0 cannot be correctly read.
According to a first aspect of the present invention, there is provided a non-volatile memory write processing method, the method comprising:
when a write operation is executed on a memory block to be processed, determining a target programming word line of the memory block to be processed;
determining a program voltage compensation amount of the target program word line;
applying a first programming voltage to the target programming word line; the first programming voltage is: presetting the difference between a programming voltage and the compensation quantity of the programming voltage; applying a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment.
Optionally, when performing a write operation on the memory block to be processed, before determining a target programming word line of the memory block to be processed, the method further includes:
and determining the program voltage compensation amount corresponding to each word line in the memory block to be processed.
Optionally, in a case that the target programming word line does not complete the write operation, applying a second programming voltage to the target programming word line; the second programming voltage is: after the summation of the first programming voltage and the first preset voltage increment, the method further comprises:
applying a third programming voltage to the target programming word line if the target programming word line does not complete the write operation; the third programming voltage is: a sum of the second programming voltage and a first preset voltage increment.
Optionally, in a case that the target programming word line does not complete the write operation, applying a second programming voltage to the target programming word line; the second programming voltage is: after the sum of the first programming voltage and the first preset voltage increment, the method further comprises:
applying a fourth programming voltage to the target programming word line if the target programming word line does not complete the write operation; the fourth programming voltage is: a sum of the second programming voltage and a second preset voltage increment, wherein the first preset voltage increment is not equal to the second preset voltage increment.
Optionally, the to-be-processed storage block includes: 64 word lines WL, the 64 word lines being the word lines ordered from WL0 to WL 63.
According to a second aspect of the present invention, there is provided a nonvolatile memory write processing apparatus, the apparatus comprising:
the target programming word line determining module is used for determining a target programming word line of a storage block to be processed when the write operation is executed on the storage block to be processed;
a program voltage compensation amount determination module for determining a program voltage compensation amount of the target program word line;
a first voltage applying module for applying a first programming voltage to the target programming word line; the first programming voltage is: presetting a difference between a programming voltage and the compensation quantity of the programming voltage;
a second voltage applying module, configured to apply a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment.
Optionally, the method further includes:
and the determining module is used for determining the program voltage compensation amount corresponding to each word line in the memory block to be processed.
Optionally, the method further includes:
a third voltage applying module, configured to apply a third programming voltage to the target programming word line if the target programming word line does not complete the write operation; the third programming voltage is: a sum of the second programming voltage and a first preset voltage increment.
Optionally, the method further includes:
a fourth voltage applying module for applying a fourth programming voltage to the target programming word line if the target programming word line does not complete the write operation; the fourth programming voltage is: a sum of the second programming voltage and a second preset voltage increment, wherein the first preset voltage increment is not equal to the second preset voltage increment.
Optionally, the to-be-processed storage block includes: 64 word lines WL, the 64 word lines being the word lines ordered from WL0 to WL 63.
In the embodiment of the present invention, it is found that the reason why the written data in the initial word line WL0 in the prior art cannot be correctly read is: in three consecutive word lines, the middle word line is subjected to capacitive coupling action (couple effect) of the two word lines, so that the conduction threshold voltage of the middle word line is increased, only one side of the initial word line WL0 is provided with the word line, so that the capacitive coupling action on the WL0 is weaker, and the distribution of the conduction threshold voltage VT0 of the WL0 is also different from that of the other word lines, for example, when a higher programming voltage is applied to the WL0, the WL1 can obtain a narrower conduction threshold voltage VT1 distribution curve based on the capacitive coupling action on the WL0 and the WL2, and the WL0 is only subjected to the action of the WL1, so that the VT0 distribution of the WL0 is more different from that of the WL1, and the conduction threshold voltage of the WL0 is greater than that of the WL1 after being read for a certain number of times, therefore, when data written in the WL0 is read, the WL0 should be in a conduction logic, but cannot be conducted because the VT0 is greater, and the written data cannot be correctly read. Therefore, when the nonvolatile memory is read, a target programming word line is determined in a memory block to be processed, the programming voltage compensation amount of the target programming word line is determined, and a first programming voltage is applied to the target programming word line initially; and the first programming voltage is: the difference between the preset programming voltage and the compensation amount of the programming voltage, that is, the first programming voltage is obtained by subtracting the compensation amount of the programming voltage of the target programming word line from the preset programming voltage, and the preset programming voltage is smaller, so that in the couple effect of the VT1, the VT0 has a smaller effect, so that the couple effect of the VT1 is close to the couple effect of the VT0, and further the distribution of the VT0 is similar to the distribution of the VT1, thereby avoiding a logic error caused by an excessively large difference between the turn-on threshold voltages of the VT0 and other word lines, and further avoiding the phenomenon that the written data in the initial word line WL0 cannot be correctly read. It can be understood that, in a write operation, it is usually necessary to apply a program voltage for many times to complete all the write operations, and therefore, in a case where the write operation is not completed on the target program word line, a second program voltage is applied to the target program word line; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment; the write operation may be completed after multiple applications of incrementally increasing programming voltages.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a prior art non-volatile memory write process voltage application;
FIG. 2 is a flow chart of a method for processing a write to a non-volatile memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the application of the write processing voltage to the nonvolatile memory according to an embodiment of the present invention;
fig. 4 is a block diagram of a nonvolatile memory write processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, are only a few examples of the invention, are not intended to limit the invention.
Example one
Referring to FIG. 2, a flow chart of a non-volatile memory write processing method is shown.
In the embodiment of the present invention, after a great deal of research, the inventor finds that, among three consecutive word lines, the middle word line may be subjected to capacitive coupling action (couple effect) of the word lines on both sides, so that the conduction threshold voltage of the middle word line is increased, while only one side of the initial word line WL0 has the word line, so that the capacitive coupling action on WL0 is weak, and the distribution of the conduction threshold voltage VT0 of WL0 is also different from that of the other word lines, for example, when a higher program voltage is applied to WL0, WL1 may obtain a narrower conduction threshold voltage VT1 distribution curve based on the capacitive coupling action of WL0 and WL2, and WL0 is only subjected to the action of WL1, so that when the VT0 distribution of WL0 is far from that of WL1, and the conduction threshold voltage of WL0 is greater than that of WL1 after being read for a certain number of times, therefore, when data written in WL0 is read, WL0 should be in a conduction logic, but VT0 is not turned on, and thus the written data cannot be correctly read.
Aiming at the discovery, when the nonvolatile memory is read, the embodiment of the invention determines a target programming word line in a memory block to be processed, determines the programming voltage compensation amount of the target programming word line, and applies a first programming voltage to the target programming word line at the beginning; and the first programming voltage is: the difference between the preset programming voltage and the compensation amount of the programming voltage, that is, the first programming voltage is obtained by subtracting the compensation amount of the programming voltage of the target programming word line from the preset programming voltage, and the preset programming voltage is smaller, so that in the couple effect of the VT1, the VT0 has a smaller effect, so that the couple effect of the VT1 is close to the couple effect of the VT0, and further the distribution of the VT0 is similar to the distribution of the VT1, thereby avoiding a logic error caused by an excessively large difference between the turn-on threshold voltages of the VT0 and other word lines, and further avoiding the phenomenon that the written data in the initial word line WL0 cannot be correctly read. It can be understood that, in a write operation, it is usually necessary to apply a program voltage for many times to complete all the write operations, and therefore, in a case where the write operation is not completed on the target program word line, a second program voltage is applied to the target program word line; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment; the write operation may be completed after multiple applications of the incremental programming voltage. Specifically, the steps 101 to 104.
Step 101: when a write operation is executed on a memory block to be processed, a target programming word line of the memory block to be processed is determined.
When the write operation is executed on the to-be-stored block in the embodiment of the invention, the target programming word line can be jacked in the to-be-stored block according to the word line address corresponding to the write operation instruction.
Step 102: a program voltage compensation amount for the target program word line is determined.
In the embodiment of the invention, the coding voltage compensation amount can be obtained by testing the conduction threshold voltage distribution of each word line in advance according to practical application, the mapping relation between each word line and the corresponding coding voltage compensation amount can be stored in a register, and the programming voltage compensation amount of the target programming word line can be directly read in the register after the target programming word line is determined. Illustratively, taking 64 word lines as the word lines ordered from WL0 to WL63 as an example, WL0 and WL63 are edge word lines of the 64 word lines, WL0 and WL63 are subjected to a couple effect different from that of WL1 to WL62, in practical application, the program voltage compensation amount of WL0 and WL63 may be higher than that of WL1 to WL62, and the program voltage compensation amount of WL0 and WL63 may be any value from 2 to 3.
In a specific application, the target encoding word line may be an edge word line (WL 0 and WL 63) or an intermediate word line (WL 1 to WL 62), and the corresponding program voltage compensation amount can be determined regardless of which word line the target encoding word line is.
In a specific application, the mode of determining the compensation amount of the program voltage corresponding to each word line in the memory block to be processed may be: respectively determining the conduction threshold voltage distribution of each word line, then setting the programming voltage compensation quantity of the word line (edge word line) with wider conduction threshold voltage distribution as a higher value, and setting the programming voltage compensation quantity of the word line (middle word line) with narrower conduction threshold voltage distribution as a lower value; it can be understood that, according to the specific situation of the conduction threshold distribution, a corresponding relationship between the conduction threshold distribution and the coding voltage compensation amount may be established, which is not specifically limited in the embodiment of the present invention.
Step 103: applying a first programming voltage to the target programming word line; the first programming voltage is: presetting the difference between the programming voltage and the compensation quantity of the programming voltage.
In an embodiment of the present invention, a first programming voltage is first applied to a target programming word line. The first programming voltage is a difference between the preset programming voltage and the compensation amount of the programming voltage, and it can be understood that the preset programming voltage may be an initial programming voltage conventionally used in the prior art.
For example, as shown in FIG. 3, the first programming voltage applied on WL0 can be a voltage that is smaller than the programming voltage of the prior art by VPGM _ WL0/1/126/127 \/OFFSET (programming voltage offset), i.e., the first programming voltage is: VPGM _ INI-VPGM _ WL 0/1/126/127/u OFFSET.
In a specific application, the first programming voltage is a smaller voltage, so that the effect of VT0 is smaller in the cascade effect of VT1, so that the cascade effect of VT1 is close to the cascade effect of VT0, and further the distribution of VT0 is similar to the distribution of VT1, thereby avoiding a logic error caused by an excessively large difference between the turn-on threshold voltages of VT0 and other word lines, and further avoiding a phenomenon that the written data in the initial word line WL0 cannot be correctly read.
Step 104: applying a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment.
In a specific application, because the nonvolatile memory may only complete a part of the write operation and not complete the entire write operation after applying the one-time programming voltage when performing the programming, it is necessary to increase the programming voltage and continue the write operation when the target programming word line does not complete the write operation, for example, as shown in fig. 3, taking the target programming word line as WL0, first applying a smaller first programming voltage VPGM _ INII-VPGM _ WL0/1/126/127 \/offset to WL0, if the write operation is not completed, further applying a voltage VPGM _ intii minus VPGM _ WL0/1/126/127 \/offset to WL0, and then adding a voltage of VPGM _ STEP, wherein VPGM _ STEP is a STEP voltage increment, and if the write operation is not completed, further applying a voltage of VPGM _ INII minus VPGM _ WL0/1/126/127 \, then adding two voltages of VPGM _ STEP, and so on WL0, and so on the like, thereby completing the write operation.
As a specific implementation manner of the embodiment of the present invention, the method further includes:
substep A1 (not shown in the figures): applying a third programming voltage to the target programming word line if the target programming word line does not complete the write operation; the third programming voltage is: a sum of the second programming voltage and a first preset voltage increment.
In an embodiment of the present invention, the program voltage applied to the target program word line may be: the first programming voltage is stepped up by a first predetermined voltage increment from the start of the first programming voltage, so that only a single first predetermined voltage increment needs to be set to sequentially perform the above-described writing operation.
For example, as shown in fig. 3, the to-be-processed memory block includes: 64 word lines WL, the 64 word lines being word lines ordered from WL0 to WL63, the initial word line comprising: WL0. Taking the target programming word line as WL0 for example, first a smaller first programming voltage VPGM _ INII-VPGM _ WL0/1/126/127 \/OFFSET is applied to WL0, if the write operation is not completed, VPGM _ INII minus VPGM _ WL0/1/126/127 \/OFFSET is further applied to WL0, then the voltage of VPGM _ STEP is added, wherein VPGM _ STEP is a STEP voltage increment, if the write operation is not completed, VPGM _ INII minus VPGM _ WL0/1/126/127 u \/OFFSET is further applied to WL0, then the voltages of two VPGM _ STEPs are added, and so on, thereby completing the write operation.
As another specific implementation manner of the embodiment of the present invention, the method further includes:
substep B1 (not shown in the figures): applying a fourth programming voltage to the target programming word line if the target programming word line does not complete the write operation; the fourth programming voltage is: a sum of the second programming voltage and a second predetermined voltage increment, wherein the first predetermined voltage increment and the second predetermined voltage increment are not equal.
In the embodiment of the present invention, the sub-step B1 may be two schemes in parallel with the sub-step A1.
By sub-step B1, it is achieved that the voltage increment of each step is different when the programming voltage is stepped up from the first programming voltage, so that it is flexible to apply the programming voltage each time.
It is to be understood that the value of the second preset voltage increment may be set by a person skilled in the art according to an actual application scenario, and the embodiment of the present invention is not limited in this respect.
In practical applications, a person skilled in the art may also set a third preset voltage increment, a fourth preset voltage increment, and the like according to actual requirements to achieve flexible increase of the programming voltage, which is not specifically limited in the embodiment of the present invention.
In a specific operation, the preset voltage increment may be set by modifying a value of a register for setting each voltage increment, or may be set in other manners, which is not specifically limited in the example of the present invention.
In summary, in the embodiment of the present invention, it is found that the reason why the written data in the initial word line WL0 cannot be correctly read in the prior art is: in three continuous word lines, the middle word line is subjected to capacitive coupling action (couple effect) of the word lines on two sides, so that the conduction threshold voltage of the middle word line is increased, while only one side of the initial word line WL0 is provided with the word line, so that the capacitive coupling action on the WL0 is weaker, and the distribution of the conduction threshold voltage VT0 of the WL0 is also different from that of other word lines, for example, when a higher programming voltage is applied to the WL0, the WL1 can obtain a narrower conduction threshold voltage VT1 distribution curve based on the capacitive coupling action of the WL0 and the WL2, and the WL0 is only subjected to the action of the WL1, so that the difference between the VT0 distribution of the WL0 and the VT1 distribution of the WL1 is larger, and the conduction threshold voltage of the WL0 is larger than the conduction threshold voltage of the WL1 after being read for a certain number of times, therefore, when the data written in the WL0 is read, the WL0 should be in the conduction logic, but cannot be conducted because the VT0 is larger, and the written data cannot be correctly read. Therefore, when the nonvolatile memory is read, a target programming word line is determined in a memory block to be processed, the programming voltage compensation amount of the target programming word line is determined, and a first programming voltage is applied to the target programming word line initially; and the first programming voltage is: the difference between the preset programming voltage and the compensation amount of the programming voltage, that is, the first programming voltage is obtained by subtracting the compensation amount of the programming voltage of the target programming word line from the preset programming voltage, and the preset programming voltage is smaller, so that in the couple effect of VT1, the function of VT0 is smaller, so that the couple effect of VT1 is close to the couple effect of VT0, and further the distribution of VT0 is similar to that of VT1, thereby avoiding a logic error caused by an excessively large difference between the turn-on threshold voltages of VT0 and other word lines, and further avoiding the phenomenon that the written data in the initial word line WL0 cannot be correctly read. It can be understood that, in a write operation, it is usually necessary to apply a program voltage for many times to complete all the write operations, and therefore, in a case where the write operation is not completed on the target program word line, a second program voltage is applied to the target program word line; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment; the write operation may be completed after multiple applications of incrementally increasing programming voltages.
Example two
Referring to fig. 4, a block diagram of a nonvolatile memory write processing apparatus is shown, which may specifically include:
a target programming word line determining module 310, configured to determine a target programming word line of a memory block to be processed when a write operation is performed on the memory block to be processed;
a program voltage compensation amount determining module 320 for determining a program voltage compensation amount of the target program word line;
a first voltage applying module 330 for applying a first programming voltage to the target programming word line; the first programming voltage is: presetting the difference between a programming voltage and the compensation quantity of the programming voltage;
a second voltage applying module 340, configured to apply a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment.
Optionally, the method further includes:
and the determining module is used for determining the programming voltage compensation amount corresponding to each word line in the memory block to be processed.
Optionally, the method further includes:
a third voltage applying module, configured to apply a third programming voltage to the target programming word line if the target programming word line does not complete the write operation; the third programming voltage is: a sum of the second programming voltage and a first preset voltage increment.
Optionally, the method further includes:
a fourth voltage applying module, configured to apply a fourth programming voltage to the target programming word line if the target programming word line does not complete the write operation; the fourth programming voltage is: a sum of the second programming voltage and a second preset voltage increment, wherein the first preset voltage increment is not equal to the second preset voltage increment.
Optionally, the to-be-processed storage block includes: 64 word lines WL, the 64 word lines being the word lines ordered from WL0 to WL 63.
In summary, in the embodiment of the present invention, it is found that the reason why the written data in the initial word line WL0 cannot be correctly read in the prior art is that: in three continuous word lines, the middle word line is subjected to capacitive coupling action (couple effect) of the word lines on two sides, so that the conduction threshold voltage of the middle word line is increased, while only one side of the initial word line WL0 is provided with the word line, so that the capacitive coupling action on the WL0 is weaker, and the distribution of the conduction threshold voltage VT0 of the WL0 is also different from that of other word lines, for example, when a higher programming voltage is applied to the WL0, the WL1 can obtain a narrower conduction threshold voltage VT1 distribution curve based on the capacitive coupling action of the WL0 and the WL2, and the WL0 is only subjected to the action of the WL1, so that the difference between the VT0 distribution of the WL0 and the VT1 distribution of the WL1 is larger, and the conduction threshold voltage of the WL0 is larger than the conduction threshold voltage of the WL1 after being read for a certain number of times, therefore, when the data written in the WL0 is read, the WL0 should be in the conduction logic, but cannot be conducted because the VT0 is larger, and the written data cannot be correctly read. Therefore, when the nonvolatile memory is read, a target programming word line is determined in a memory block to be processed, the programming voltage compensation amount of the target programming word line is determined, and a first programming voltage is applied to the target programming word line initially; and the first programming voltage is: the difference between the preset programming voltage and the compensation amount of the programming voltage, that is, the first programming voltage is obtained by subtracting the compensation amount of the programming voltage of the target programming word line from the preset programming voltage, and the preset programming voltage is smaller, so that in the couple effect of the VT1, the VT0 has a smaller effect, so that the couple effect of the VT1 is close to the couple effect of the VT0, and further the distribution of the VT0 is similar to the distribution of the VT1, thereby avoiding a logic error caused by an excessively large difference between the turn-on threshold voltages of the VT0 and other word lines, and further avoiding the phenomenon that the written data in the initial word line WL0 cannot be correctly read. It can be understood that, in a write operation, it is usually necessary to apply a program voltage for many times to complete all the write operations, and therefore, in a case where the write operation is not completed on the target program word line, a second program voltage is applied to the target program word line; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment; the write operation may be completed after multiple applications of incrementally increasing programming voltages.
For the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically-processable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (transport media), such as modulated data signals and carrier waves.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable non-volatile memory write processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable non-volatile memory write processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable non-volatile memory to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable non-volatile memory write processing terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the true scope of the embodiments of the present invention.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or terminal device that comprises the element.
The present invention provides a method and a device for processing a non-volatile memory write, which are introduced in detail above, and specific examples are applied herein to explain the principles and embodiments of the present invention, and the descriptions of the above embodiments are only used to help understanding the method and the core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A non-volatile memory write processing method, the method comprising:
determining a target programming word line of a memory block to be processed when the memory block to be processed executes a write operation;
determining a program voltage compensation amount of the target program word line;
applying a first programming voltage to the target programming word line; the first programming voltage is: presetting a difference between a programming voltage and the compensation quantity of the programming voltage;
applying a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment;
when the write operation is executed on the memory block to be processed, before determining the target programming word line of the memory block to be processed, the method further comprises:
determining a program voltage compensation amount corresponding to each word line in the memory block to be processed, wherein the program voltage compensation amount of the edge word line is higher than that of the middle word line.
2. The method of claim 1, wherein the applying a second programming voltage to the target programming word line if the target programming word line does not complete a write operation; the second programming voltage is: after the sum of the first programming voltage and the first preset voltage increment, the method further comprises:
applying a third programming voltage to the target programming word line if the target programming word line does not complete a write operation; the third programming voltage is: a sum of the second programming voltage and a first preset voltage increment.
3. The method according to claim 1, wherein the applying a second programming voltage to the target programming word line in case the target programming word line does not complete a write operation; the second programming voltage is: after the summation of the first programming voltage and the first preset voltage increment, the method further comprises:
applying a fourth programming voltage to the target programming word line if the target programming word line does not complete the write operation; the fourth programming voltage is: a sum of the second programming voltage and a second preset voltage increment, wherein the first preset voltage increment is not equal to the second preset voltage increment.
4. The method according to any of claims 1-3, wherein the pending memory block comprises: 64 word lines WL, the 64 word lines being word lines ordered from WL0 to WL 63.
5. A non-volatile memory write processing apparatus, the apparatus comprising:
the target programming word line determining module is used for determining a target programming word line of a storage block to be processed when the write operation is executed on the storage block to be processed;
a program voltage compensation amount determination module for determining a program voltage compensation amount of the target program word line;
a first voltage applying module for applying a first programming voltage to the target programming word line; the first programming voltage is: presetting the difference between a programming voltage and the compensation quantity of the programming voltage;
a second voltage applying module for applying a second programming voltage to the target programming word line if the target programming word line does not complete the write operation; the second programming voltage is: a sum of the first programming voltage and a first preset voltage increment;
further comprising:
the determining module is used for determining a program voltage compensation amount corresponding to each word line in the memory block to be processed, wherein the program voltage compensation amount of the edge word line is higher than that of the middle word line.
6. The apparatus of claim 5, further comprising:
a third voltage applying module for applying a third programming voltage to the target programming word line if the target programming word line does not complete the write operation; the third programming voltage is: a sum of the second programming voltage and a first preset voltage increment.
7. The apparatus of claim 5, further comprising:
a fourth voltage applying module, configured to apply a fourth programming voltage to the target programming word line if the target programming word line does not complete the write operation; the fourth programming voltage is: a sum of the second programming voltage and a second predetermined voltage increment, wherein the first predetermined voltage increment and the second predetermined voltage increment are not equal.
8. The apparatus of any of claims 5-7, wherein the pending memory block comprises: 64 word lines WL, the 64 word lines being the word lines ordered from WL0 to WL 63.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1848297A (en) * | 2005-04-11 | 2006-10-18 | 海力士半导体有限公司 | Non-volatile memory device and method of preventing hot electron program disturb phenomenon |
| CN106856102A (en) * | 2015-12-08 | 2017-06-16 | 北京兆易创新科技股份有限公司 | A kind of programmed method of Nand Flash |
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| US8737131B2 (en) * | 2011-11-29 | 2014-05-27 | Micron Technology, Inc. | Programming memory cells using smaller step voltages for higher program levels |
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| CN1848297A (en) * | 2005-04-11 | 2006-10-18 | 海力士半导体有限公司 | Non-volatile memory device and method of preventing hot electron program disturb phenomenon |
| CN106856102A (en) * | 2015-12-08 | 2017-06-16 | 北京兆易创新科技股份有限公司 | A kind of programmed method of Nand Flash |
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