CN110634525B - Nonvolatile memory processing method and device - Google Patents
Nonvolatile memory processing method and device Download PDFInfo
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- CN110634525B CN110634525B CN201810664594.4A CN201810664594A CN110634525B CN 110634525 B CN110634525 B CN 110634525B CN 201810664594 A CN201810664594 A CN 201810664594A CN 110634525 B CN110634525 B CN 110634525B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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Abstract
The embodiment of the invention provides a nonvolatile memory processing method and a nonvolatile memory processing device, wherein the method comprises the following steps: acquiring a current erasing pulse state in the nonvolatile memory; determining an adjustment voltage according to the current erasing pulse state; determining a first voltage corresponding to a current erasing pulse; determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage; and in the next erasing pulse, erasing operation is carried out according to the second voltage. In the embodiment of the invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, and the erasing operation is carried out according to the second voltage in the next erasing pulse, so that the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for processing a nonvolatile memory.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), can realize multiple times of programming, and has large capacity, simple reading and writing, few peripheral devices and low price.
In the prior art, when an erase operation is performed on a NAND memory, an erase process usually corresponds to a plurality of erase pulses, a voltage corresponding to an erase pulse at an initial time is an initial voltage, and as the erase operation is performed, a voltage corresponding to each erase pulse is gradually increased according to a fixed erase pulse voltage difference based on the initial voltage until the erase operation is completed.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: if the fixed erasing pulse voltage difference is small, the damage to the cell is small when the NAND memory is subjected to erasing operation, so that the reliability of the cell is high, but the erasing efficiency is low; if the fixed erase pulse voltage difference is large, the erase efficiency is high when the NAND memory is erased, but the cell is damaged, resulting in the decrease of the reliability of the cell. That is, no matter what the fixed erase pulse voltage difference is set, a reliable and efficient erase operation of the nonvolatile memory cannot be realized.
Disclosure of Invention
In view of the above, embodiments of the present invention are proposed to provide a non-volatile memory processing method and apparatus that overcome or at least partially solve the above problems.
According to a first aspect of the present invention, there is provided a non-volatile memory processing method, the method comprising:
acquiring a current erasing pulse state in the nonvolatile memory;
determining an adjustment voltage according to the current erasing pulse state;
determining a first voltage corresponding to a current erasing pulse;
determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage;
and in the next erasing pulse, erasing operation is carried out according to the second voltage.
According to a second aspect of the present invention, there is provided a non-volatile memory processing apparatus, the apparatus comprising:
the current erasing pulse state acquisition module is used for acquiring the current erasing pulse state in the nonvolatile memory;
the adjusting voltage determining module is used for determining adjusting voltage according to the current erasing pulse state;
the first voltage determining module is used for determining a first voltage corresponding to the current erasing pulse;
the second voltage determining module is used for determining a second voltage corresponding to the next erasing pulse according to the regulating voltage and the first voltage;
and the erasing module is used for erasing operation according to the second voltage in the next erasing pulse.
In the embodiment of the invention, the current erasing pulse state in the nonvolatile memory is firstly obtained, the regulating voltage is determined according to the current erasing state, and the first voltage corresponding to the current erasing pulse is determined; then determining a second voltage corresponding to the next erasing pulse according to the current regulating voltage and the first voltage; that is, in the embodiment of the present invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, for example, in one erasing operation, the adjustment voltage may be determined to be a larger value according to the current erasing pulse state, so that the second voltage is much larger than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the erasing efficiency can be improved; in another erasing, the adjusting voltage can be determined to be a negative value according to the current erasing pulse state, so that the second voltage is smaller than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the damage to the memory cell can be reduced, and the reliability of the memory cell is improved; therefore, the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart of a method for processing a non-volatile memory according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for processing a non-volatile memory according to an embodiment of the present invention;
FIG. 3 is a block diagram of a non-volatile memory processing device according to an embodiment of the present invention;
FIG. 4 is a detailed block diagram of a nonvolatile memory processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 1, a flowchart of a processing method of a nonvolatile memory is shown, which may specifically include the following steps:
step 101: the current erase pulse state in the non-volatile memory is obtained.
In the embodiment of the invention, the nonvolatile memory can be provided with the detection module, and the current erasing pulse state in the nonvolatile memory can be acquired through the detection module. In specific application, the detection module can acquire the current erasing pulse state once after each erasing pulse is finished, so that the current erasing pulse state of the nonvolatile memory can be obtained after each erasing pulse is finished, and the erasing operation of the nonvolatile memory can be accurately controlled; the detection module may also acquire the current erase pulse state once after two or more erase pulses are completed, and intermittently acquire the current erase pulse state of the nonvolatile memory to reduce the occupation of the detection operation on resources.
In a specific application, the current erase pulse state in the non-volatile memory may be: the number of the erase pulses that have been sent out, or the number of the erase pulses that have not been sent out, etc., may be set by those skilled in the art according to the actual application scenario, and the embodiment of the present invention does not limit the specific content of the current erase pulse state.
Step 102: and determining the regulating voltage according to the current erasing pulse state.
In the embodiment of the invention, the data erasing process of the nonvolatile memory is taken as a dynamically adjustable process, and the adjusting voltage can be determined according to the current erasing pulse state in the nonvolatile memory.
In specific applications, the adjustment voltage may be determined according to a comparison between a current erase pulse state and a last acquired erase pulse state. For example, if the current erase pulse state is the number of already-issued erase pulses, the adjustment voltage may be determined according to the comparison between the current number of already-issued erase pulses and the number of already-issued erase pulses obtained last time. Specifically, if the number of the currently issued erase pulses is much larger than the number of the issued erase pulses obtained last time, it indicates that the current erase voltage is too large, the erase speed is too fast, and damage is easily caused to the memory cells of the nonvolatile memory, so that the adjustment voltage may be determined to be a negative value, or the adjustment voltage may be determined to be zero, that is, the original erase voltage is kept from increasing.
In specific application, the adjustment voltage can also be determined according to the comparison condition of the current erasing pulse state and the total number of the preset erasing pulses. For example, if the current erase pulse state is the number of the issued erase pulses, the adjustment voltage may be determined according to the comparison between the current number of the issued erase pulses and the total number of the preset erase pulses. Specifically, if the number of currently issued erase pulses is much smaller than the preset total number of erase pulses, it is indicated that the erase voltage can be increased to increase the erase speed, and thus the adjustment voltage can be determined to be a positive value.
It is understood that, according to the actual situation, a person skilled in the art may also determine the adjustment voltage by using other methods according to the current erase pulse state, which is not specifically limited in the embodiment of the present invention.
Step 103: a first voltage corresponding to a current erase pulse is determined.
In the embodiment of the invention, when the nonvolatile memory is erased, each erasing pulse corresponds to an erasing voltage, and the voltage value corresponding to the currently acquired erasing pulse is called as a first voltage.
Step 104: and determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage.
In the embodiment of the invention, the adjusting voltage and the first voltage can be summed to obtain the second voltage. If the regulated voltage is a positive value, the second voltage is greater than the first voltage; if the regulated voltage is a negative value, the second voltage is less than the first voltage; if the regulated voltage is zero, the second voltage is equal to the first voltage. It can be understood that a person skilled in the art may perform other linear operations on the adjustment voltage and the first voltage to obtain the second voltage, and the embodiment of the present invention does not specifically limit the manner of determining the second voltage corresponding to the next erase pulse.
Step 105: and in the next erasing pulse, erasing operation is carried out according to the second voltage.
In the embodiment of the invention, after the second voltage is determined, the determined second voltage is adopted to carry out erasing operation in the next erasing operation, and the second voltage is the erasing voltage which accords with the erasing state of the current nonvolatile memory, so that the reliable and efficient erasing operation of the nonvolatile memory can be realized.
In summary, in the embodiment of the present invention, a current erase pulse state in the nonvolatile memory is first obtained, the adjustment voltage is determined according to the current erase state, and a first voltage corresponding to the current erase pulse is determined; then determining a second voltage corresponding to the next erasing pulse according to the current regulating voltage and the first voltage; that is, in the embodiment of the present invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, for example, in one erasing operation, the adjustment voltage may be determined to be a larger value according to the current erasing pulse state, so that the second voltage is much larger than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the erasing efficiency can be improved; in another erasing, the adjusting voltage can be determined to be a negative value according to the current erasing pulse state, so that the second voltage is smaller than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the damage to the memory cell can be reduced, and the reliability of the memory cell is improved; therefore, the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.
Example two
Referring to fig. 2, a specific flowchart of a processing method of a nonvolatile memory is shown, which may specifically include the following steps:
step 201: acquiring a current erasing pulse state in the nonvolatile memory; the non-volatile memory corresponds to an initial erase pulse voltage difference.
In the embodiment of the present invention, an initial erase pulse voltage difference of the nonvolatile memory may be set, where the initial erase pulse voltage difference is: and when the adjusting voltage is 0, the difference value of the erasing voltages corresponding to every two adjacent erasing pulses. Specifically, when the adjustment voltage is 0, if the erase voltage corresponding to the previous erase pulse is u0, the erase voltage corresponding to the current erase pulse is u1, and the erase voltage corresponding to the next erase pulse is u2, the difference between u1 and u0 is the initial erase pulse voltage difference, and the difference between u2 and u1 is also the initial erase pulse voltage difference.
Step 202: and determining the regulating voltage according to the current erasing pulse state.
As a preferable solution of the embodiment of the present invention, the current erase pulse state includes: a first number of erase pulses have been issued at the present time, step 202 comprising:
determining a first difference between the first number and the second number; the second number is: a number of erase pulses that have been issued in the non-volatile memory at a first time; the first time is earlier than the current time; if the first difference is smaller than a first threshold value, determining that the regulating voltage is a positive value; if the first difference is larger than a first threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first difference is equal to the first threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
In the embodiment of the present invention, the nonvolatile memory may set a storage location, and store the acquired time and number of times when the erase pulse has been sent out at each time in the storage location. After acquiring the first number of currently issued erase pulses, the time of acquiring the first number, and the second number of the issued erase pulses in the nonvolatile memory acquired when the first number is stored in the storage location, and the first time is taken out from the storage location, where the first time is earlier than the current time, may be the time of acquiring the number of issued erase pulses immediately before the current time, or may be any time earlier than the current time, and a specific value of the first time is not limited in the embodiment of the present invention.
In the specific application, a first number of currently sent erasing pulses is determined, and a difference between the first number of currently sent erasing pulses and a second number of currently sent erasing pulses in the nonvolatile memory at a first moment is a first difference value; if the first difference is greater than the first threshold, it indicates that the number of currently-issued erase pulses is greater than the number of currently-issued erase pulses at the first time, it may be determined that the current erase speed is faster, and therefore, the adjustment voltage may be determined to be a negative value, or may be determined to be zero; if the first difference is equal to the first threshold, a person skilled in the art may determine, according to an actual situation, that the adjustment voltage is a positive value, or that the adjustment voltage is a negative value, or that the adjustment voltage is zero, which is not specifically limited in the embodiment of the present invention. The measurement units of the first threshold may be consistent with the measurement units of the first number and the second number, for example, the measurement units are collectively set to be bits, bytes, double bytes, pieces, and the like, and the specific value of the first threshold may be set according to an actual application scenario, for example, when a requirement on the erase efficiency of the nonvolatile memory is high, the first threshold may be set to be a small value, and when a requirement on the performance reliability of the nonvolatile memory is high, the first threshold may be set to be a large value.
As another preferable solution of the embodiment of the present invention, the current erase pulse state includes: a third number of erase pulses are not issued at the present time, step 202 comprising:
determining a second difference between the third number and the fourth number; the third number is: the number of erase pulses not issued in the non-volatile memory at a second time; the second time is earlier than the current time; if the second difference is larger than a second threshold value, determining that the regulating voltage is a positive value; if the second difference is smaller than a second threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second difference is equal to the second threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
In the embodiment of the present invention, the nonvolatile memory may set a storage location, and store the acquired time and number of times when the erase pulse has been sent out at each time in the storage location. After acquiring the third number of the currently non-emitted erase pulses, the time of acquiring the third number, and the fourth number of the currently non-emitted erase pulses in the nonvolatile memory acquired when the third number is stored in the storage location, and the second time is taken out from the storage location, where the second time is earlier than the current time, may be the time of acquiring the number of the already-emitted erase pulses immediately before the current time, or may be any time earlier than the current time, and a specific value of the second time is not limited in the embodiment of the present invention.
In a specific application, determining that the difference between the current third number of the un-sent erasing pulses and the fourth number of the un-sent erasing pulses in the nonvolatile memory at the second moment is a second difference value, wherein the number of the un-sent erasing pulses is continuously reduced during the erasing operation, so that the second difference value is a negative value under a normal condition; if the second difference is larger than the second threshold, the number of the currently-emitted erasing pulses is indicated, and the difference between the number of the currently-emitted erasing pulses and the number of the currently-emitted erasing pulses at the second moment is not large, the current erasing efficiency can be judged to be low, so that the regulating voltage can be determined to be a positive value; if the second difference is smaller than the second threshold, it indicates that the number of the currently-emitted erase pulses is not greater than the number of the currently-emitted erase pulses at the second time, it may be determined that the current erase speed is faster, and therefore, the adjustment voltage may be determined to be a negative value, or may be determined to be zero; if the second difference is equal to the second threshold, a person skilled in the art may determine, according to an actual scenario, that the adjustment voltage is a positive value, or that the adjustment voltage is a negative value, or that the adjustment voltage is zero, which is not specifically limited in the embodiment of the present invention. The second threshold may be set to be a negative value, the measurement units of the second threshold may be consistent with the measurement units of the third number and the fourth number, for example, the measurement units are uniformly set to be bits, bytes, double bytes, units, and the like, the specific value of the second threshold may be set according to an actual application scenario, for example, when the requirement on the erasure efficiency of the nonvolatile memory is high, the second threshold may be set to be a large negative value, and when the requirement on the performance reliability of the nonvolatile memory is high, the second threshold may be set to be a small negative value, which is not specifically limited in the embodiment of the present invention.
It can be understood that, in the embodiment of the present invention, the second threshold may be further set to be a positive value, the adjustment voltage is determined according to a magnitude relationship between the absolute value of the second difference and the second threshold, if the absolute value of the second difference is smaller than the second threshold, it indicates that the number of the currently-emitted erase pulses is not large, and if the difference between the absolute value of the second difference and the number of the currently-emitted erase pulses is not large, it may be determined that the current erase efficiency is low, and therefore, the adjustment voltage may be determined to be the positive value; if the absolute value of the second difference is greater than the second threshold, it indicates that the number of currently-emitted erase pulses is greater than the number of currently-emitted erase pulses at the second time, it may be determined that the current erase speed is faster, and therefore, the adjustment voltage may be determined to be a negative value. The embodiment of the present invention is not particularly limited to this.
As another preferable solution of the embodiment of the present invention, the current erase pulse state includes: a fifth number of erase pulses have been issued at the present time, step 202 comprising:
determining a first ratio of the fifth number to a total number of pulses, the total number of pulses being a preset total number of pulses in the non-volatile memory; if the first ratio is smaller than a third threshold value, determining that the regulated voltage is a positive value; if the first ratio is larger than a third threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first ratio is equal to the third threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
In the embodiment of the invention, when the nonvolatile memory is initially erased, the total quantity of pulses which need to be erased can be determined, and after the fifth quantity of the currently sent erasing pulses is obtained, the first ratio of the fifth quantity to the total quantity of the pulses can be determined.
In specific application, if the first ratio is smaller than the third threshold, the number of currently-sent erase pulses is indicated, and the ratio of the total number of preset erase pulses to the total number of preset erase pulses is smaller, the current erase efficiency can be determined to be lower, so that the adjustment voltage can be determined to be a positive value; if the first ratio is greater than the third threshold, it indicates that the number of currently-issued erase pulses is greater than the total preset number of erase pulses, and it may be determined that the current erase speed is faster, and therefore, the adjustment voltage may be determined to be a negative value, or may be determined to be zero; if the first ratio is equal to the third threshold, a person skilled in the art may determine, according to an actual scenario, that the adjustment voltage is a positive value, or that the adjustment voltage is a negative value, or that the adjustment voltage is zero, which is not specifically limited in the embodiment of the present invention. The specific value of the third threshold may be set according to an actual application scenario, for example, when the requirement on the erase efficiency of the nonvolatile memory is high, the third threshold may be set to a smaller value, and when the requirement on the performance reliability of the nonvolatile memory is high, the third threshold may be set to a larger value.
As another preferable solution of the embodiment of the present invention, the current erase pulse state includes: a sixth number of erase pulses are not issued at the present time, step 202 comprising:
determining a second ratio of the sixth quantity to a total number of pulses, the total number of pulses being a preset total number of pulses in the non-volatile memory; if the second ratio is larger than a fourth threshold, determining that the regulated voltage is a positive value; if the second ratio is smaller than a fourth threshold, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second ratio is equal to the fourth threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
In the embodiment of the invention, when the nonvolatile memory is initially erased, the total amount of pulses which need to be erased can be determined, and after the sixth amount of currently-unexmitted erasing pulses is obtained, the second ratio of the sixth amount to the total amount of pulses can be determined.
In specific application, if the second ratio is greater than the fourth threshold, it indicates that the number of currently-emitted erase pulses is not greater, and the ratio of the currently-emitted erase pulses to the total preset erase pulses is greater, it can be determined that the current erase efficiency is low, and therefore, the adjustment voltage can be determined as a positive value; if the second ratio is smaller than the fourth threshold, it indicates that the number of currently-issued erase pulses is smaller than the preset erase pulses, and it may be determined that the current erase speed is faster, and therefore, the adjustment voltage may be determined to be a negative value, or may be determined to be zero; if the second ratio is equal to the fourth threshold, a person skilled in the art may determine, according to an actual situation, that the adjustment voltage is a positive value, or that the adjustment voltage is a negative value, or that the adjustment voltage is zero, which is not specifically limited in the embodiment of the present invention. The specific value of the fourth threshold may be set according to an actual application scenario, for example, when the requirement on the erase efficiency of the nonvolatile memory is high, the fourth threshold may be set to a smaller value, and when the requirement on the performance reliability of the nonvolatile memory is high, the fourth threshold may be set to a larger value.
It can be understood that, in practical application, a person skilled in the art may also set a threshold of the number of emitted erase pulses in advance according to a practical application scenario, and after obtaining the current number of emitted erase pulses of the nonvolatile memory, if the current number of emitted erase pulses is smaller than the threshold of the preset number of emitted erase pulses, it may be determined that the current erase efficiency is low, and therefore, the adjustment voltage may be determined to be a positive value; if the current number of issued erase pulses is greater than the threshold for the preset number of issued erase pulses, it may be determined that the current erase speed is fast, and therefore, the adjustment voltage may be determined to be a negative value, or may be determined to be zero; if the current number of issued erase pulses is equal to the preset threshold for the number of issued erase pulses, a person skilled in the art may determine, according to an actual scenario, that the adjustment voltage is a positive value, or that the adjustment voltage is a negative value, or that the adjustment voltage is zero, which is not specifically limited in this embodiment of the present invention.
In practical application, a person skilled in the art can also preset a threshold value of the number of the non-emitted erasing pulses according to an actual application scene, and after the current number of the non-emitted erasing pulses of the nonvolatile memory is acquired, if the current number of the non-emitted erasing pulses is greater than the preset threshold value of the number of the emitted erasing pulses, it can be determined that the current erasing efficiency is low, and therefore, the adjustment voltage can be determined as a positive value; if the number of the currently unexmitted erase pulses is smaller than the preset threshold value of the number of the emitted erase pulses, the current erase speed can be judged to be faster, and therefore, the regulating voltage can be determined to be a negative value, or the regulating voltage can be determined to be zero; if the current number of non-emitted erase pulses is equal to the preset threshold for the number of emitted erase pulses, a person skilled in the art may determine, according to an actual scenario, that the adjustment voltage is a positive value, or that the adjustment voltage is a negative value, or that the adjustment voltage is zero, which is not specifically limited in this embodiment of the present invention.
Step 203: a first voltage corresponding to a current erase pulse is determined.
Step 204: and adjusting the initial erasing pulse voltage difference value according to the adjusting voltage to obtain an actual adjusting voltage difference value.
Step 205: and determining a second voltage corresponding to the next erasing pulse according to the difference value of the first voltage and the actual adjusting voltage.
In the embodiment of the invention, a voltage adjusting module can be arranged in the nonvolatile memory, and the voltage adjusting module can adjust the voltage difference of the initial erasing pulse. In a specific application, the sum of the adjustment voltage and the voltage difference of the initial erase pulse may be determined as the actual adjustment voltage difference. For example, if the adjustment voltage is a positive value, it is determined that the actual adjustment voltage difference value is a value greater than the initial erase pulse voltage difference value; if the adjustment voltage is a negative value, determining that the actual adjustment voltage difference is a value less than the initial erase pulse voltage difference; if the adjustment voltage is zero, the actual adjustment voltage difference is determined to be a value equal to the initial erase pulse voltage difference. That is, in the embodiment of the present invention, the actual adjustment voltage difference is not a fixed value, but a dynamically changing value determined according to the current erase pulse state.
After the actual adjustment voltage difference is determined, the sum of the actual adjustment voltage difference and the first voltage may be used as the second voltage, and it can be understood that a person skilled in the art may perform other linear operations on the actual adjustment voltage difference and the first voltage to obtain the second voltage.
In the embodiment of the invention, the second voltage corresponding to the next erasing pulse is determined by adjusting the initial erasing pulse voltage difference of the nonvolatile memory, the logic module can be simply arranged in the nonvolatile memory, the logic module adjusts the initial erasing pulse voltage difference according to the adjusting voltage, the adjusting mode is simple, and the method is easy to realize.
As another preferred solution of the embodiment of the present invention, the nonvolatile memory corresponds to an initial erase voltage and an initial erase pulse voltage difference; steps 204 and 205 may be replaced with:
step A1: and determining an initial erasing voltage adjusting value according to the adjusting voltage.
Step A2: and determining a second voltage corresponding to the next erasing pulse according to the first voltage, the initial erasing voltage adjustment value and the initial erasing pulse voltage difference value.
In the embodiment of the present invention, a difference between an initial erase voltage and an initial erase pulse voltage of the nonvolatile memory may be set, so that when the adjustment voltage is 0, the erase voltage corresponding to each erase pulse is obtained by summing the initial erase voltage and one or more initial erase pulse voltage differences, and a difference between the erase voltages corresponding to every two adjacent erase pulses is the initial erase pulse voltage difference.
In a specific application, a voltage regulation module can be arranged in the nonvolatile memory, and the voltage regulation module can regulate the initial erasing voltage. Specifically, the adjustment voltage may be determined as an initial erase voltage adjustment value. According to the initial erase voltage adjustment value, the initial erase voltage can be adjusted, that is, in the embodiment of the present invention, the actual initial erase voltage is not a fixed value but a dynamically changing value determined according to the current erase pulse state.
After the initial erase voltage adjustment value is determined, the initial erase voltage adjustment value, the first voltage, and the initial erase pulse voltage difference value may be summed to obtain the second voltage, and it can be understood that a person skilled in the art may perform other linear operations on the initial erase voltage adjustment value, the first voltage, and the initial erase pulse voltage difference value to obtain the second voltage.
In the embodiment of the invention, the second voltage corresponding to the next erasing pulse is determined by adjusting the initial erasing voltage of the nonvolatile memory, and the second voltage can be realized by simply setting a logic module in the nonvolatile memory and adjusting the initial erasing voltage by the logic module according to the adjusting voltage; the initial erase voltage gradient option may also be set in the nonvolatile memory, where different gradient options correspond to different initial erase voltage values, and the initial erase voltage may be adjusted by controlling the gradient option, which is not specifically limited in this embodiment of the present invention.
It can be understood that as another preferred implementation manner of the embodiment of the present invention, a voltage adjustment module may be further disposed in the nonvolatile memory, where the voltage adjustment module may implement adjustment of both the initial erase voltage and the initial erase pulse voltage difference, and determine the second voltage by adjusting the initial erase pulse voltage difference of the initial erase voltage at the same time, which is not specifically limited in the embodiment of the present invention.
Step 206: and in the next erasing pulse, erasing operation is carried out according to the second voltage.
In summary, in the embodiment of the present invention, a current erase pulse state in the nonvolatile memory is first obtained, the adjustment voltage is determined according to the current erase state, and a first voltage corresponding to the current erase pulse is determined; then determining a second voltage corresponding to the next erasing pulse according to the current regulating voltage and the first voltage; that is, in the embodiment of the present invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, for example, in one erasing operation, the adjustment voltage may be determined to be a larger value according to the current erasing pulse state, so that the second voltage is much larger than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the erasing efficiency can be improved; in another erasing, the adjusting voltage can be determined to be a negative value according to the current erasing pulse state, so that the second voltage is smaller than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the damage to the memory cell can be reduced, and the reliability of the memory cell is improved; therefore, the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.
It should be noted that the foregoing method embodiments are described as a series of acts or combinations for simplicity in explanation, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
EXAMPLE III
Referring to fig. 3, there is shown a block diagram of a non-volatile memory processing apparatus, which may specifically include:
a current erasing pulse state obtaining module 310, configured to obtain a current erasing pulse state in the nonvolatile memory;
an adjustment voltage determining module 320, configured to determine an adjustment voltage according to the current erase pulse state;
a first voltage determining module 330, configured to determine a first voltage corresponding to the current erase pulse;
a second voltage determining module 340, configured to determine a second voltage corresponding to a next erase pulse according to the adjustment voltage and the first voltage;
and an erasing module 350, configured to perform an erasing operation according to the second voltage in the next erasing pulse.
Preferably, referring to fig. 4, on the basis of fig. 3, the apparatus may further include:
preferably, the nonvolatile memory corresponds to an initial erase pulse voltage difference; the second voltage determining module 340 includes:
the second voltage determination first sub-module 3401 is configured to adjust the initial erase pulse voltage difference according to the adjustment voltage to obtain an actual adjustment voltage difference; and determining a second voltage corresponding to the next erasing pulse according to the difference value of the first voltage and the actual adjusting voltage.
Preferably, the nonvolatile memory corresponds to an initial erase voltage, and an initial erase pulse voltage difference; the second voltage determining module 340 includes:
the second voltage determination second submodule is used for determining an initial erasing voltage adjustment value according to the adjusting voltage; and determining a second voltage corresponding to the next erasing pulse according to the first voltage, the initial erasing voltage adjustment value and the initial erasing pulse voltage difference value.
Preferably, the current erase pulse state includes: the adjustment voltage determining module 320 comprises:
a first regulation voltage determination submodule 3201 for determining a first difference of the first number and the second number; the second number is: a number of erase pulses that have been issued in the non-volatile memory at a first time; the first time is earlier than the current time; if the first difference is smaller than a first threshold value, determining that the regulating voltage is a positive value; if the first difference is larger than a first threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first difference is equal to the first threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
Preferably, the current erase pulse state includes: a third number of erase pulses not being sent at the present time, the adjustment voltage determining module 320 includes:
a second regulation voltage determination submodule 3202 for determining a second difference between the third number and the fourth number; the third number is: the number of erase pulses not issued in the non-volatile memory at a second time; the second time is earlier than the current time; if the second difference is larger than a second threshold value, determining that the regulating voltage is a positive value; if the second difference is smaller than a second threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second difference is equal to the second threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
Preferably, the current erase pulse state includes: a fifth number of erase pulses have been issued at the present time, the adjustment voltage determination module 320 includes:
a third adjustment voltage determining submodule 3203, configured to determine a first ratio of the fifth number to a total number of pulses, where the total number of pulses is a total number of pulses preset in the nonvolatile memory; if the first ratio is smaller than a third threshold value, determining that the regulated voltage is a positive value; if the first ratio is larger than a third threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first ratio is equal to the third threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
Preferably, the current erase pulse state includes: a sixth number of erase pulses not being sent at the present time, the adjustment voltage determining module 320 includes:
a fourth adjustment voltage determining submodule 3204, configured to determine a second ratio of the sixth number to a total number of pulses, where the total number of pulses is a total number of pulses preset in the nonvolatile memory; if the second ratio is larger than a fourth threshold, determining that the regulated voltage is a positive value; if the second ratio is smaller than a fourth threshold, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second ratio is equal to the fourth threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
In summary, in the embodiment of the present invention, a current erase pulse state in the nonvolatile memory is first obtained, the adjustment voltage is determined according to the current erase state, and a first voltage corresponding to the current erase pulse is determined; then determining a second voltage corresponding to the next erasing pulse according to the current regulating voltage and the first voltage; that is, in the embodiment of the present invention, the second voltage is determined according to the current actual erasing condition of the nonvolatile memory, for example, in one erasing operation, the adjustment voltage may be determined to be a larger value according to the current erasing pulse state, so that the second voltage is much larger than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the erasing efficiency can be improved; in another erasing, the adjusting voltage can be determined to be a negative value according to the current erasing pulse state, so that the second voltage is smaller than the first voltage, and in the next erasing pulse, the erasing operation is performed according to the second voltage, so that the damage to the memory cell can be reduced, and the reliability of the memory cell is improved; therefore, the reliable and efficient erasing operation can be carried out in the whole erasing process of the nonvolatile memory.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (fransitory media), such as modulated data signals and carrier waves.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable non-volatile memory processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable non-volatile memory processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable non-volatile processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable non-volatile memory processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The present invention provides a nonvolatile memory processing method and a nonvolatile memory processing apparatus, which have been described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (12)
1. A non-volatile memory processing method, the method comprising:
acquiring a current erasing pulse state in the nonvolatile memory;
determining an adjustment voltage according to the current erasing pulse state;
determining a first voltage corresponding to a current erasing pulse;
determining a second voltage corresponding to the next erasing pulse according to the adjusting voltage and the first voltage;
in the next erasing pulse, erasing operation is carried out according to the second voltage;
the current erase pulse state includes: the step of determining the regulated voltage in dependence upon the current erase pulse state, having issued a first number of erase pulses at the present time, comprises:
determining a first difference between the first number and the second number; the second number is: a number of erase pulses that have been issued in the non-volatile memory at a first time; the first time is earlier than the current time;
if the first difference is smaller than a first threshold value, determining that the regulating voltage is a positive value;
if the first difference is larger than a first threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;
if the first difference is equal to the first threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
2. The method of claim 1, wherein the non-volatile memory corresponds to an initial erase pulse voltage difference;
the step of determining a second voltage corresponding to a next erase pulse according to the adjustment voltage and the first voltage includes:
adjusting the initial erasing pulse voltage difference value according to the adjusting voltage to obtain an actual adjusting voltage difference value;
and determining a second voltage corresponding to the next erasing pulse according to the difference value of the first voltage and the actual adjusting voltage.
3. The method of claim 1, wherein the non-volatile memory corresponds to an initial erase voltage, and an initial erase pulse voltage difference;
the step of determining a second voltage corresponding to a next erase pulse according to the adjustment voltage and the first voltage includes:
determining an initial erase voltage adjustment value according to the adjustment voltage;
and determining a second voltage corresponding to the next erasing pulse according to the first voltage, the initial erasing voltage adjustment value and the initial erasing pulse voltage difference value.
4. The method of claim 1, wherein the current erase pulse state comprises: determining a third number of erase pulses not sent at the present time, wherein the step of determining the regulated voltage according to the state of the present erase pulses comprises:
determining a second difference between the third number and the fourth number; the third number is: the number of erase pulses not issued in the non-volatile memory at a second time; the second time is earlier than the current time;
if the second difference is larger than a second threshold value, determining that the regulating voltage is a positive value;
if the second difference is smaller than a second threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;
if the second difference is equal to the second threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
5. The method of claim 1, wherein the current erase pulse state comprises: determining a fifth number of erase pulses that have been sent at the present time, said determining a regulated voltage based on the state of the present erase pulses comprising:
determining a first ratio of the fifth number to a total number of pulses, the total number of pulses being a preset total number of pulses in the non-volatile memory;
if the first ratio is smaller than a third threshold value, determining that the regulated voltage is a positive value;
if the first ratio is larger than a third threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;
if the first ratio is equal to the third threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
6. The method of claim 1, wherein the current erase pulse state comprises: determining the adjustment voltage according to the current erase pulse state, wherein the sixth number of erase pulses not emitted at the current time comprises:
determining a second ratio of the sixth quantity to a total number of pulses, the total number of pulses being a preset total number of pulses in the non-volatile memory;
if the second ratio is larger than a fourth threshold, determining that the regulated voltage is a positive value;
if the second ratio is smaller than a fourth threshold, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero;
if the second ratio is equal to the fourth threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
7. A non-volatile memory processing apparatus, the apparatus comprising:
the current erasing pulse state acquisition module is used for acquiring the current erasing pulse state in the nonvolatile memory;
the adjusting voltage determining module is used for determining adjusting voltage according to the current erasing pulse state;
the first voltage determining module is used for determining a first voltage corresponding to the current erasing pulse;
the second voltage determining module is used for determining a second voltage corresponding to the next erasing pulse according to the regulating voltage and the first voltage;
the erasing module is used for carrying out erasing operation according to the second voltage in the next erasing pulse;
the current erase pulse state includes: a first number of erase pulses having been issued at a present time, the regulated voltage determination module comprising:
a first regulation voltage determination submodule for determining a first difference between the first number and the second number; the second number is: a number of erase pulses that have been issued in the non-volatile memory at a first time; the first time is earlier than the current time; if the first difference is smaller than a first threshold value, determining that the regulating voltage is a positive value; if the first difference is larger than a first threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first difference is equal to the first threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
8. The apparatus of claim 7, wherein the non-volatile memory corresponds to an initial erase pulse voltage difference;
the second voltage determination module includes:
the second voltage determination first submodule is used for adjusting the initial erasing pulse voltage difference value according to the adjusting voltage to obtain an actual adjusting voltage difference value; and determining a second voltage corresponding to the next erasing pulse according to the difference value of the first voltage and the actual adjusting voltage.
9. The apparatus of claim 7, wherein the non-volatile memory corresponds to an initial erase voltage, and an initial erase pulse voltage difference;
the second voltage determination module includes:
the second voltage determination second submodule is used for determining an initial erasing voltage adjustment value according to the adjusting voltage; and determining a second voltage corresponding to the next erasing pulse according to the first voltage, the initial erasing voltage adjustment value and the initial erasing pulse voltage difference value.
10. The apparatus of claim 7, wherein the current erase pulse state comprises: a third number of erase pulses not being issued at the present time, the adjustment voltage determination module comprising:
a second regulation voltage determination submodule for determining a second difference between the third number and the fourth number; the third number is: the number of erase pulses not issued in the non-volatile memory at a second time; the second time is earlier than the current time; if the second difference is larger than a second threshold value, determining that the regulating voltage is a positive value; if the second difference is smaller than a second threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second difference is equal to the second threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
11. The apparatus of claim 7, wherein the current erase pulse state comprises: a fifth number of erase pulses having been issued at the present time, the adjustment voltage determination module comprising:
a third adjustment voltage determination submodule, configured to determine a first ratio of the fifth number to a total pulse amount, where the total pulse amount is a total pulse amount preset in the nonvolatile memory; if the first ratio is smaller than a third threshold value, determining that the regulated voltage is a positive value; if the first ratio is larger than a third threshold value, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the first ratio is equal to the third threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
12. The apparatus of claim 7, wherein the current erase pulse state comprises: a sixth number of erase pulses not being emitted at the present time, the adjustment voltage determination module comprising:
a fourth adjustment voltage determination submodule, configured to determine a second ratio of the sixth number to a total pulse amount, where the total pulse amount is a total pulse amount preset in the nonvolatile memory; if the second ratio is larger than a fourth threshold, determining that the regulated voltage is a positive value; if the second ratio is smaller than a fourth threshold, determining that the adjusting voltage is a negative value, or determining that the adjusting voltage is zero; if the second ratio is equal to the fourth threshold, determining that the regulated voltage is a positive value, or determining that the regulated voltage is a negative value, or determining that the regulated voltage is zero.
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Address after: Room 604, block B, Tengfei innovation center, No.38, Gaoxin 6th Road, high tech Zone, Xi'an City, Shaanxi Province, 710075 Patentee after: XI'AN GEYI ANCHUANG INTEGRATED CIRCUIT Co.,Ltd. Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: Room 604, block B, Tengfei innovation center, No.38, Gaoxin 6th Road, high tech Zone, Xi'an City, Shaanxi Province, 710075 Patentee before: XI'AN GEYI ANCHUANG INTEGRATED CIRCUIT Co.,Ltd. Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |