CN111951862A - Nonvolatile memory erasing processing method and device - Google Patents
Nonvolatile memory erasing processing method and device Download PDFInfo
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- CN111951862A CN111951862A CN201910399725.5A CN201910399725A CN111951862A CN 111951862 A CN111951862 A CN 111951862A CN 201910399725 A CN201910399725 A CN 201910399725A CN 111951862 A CN111951862 A CN 111951862A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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Abstract
The embodiment of the invention provides a nonvolatile memory erasing processing method and a nonvolatile memory erasing processing device, wherein the method comprises the following steps: verifying the erasing state of the memory block to be erased; and when the memory block to be erased is in an erased state, applying no erasing pulse to the memory block to be erased. When the erasing operation is carried out on the memory block to be erased in the nonvolatile memory, the erasing state of the memory block to be erased is verified firstly, and under the condition that the memory block to be erased is in the erased state, the erasing pulse is not applied to the memory block to be erased, so that the memory block to be erased in the erased state does not need to bear the meaningless erasing pulse, and the service life of the nonvolatile memory can be prolonged.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a method and an apparatus for erasing a nonvolatile memory.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices have been developed. For example, a non-volatile Memory NAND Flash (NAND Flash Memory) is taken as an example, and the NAND Flash stores data by performing read-write operation on a Memory cell (Memory cell), has the advantages of high rewriting speed, large storage capacity and the like, and is widely used in electronic products. In the erasing operation of the nonvolatile memory, erasing is usually performed in Block (memory Block) units
In the prior art, when performing an erase operation, a nonvolatile memory first applies an erase pulse to a memory block to be erased, and then verifies whether the memory block to be erased completes the erase operation.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: if the memory block to be erased is already in an erased state, the prior art method of applying the erase pulse may cause the memory block to be erased to receive an erase pulse which is meaningless once, and the erase pulse may affect the lifetime of the memory block to be erased, resulting in a short lifetime of the nonvolatile memory.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present invention provide a method and an apparatus for erasing a nonvolatile memory, so as to prolong the service life of the nonvolatile memory.
According to a first aspect of the present invention, there is provided a nonvolatile memory erase processing method, the method comprising:
verifying the erasing state of the memory block to be erased;
and when the memory block to be erased is in an erased state, applying no erasing pulse to the memory block to be erased.
Optionally, the method further includes:
and applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an unerased state.
Optionally, the applying an erase pulse to the memory block to be erased includes:
applying a first erasing pulse to the memory block to be erased;
verifying the erasing state of the memory block to be erased;
applying a second erasing pulse to the memory block to be erased under the condition that the erasing state of the memory block to be erased is an unerased state until the memory block to be erased is in an erased state; wherein the second erase pulse is: a sum of the first erase pulse and a preset voltage increment.
Optionally, the erased state is: and all the memory cells in the memory block to be erased are in a high level state.
Optionally, the non-erased state is: among the memory cells of the memory block to be erased, there are memory cells in a low level state.
According to a second aspect of the present invention, there is provided a nonvolatile memory erase processing apparatus, the apparatus including:
the verification module is used for verifying the erasing state of the memory block to be erased;
the selection module is used for not applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an erased state.
Optionally, the method further includes: and the erasing module is used for applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an un-erased state.
Optionally, the erasing module includes:
the first erasing pulse applying submodule is used for applying a first erasing pulse to the memory block to be erased;
the verification submodule is used for verifying the erasing state of the storage block to be erased;
the second erasing pulse applying submodule is used for applying a second erasing pulse to the memory block to be erased under the condition that the erasing state of the memory block to be erased is an unerased state until the memory block to be erased is in an erased state; wherein the second erase pulse is: a sum of the first erase pulse and a preset voltage increment.
Optionally, the erased state is: and all the memory cells in the memory block to be erased are in a high level state.
Optionally, the non-erased state is: among the memory cells of the memory block to be erased, there are memory cells in a low level state.
In the embodiment of the invention, when the erasing operation is carried out on the to-be-erased storage block in the nonvolatile storage, the erasing state of the to-be-erased storage block is verified firstly, and under the condition that the to-be-erased storage block is in the erased state, the erasing pulse is not applied to the to-be-erased storage block, so that the to-be-erased storage block in the erased state does not need to bear the meaningless erasing pulse, and the service life of the nonvolatile storage can be prolonged.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart of a method for erasing a non-volatile memory according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for erasing a non-volatile memory according to an embodiment of the present invention;
FIG. 3 is a block diagram of an apparatus for erasing a non-volatile memory according to an embodiment of the present invention;
fig. 4 is a specific block diagram of a nonvolatile memory erasing processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 1, a flowchart of a nonvolatile memory erasing processing method is shown, which may specifically include the following steps:
step 101: and verifying the erasing state of the memory block to be erased.
In the embodiment of the invention, before the erasing operation is carried out on the memory block to be erased in the nonvolatile memory, the erasing state of the memory block to be erased can be verified. In specific application, the signal state of each storage unit in the storage block to be erased can be read, and if each storage unit is in a high-level state, the storage block to be erased can be indicated to be in an erased state, and repeated erasing operation is not needed; if the memory cell in the low leveling state exists in each memory cell, it can be said that the memory block to be erased is in the un-erased state, and an erase operation is required.
Step 102: and when the memory block to be erased is in an erased state, applying no erasing pulse to the memory block to be erased.
In the embodiment of the invention, under the condition that the memory block to be erased is in an erased state, the erasing pulse is not applied to the memory block to be erased, so that the module to be erased in the erased state does not need to receive meaningless erasing pulse, and the damage of excessive erasing pulse to the performance of the module to be erased is avoided.
In specific application, the voltage value corresponding to the erasing pulse can be set according to an actual application scene, and only the erasing operation of the memory block to be erased can be realized through the erasing pulse; it can be understood that the erase pulse with a high voltage value may cause a loss of performance of the memory block to be erased, and therefore, in order to avoid an excessive loss of performance of the memory block to be erased, the voltage value corresponding to the erase pulse may be set to a lower value, for example, a minimum voltage value at which the memory block to be erased can be achieved, so that the lifetime of the nonvolatile memory can be prolonged.
In summary, in the embodiments of the present invention, when performing an erase operation on a to-be-erased memory block in a nonvolatile memory, an erase state of the to-be-erased memory block is verified first, and when the to-be-erased memory block is in an erased state, an erase pulse is not applied to the to-be-erased memory block, so that the to-be-erased memory block in the erased state does not need to bear an erase pulse that is meaningless, and thus the life of the nonvolatile memory can be prolonged.
Example two
Referring to fig. 2, a specific flowchart of a nonvolatile memory erase processing method is shown, which may specifically include the following steps:
step 201: and verifying the erasing state of the memory block to be erased.
Step 202: and when the memory block to be erased is in an erased state, applying no erasing pulse to the memory block to be erased.
Step 203: and applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an unerased state.
In the embodiment of the present invention, the erased state may be defined as: all the storage units in the storage block to be erased are in a high level state; the non-erased state is: among the memory cells of the memory block to be erased, there are memory cells in a low level state.
In a specific application, under the condition that the memory block to be erased is in an unerased state, it is described that an erasing operation needs to be performed on the memory block to be erased, so that an erasing pulse can be applied to the memory block to be erased, it can be understood that the operation of applying the erasing pulse can be performed by applying a larger erasing pulse at a time to erase the memory block to be erased, or by applying a smaller erasing pulse first and then verifying whether the smaller erasing pulse can erase the memory block to be erased, if not, a voltage increment can be set, and until the memory block to be erased is erased, the voltage increment is increased in a stepped manner. The embodiment of the present invention does not limit the specific manner of applying the erase pulse.
As a specific implementation manner of the embodiment of the present invention, the applying of the erase pulse to the memory block to be erased includes:
substep a1 (not shown): and applying a first erasing pulse to the memory block to be erased.
Substep a2 (not shown): and verifying the erasing state of the memory block to be erased.
Substep a3 (not shown): applying a second erasing pulse to the memory block to be erased under the condition that the erasing state of the memory block to be erased is an unerased state until the memory block to be erased is in an erased state; wherein the second erase pulse is: a sum of the first erase pulse and a preset voltage increment.
In the embodiment of the present invention, through sub-steps a1 to A3, a lower first erase pulse is applied to a memory block to be erased, then the erase state of the memory block to be erased is verified, if the memory block to be erased is in an erased state, the erase operation may be ended, if the erase state of the memory block to be erased is in an un-erased state, it indicates that the first erase pulse is too small to complete the erase operation of the memory block to be erased, and therefore a second erase pulse needs to be applied to the memory block to be erased, the second erase pulse is the sum of the first erase pulse and a preset voltage increment, in a specific application, the preset voltage increment may be set according to an actual application scenario, it can be understood that, in order to avoid the second erase pulse being too high and causing damage to the memory block to be erased, the preset voltage increment may be set to a smaller value, by a manner of raising the erase pulse in a staircase manner, the erasing of the memory block to be erased is realized, and it can be understood that the erasing pulse for realizing the erasing of the memory block to be erased is close to the erasing critical pulse of the memory block to be erased, that is, the lowest erasing pulse value for realizing the erasing operation of the memory block to be erased, so that the loss of the memory block to be erased caused by an excessively high erasing pulse can be avoided, and the service life of the nonvolatile memory can be prolonged.
In a specific application, the adjustment of the erase pulse may be implemented by modifying a voltage corresponding value of a register corresponding to the erase pulse, and it can be understood that a person skilled in the art may also adjust the erase pulse in other ways according to an actual application scenario, which is not specifically limited in this embodiment of the present invention.
In summary, in the embodiments of the present invention, when performing an erase operation on a to-be-erased memory block in a nonvolatile memory, an erase state of the to-be-erased memory block is verified first, and when the to-be-erased memory block is in an erased state, an erase pulse is not applied to the to-be-erased memory block, so that the to-be-erased memory block in the erased state does not need to bear an erase pulse that is meaningless, and thus the life of the nonvolatile memory can be prolonged.
EXAMPLE III
Referring to fig. 3, a block diagram of a nonvolatile memory erase processing apparatus is shown, which may specifically include:
the verifying module 310 is configured to verify an erase state of a memory block to be erased;
a selecting module 320, configured to not apply an erase pulse to the memory block to be erased if the memory block to be erased is in an erased state.
Preferably, referring to fig. 4, on the basis of fig. 3, the apparatus further comprises:
the erasing module 330 is configured to apply an erasing pulse to the memory block to be erased when the memory block to be erased is in an unerased state.
Optionally, the erasing module 330 includes:
the first erasing pulse applying submodule is used for applying a first erasing pulse to the memory block to be erased;
the verification submodule is used for verifying the erasing state of the storage block to be erased;
the second erasing pulse applying submodule is used for applying a second erasing pulse to the memory block to be erased under the condition that the erasing state of the memory block to be erased is an unerased state until the memory block to be erased is in an erased state; wherein the second erase pulse is: a sum of the first erase pulse and a preset voltage increment.
Optionally, the erased state is: and all the memory cells in the memory block to be erased are in a high level state.
Optionally, the non-erased state is: among the memory cells of the memory block to be erased, there are memory cells in a low level state.
In the embodiment of the invention, when the erasing operation is carried out on the to-be-erased storage block in the nonvolatile storage, the erasing state of the to-be-erased storage block is verified firstly, and under the condition that the to-be-erased storage block is in the erased state, the erasing pulse is not applied to the to-be-erased storage block, so that the to-be-erased storage block in the erased state does not need to bear the meaningless erasing pulse, and the service life of the nonvolatile storage can be prolonged.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
In a typical configuration, the computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory. The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium. Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), electrically-processable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (fransitory media), such as modulated data signals and carrier waves.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable nonvolatile memory erasure processing terminal apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable nonvolatile memory erasure processing terminal apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable non-volatile memory erase processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable non-volatile memory erase processing terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The present invention provides a nonvolatile memory erase processing method and a nonvolatile memory erase processing apparatus, which have been described in detail above, and the principle and the implementation of the present invention are explained herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method of non-volatile memory erase processing, the method comprising:
verifying the erasing state of the memory block to be erased;
and when the memory block to be erased is in an erased state, applying no erasing pulse to the memory block to be erased.
2. The method of claim 1, further comprising:
and applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an unerased state.
3. The method of claim 2, wherein the applying an erase pulse to the memory block to be erased comprises:
applying a first erasing pulse to the memory block to be erased;
verifying the erasing state of the memory block to be erased;
applying a second erasing pulse to the memory block to be erased under the condition that the erasing state of the memory block to be erased is an unerased state until the memory block to be erased is in an erased state; wherein the second erase pulse is: a sum of the first erase pulse and a preset voltage increment.
4. The method of claim 1, wherein the erased state is: and all the memory cells in the memory block to be erased are in a high level state.
5. The method of any of claims 2 to 4, wherein the unerased state is: among the memory cells of the memory block to be erased, there are memory cells in a low level state.
6. A nonvolatile memory erase processing apparatus, characterized in that the apparatus comprises:
the verification module is used for verifying the erasing state of the memory block to be erased;
the selection module is used for not applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an erased state.
7. The apparatus of claim 6, further comprising:
and the erasing module is used for applying an erasing pulse to the memory block to be erased under the condition that the memory block to be erased is in an un-erased state.
8. The apparatus of claim 7, wherein the erase module comprises:
the first erasing pulse applying submodule is used for applying a first erasing pulse to the memory block to be erased;
the verification submodule is used for verifying the erasing state of the storage block to be erased;
the second erasing pulse applying submodule is used for applying a second erasing pulse to the memory block to be erased under the condition that the erasing state of the memory block to be erased is an unerased state until the memory block to be erased is in an erased state; wherein the second erase pulse is: a sum of the first erase pulse and a preset voltage increment.
9. The apparatus of claim 6, wherein the erased state is: and all the memory cells in the memory block to be erased are in a high level state.
10. The apparatus of any of claims 7 to 9, wherein the unerased state is: among the memory cells of the memory block to be erased, there are memory cells in a low level state.
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| CN101079320A (en) * | 2006-05-24 | 2007-11-28 | 富士通株式会社 | Non-volatile semiconductor memory device, erase method for same, and test method for same |
| JP2008293616A (en) * | 2007-05-28 | 2008-12-04 | Sharp Corp | Erasing method for nonvolatile semiconductor memory |
| CN102136295A (en) * | 2011-04-22 | 2011-07-27 | 上海宏力半导体制造有限公司 | Data wiping method for NOR flash memory |
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