CN105976867A - Erasing method for storage units - Google Patents
Erasing method for storage units Download PDFInfo
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- CN105976867A CN105976867A CN201610529412.3A CN201610529412A CN105976867A CN 105976867 A CN105976867 A CN 105976867A CN 201610529412 A CN201610529412 A CN 201610529412A CN 105976867 A CN105976867 A CN 105976867A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000003860 storage Methods 0.000 title claims abstract description 22
- 238000012795 verification Methods 0.000 claims abstract description 17
- 238000007689 inspection Methods 0.000 claims description 11
- 230000014759 maintenance of location Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Abstract
The invention discloses an erasing method for storage units. The method comprises: according to an erasing instruction, carrying out an erasing operation on a plurality of storage units corresponding to a current erasing block address; carrying out erasing verification on each storage unit corresponding to the erasing block address, checking if a current state of each storage unit is a successful erasing state, ending the current erasing operation if yes, or increasing a pulse width of an erasing voltage and returning to execute the erasing operation carried out on the plurality of storage units corresponding to the current erasing block address until each storage unit corresponding to each erasing block address is successfully erased. According to the erasing method for the storage units which is provided by the embodiment of the invention, by continuously increasing the pulse width of the erasing voltage along with increase of erasing times, rapid erasion on the storage units is implemented, and an erasing speed is improved.
Description
Technical field
The present embodiments relate to technical field of memory, be specifically related to the method for deleting of a kind of memory element.
Background technology
Nonvolatile flash memory medium (nor flash/nand flash) is the most common a kind of storage chip, have concurrently with
Machine memorizer (Random Access Memory, RAM) and read only memory (Read-Only Memory,
ROM) advantage, data power down will not lose, and is a kind of can to carry out, in system, the memorizer that electricity is erasable, with
Time its high integration and low cost make it the market mainstream.Flash chip is to be deposited by thousands of of inside
Storage unit composition, each storage element storage a data, multiple memory element constitute page, multiple pages of groups
In bulk, just because of the physical arrangement that this is special, is to carry out in units of page in nor flash/nand flash
Read/write (erasing operation) data, carry out wiping data in units of block.
In Flash chip, a memory element can see a metal oxide semiconductcor field effect transistor as
(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET).Fig. 1 is a kind of common
MOSFET structure figure, including grid 20, source electrode 21, drain electrode 22, p-type trap 23, N-type trap 25,
P-type silicon Semiconductor substrate 26 and tunnel oxide 24, its mutual connection is: P-type silicon quasiconductor serves as a contrast
The end 26, diffuses out two N-type region, covers one layer of tunnel oxide 24, finally in N-type above p-type trap 23
Make two holes by the method for corrosion above district, distinguished the most on the insulating layer and two by metallized method
Three electrodes are made: grid 20, source electrode 21 and drain electrode 22, source electrode 21 is the most corresponding with drain electrode 22 in hole
Two N-type region and grid 20 are the wordline of memory element, and drain electrode 22 is the bit line of memory element.Further
, grid 20 include again control gate 201, IPD 202 (Inter-Poly Dielectric,
IPD), floating grid 203, and floating grid 203 can store electric charge.When a memory element is wiped
During division operation, apply corresponding erasing voltage, when p-type trap 23 to respectively grid 20 and p-type trap 23
Electronics when reaching some, this memory element is just wiped free of successfully, i.e. this memory element is successfully write 1.
But, due to the problem of Flash chip processing technology, have some memory element and be difficult to be wiped free of, existing
Solution is: in order to ensure the correctness of erasing, increase erasing times, but but to sacrifice erasing speed
For cost.
Therefore, it is necessary to design the method for deleting of a kind of new memory element, to improve erasing speed.
Summary of the invention
The present invention provides the method for deleting of a kind of memory element, to improve erasing speed.The method includes:
According to erasing instruction, multiple memory element that current erasure block address is corresponding are carried out erasing to operate；
Each memory element that described erasing block address is corresponding is carried out erasing verification, inspection described each
Whether the current state of memory element is to have wiped successfully, the most then terminate current erasure operation, otherwise
Increase the pulse width of erasing voltage, and return the described multiple storages corresponding to current erasure block address of execution
Erasing that unit is carried out operation, until each memory element corresponding to described erasing block address is wiped successfully.
Further, the pulse width of described increase erasing voltage, including:
The pulse width of described erasing voltage increases according to equation below:
Ti=T0+ (N-1) * Δ t
Wherein, TiRepresent and multiple memory element that described current erasure block address is corresponding are carried out i & lt erasing
Time corresponding erasing voltage pulse width, T0 represents the initial pulse width of erasing voltage, and N represents institute
Stating the number of times that multiple memory element corresponding to current erasure block address carry out wiping, Δ t represents the increasing of pulse width
Dosage.
Further, before increasing the pulse width of erasing voltage, also include:
By erasing enumerator multiple memory element that described current erasure block address is corresponding wipes unsuccessfully secondary
Number adds up；
Judge whether the described erasing frequency of failure is to preset the erasing frequency of failure, the most then terminate erasing operation,
Otherwise perform to increase the operation of the pulse width of erasing voltage.
Preferably, the described default erasing frequency of failure is the positive integer less than or equal to 2000.
Further, after multiple memory element that described current erasure block address is corresponding are wiped successfully, also
Including:
Judge whether described current erasure block address is last erasing block address, if then exiting erasing operation,
Otherwise change described current erasure block address, continue other erasing block carries out erasing operation, and wipe
Except verification, until all of memory element completes erasing operation.
Exemplarily, described erasing operation includes:
Erasing voltage is applied respectively to grid and the p-well of described memory element.
Exemplarily, the erasing voltage scope applied to the grid of described memory element is-7V to-10V, to described
The erasing voltage scope that the p-well of memory element applies is 6V to 10V.
Exemplarily, whether the current state of each memory element described in described inspection is to have wiped successfully,
Particularly as follows:
Detect whether the current value flowing to drain from the source electrode of memory element is more than pre-set current value, the most described
The current state of memory element is for have wiped successfully.
The method for deleting of a kind of memory element that the embodiment of the present invention provides, first according to erasing instruction to currently
Wipe multiple memory element corresponding to block address and carry out erasing operation, then corresponding to described erasing block address
Each memory element carries out erasing verification, and whether the current state of inspection each memory element described is
Erased success, the most then terminate current erasure operation, otherwise increase the pulse width of erasing voltage, and
Return and perform the described erasing that multiple memory element that current erasure block address is corresponding are carried out operation, until institute
Each memory element stating erasing block address corresponding is wiped successfully.Corresponding many to current erasure block address
After individual memory element carries out wiping operation for the first time, without wiping successfully, when the most again it being wiped
Increase the pulse width of erasing voltage, by along with the pulse increasing constantly increase erasing voltage of erasing times
Width, it is achieved that the quick erasing to memory element, improves erasing speed.
Accompanying drawing explanation
Fig. 1 is the knot of a kind of metal oxide semiconductcor field effect transistor as memory element in Flash chip
Composition；
Fig. 2 is the method for deleting flow chart of a kind of memory element in the embodiment of the present invention one；
Fig. 3 is the method for deleting flow chart of a kind of memory element in the embodiment of the present invention two；
Fig. 4 is the method for deleting flow chart of a kind of memory element in the embodiment of the present invention three.
Detailed description of the invention
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that this
Specific embodiment described by place is used only for explaining the present invention, rather than limitation of the invention.The most also need
It is noted that for the ease of describing, accompanying drawing illustrate only part related to the present invention and not all knot
Structure.
Embodiment one
The method for deleting flow chart of a kind of memory element that Fig. 2 provides for the embodiment of the present invention one, the present embodiment
It is applicable to that some are difficult to be wiped free of successful memory element and carries out erasing operation.See Fig. 2, this enforcement
The method for deleting of memory element that example provides specifically includes following steps:
S110, according to erasing instruction multiple memory element that current erasure block address is corresponding are carried out erasing operation.
In the present embodiment, the memory cell array of described current erasure block concretely flash memory needs
Carry out a memory cell block of erasing operation.The memory cell array of each flash memory is deposited by multiple
Storage unit block forms, and described memory cell block is made up of multiple memory element pages, and described memory element page is by many
Individual memory element connects composition with ranks.In a memory element page, often go by multiple memory element with word
Line connects, and each column is connected with bit line by multiple memory element, and a memory element page shares a wordline,
One memory cell block shares a bit line, and in i.e. one memory cell block, the p-well of all memory element is even
Together.The described erasing operation of the specific physical structures shape of flash memory must be with memory cell block
Carry out for unit.
Flash memory can be controlled by coding code and carry out three big primary operational, be respectively read operation,
Write operation and erasing operation, wherein erasing operation specifically completes to write memory element 1 operation.To storage
It is by applying corresponding to the grid of memory element and p-well respectively that unit carries out the ultimate principle of erasing operation
Erasing voltage, have after applying described erasing voltage electric current from source electrode flow to drain electrode, electronics from drain electrode flow to
In the way of source electrode, understand some and flow to p-well, when the electronics in p-well reaches some, this storage
Unit is just wiped free of successfully, i.e. this memory element is successfully write 1.The essence of erasing operation is by storage
The p-well of unit accumulates a certain amount of electronics, thus the threshold voltage of memory element is pulled down to setting value, complete
Become the erasing operation of memory element.The concrete structure of memory element may refer to the structural representation shown in Fig. 1.
Exemplarily, described erasing operation can be specifically to apply to grid and the p-well of described memory element respectively
Erasing voltage.Typically, the erasing voltage applied to the grid of described memory element can be between-7V to-10V
Any number, the erasing voltage applied to the p-well of described memory element can be any between 6V to 10V
Numerical value.As it is known by the man skilled in the art that the voltage range-7V to-10V-on the grid being applied to memory element
And voltage range 6V to the 10V being applied in the p-well of memory element is preferred exemplary value scope,
And be not limited thereof.
S120, each memory element that described erasing block address is corresponding carrying out erasing verification, inspection is described
Whether the current state of each memory element is to have wiped successfully, the most then perform step S130 and terminate
Current erasure operates, and otherwise performs step S140, the pulse width of increase erasing voltage, and returns execution institute
State the erasing operation that multiple memory element that current erasure block address is corresponding are carried out, until described erasing block ground
Each memory element corresponding to location is wiped successfully.
Wherein, the essence that described memory element carries out erasing verification is once to read described memory element
Operation, more specifically can be understood as whether inspection numerical value of reading from described memory element is 1, if
It is 1 and illustrates that described memory element has been wiped successfully that otherwise failure needs again to carry out erasing operation.
It should be noted that carrying out flash memory wiping operation is to carry out in units of a memory cell block,
Multiple memory element in described memory cell block can be simultaneously erased, but after often completing once to wipe operation,
Need the multiple memory element in described piece to carry out erasing verification respectively, to check each memory element
Whether current state is to have wiped successfully.
Exemplarily, whether the current state of each memory element described in described inspection is to have wiped successfully,
Particularly as follows:
Detect whether the current value flowing to drain from the source electrode of memory element is more than pre-set current value, the most described
The current state of memory element is for have wiped successfully.Now think there has been abundance in the p-well of memory element
Electronics, now the state of memory element is 1.Preferably, described pre-set current value can be 20 μ A or 30 μ A,
Certainly can also is that other numerical value, need the difference of the processing technology according to each flash chip to change.
When run into erasing certain memory element corresponding to block address wipe unsuccessfully when, traditional method for deleting is
Ensure that this memory element is wiped successfully by increasing erasing times, but but sacrifice erasing speed.This reality
Executing the technical scheme of example for the way of this kind of situation is, when in the memory element that described erasing block address is corresponding
When failed memory element is wiped in existence, i.e. erasing verification is not passed through, then the storage list corresponding to this erasing block
Unit carries out increasing when second time wipes operation the pulse width of erasing voltage, after operating through second time erasing,
When carrying out erasing verification, still there is the storage that erasing verification is not passed through in the memory element that described erasing block is corresponding
Unit, then continue to increase the pulse width of erasing voltage, even if the pulse width of described erasing voltage is along with wiping
It is continuously increased except the increase of number of times.
Typically, the pulse width of the erasing voltage every time increased can be 0.5 μ s, described erasing voltage
After pulse width increases, can increase from the persistent period of the electric current of source electrode flow direction drain electrode, correspondingly, have more
Many time allows electronics flow to flow to p-well the way of source electrode from drain electrode, and the electrons in p-well reaches quickly
Set quantity, and then described memory element can be wiped successfully quickly, improve erasing speed.
S130, end current erasure operation.
S140, the pulse width of increase erasing voltage, and it is described corresponding to current erasure block address to return execution
The erasing operation that carries out of multiple memory element, until each memory element that described erasing block address is corresponding
Wipe successfully.
The method for deleting of a kind of memory element that the embodiment of the present invention provides, first according to erasing instruction to currently
Wipe multiple memory element corresponding to block address and carry out erasing operation, then corresponding to described erasing block address
Each memory element carries out erasing verification, and whether the current state of inspection each memory element described is
Erased success, the most then terminate current erasure operation, otherwise increase the pulse width of erasing voltage, and
Return and perform the described erasing that multiple memory element that current erasure block address is corresponding are carried out operation, until institute
Each memory element stating erasing block address corresponding is wiped successfully.Corresponding many to current erasure block address
After individual memory element carries out wiping operation for the first time, without wiping successfully, when the most again it being wiped
Increase the pulse width of erasing voltage, by along with the pulse increasing constantly increase erasing voltage of erasing times
Width, it is achieved that the quick erasing to memory element, improves erasing speed.
Embodiment two
The method for deleting flow chart of a kind of memory element that Fig. 3 provides for the embodiment of the present invention two, the present embodiment
Optimize further on the basis of embodiment one, before increasing the pulse width of erasing voltage, increase
: by erasing enumerator multiple memory element that described current erasure block address is corresponding wipes unsuccessfully secondary
Number carries out the operations that add up, the so benefit of optimization, it is to avoid to corresponding multiple of current erasure block address
Memory element unrestrictedly wipes operation, makes whole program be absorbed in endless loop.See Fig. 3, this enforcement
The method for deleting of memory element that example provides specifically includes following steps:
S210, according to erasing instruction multiple memory element that current erasure block address is corresponding are carried out erasing operation.
S220, each memory element that described erasing block address is corresponding carrying out erasing verification, inspection is described
Whether the current state of each memory element is to have wiped successfully.
S230, the most then terminate current erasure operation.
S240, otherwise, by multiple memory element that erasing enumerator is corresponding to described current erasure block address
Wipe failed number of times to add up.
Aforesaid operations is primarily directed to when a memory element is through repeatedly wiping operation still not over erasing
The situation of verification, in order to prevent program from entering in the endless loop of " erasing-erasing verification-erasing ", arranges erasing
Enumerator adds up wiping failed number of times, specifically refers to that current erasure block is wiped failed number of times and enters
Row counting.
S250, judge that whether the described erasing frequency of failure is to preset the erasing frequency of failure, the most then return step
Rapid S230 terminates erasing operation.
Set one for each erasing block and allow the number of times that erasing is failed, when the erasing failure time to certain erasing block
Number reaches described when allowing the failed number of times of erasing, the most then compulsory withdrawal erasing operates, no longer to this erasing
Block carries out erasing operation, continues other erasing blocks to not carrying out erasing operation in erasing region and wipes
Operation.Typically, the described default erasing frequency of failure is the positive integer less than or equal to 2000.Certainly,
Those skilled in the art both knows about, the described default erasing frequency of failure be not limited to some or certain some
Fixed numbers, needs to select suitable numerical value according to the processing technology of practical operation situation and flash chip.
S260, otherwise increase the pulse width of erasing voltage, and return execution step S210, until described wiping
Each memory element corresponding except block address is wiped successfully.
Exemplarily, the pulse width of described increase erasing voltage, specifically may include that
The pulse width of described erasing voltage increases according to equation below:
Ti=T0+ (N-1) * Δ t
Wherein, TiRepresent and multiple memory element that described current erasure block address is corresponding are carried out i & lt erasing
Time corresponding erasing voltage pulse width, T0 represents the initial pulse width of erasing voltage, and N represents institute
Stating the number of times that multiple memory element corresponding to current erasure block address carry out wiping, Δ t represents the increasing of pulse width
Dosage.
The method for deleting of a kind of memory element that the embodiment of the present invention provides, at the pulse width increasing erasing voltage
Before degree, by erasing enumerator multiple memory element that current erasure block address is corresponding wipes unsuccessfully secondary
Number adds up, and judges whether the described erasing frequency of failure is to preset the erasing frequency of failure, the most then tie
Bundle erasing operation, otherwise performs to increase the operation of the pulse width of erasing voltage, continues current erasure block ground
Multiple memory element corresponding to location carry out erasing operation, until wiping successfully.By arranging erasing enumerator,
Achieve the endless loop preventing program from entering " erasing-erasing verification-erasing ".
Embodiment three
The method for deleting flow chart of a kind of memory element that Fig. 4 provides for the embodiment of the present invention three, the present embodiment
Optimize further on the basis of the various embodiments described above, add and judge that described current erasure block address is
The no operation for last erasing block address, the benefit so optimized is can to quickly complete whole wiping
Except the erasing in region operates.Seeing Fig. 4, the method for deleting of the memory element that the present embodiment provides specifically includes
Following steps:
S310, according to erasing instruction multiple memory element that current erasure block address is corresponding are carried out erasing operation.
S320, each memory element that described erasing block address is corresponding carrying out erasing verification, inspection is described
Whether the current state of each memory element is to have wiped successfully, if then performing step S330, otherwise
Perform step S360.
S330, judge whether described current erasure block address is last erasing block address, the most then perform
Step S340, otherwise performs step S350.
S340, end current erasure operation.
S350, change described current erasure block address, and return execution step S310, continue new erasing
When block carries out erasing operation.
S360, the pulse width of increase erasing voltage, and return execution step S310, until wiping successfully.
The method for deleting of a kind of memory element that the embodiment of the present invention provides, on the basis of the various embodiments described above,
When the multiple memory element checking current erasure block address corresponding are wiped successfully, it is judged that described current erasure block
Whether address is last erasing block address, if then exiting erasing operation, otherwise changes described current erasure
Block address, continues other erasing block carries out erasing operation, and carries out erasing verification, until erasing region
Interior all of erasing block completes erasing operation.Achieve the erasing that can quickly complete whole erasing region
Operation.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.Those skilled in the art
It will be appreciated that the invention is not restricted to specific embodiment described here, can enter for a person skilled in the art
Row various obvious changes, readjust and substitute without departing from protection scope of the present invention.Therefore, though
So by above example, the present invention is described in further detail, but the present invention be not limited only to
Upper embodiment, without departing from the inventive concept, it is also possible to include other Equivalent embodiments more,
And the scope of the present invention is determined by scope of the appended claims.
Claims (8)
1. the method for deleting of a memory element, it is characterised in that including:
According to erasing instruction, multiple memory element that current erasure block address is corresponding are carried out erasing to operate；
Each memory element that described erasing block address is corresponding is carried out erasing verification, inspection described each
Whether the current state of memory element is to have wiped successfully, the most then terminate current erasure operation, otherwise
Increase the pulse width of erasing voltage, and return the described multiple storages corresponding to current erasure block address of execution
Erasing that unit is carried out operation, until each memory element corresponding to described erasing block address is wiped successfully.
Method the most according to claim 1, it is characterised in that the pulse width of described increase erasing voltage,
Including:
The pulse width of described erasing voltage increases according to equation below:
Ti=T0+ (N-1) * Δ t
Wherein, TiRepresent and multiple memory element that described current erasure block address is corresponding are carried out i & lt erasing
Time corresponding erasing voltage pulse width, T0 represents the initial pulse width of erasing voltage, and N represents institute
Stating the number of times that multiple memory element corresponding to current erasure block address carry out wiping, Δ t represents the increasing of pulse width
Dosage.
Method the most according to claim 1, it is characterised in that increase erasing voltage pulse width it
Before, also include:
By erasing enumerator multiple memory element that described current erasure block address is corresponding wipes unsuccessfully secondary
Number adds up；
Judge whether the described erasing frequency of failure is to preset the erasing frequency of failure, the most then terminate erasing operation,
Otherwise perform to increase the operation of the pulse width of erasing voltage.
Method the most according to claim 3, it is characterised in that the described default erasing frequency of failure is little
In or equal to 2000 positive integer.
Method the most according to claim 1, it is characterised in that corresponding to described current erasure block address
Multiple memory element wipe successfully after, also include:
Judge whether described current erasure block address is last erasing block address, if then exiting erasing operation,
Otherwise change described current erasure block address, continue other erasing block carries out erasing operation, and wipe
Except verification, until all of memory element completes erasing operation.
6. according to the arbitrary described method of claim 1-5, it is characterised in that described erasing operation includes:
Erasing voltage is applied respectively to grid and the p-well of described memory element.
Method the most according to claim 6, it is characterised in that the wiping applied to the grid of described memory element
Except voltage range is-7V to-10V, the erasing voltage scope applied to the p-well of described memory element is 6V to 10V.
8. according to the arbitrary described method of claim 1-5, it is characterised in that described in described inspection, each is deposited
Whether the current state of storage unit is to have wiped successfully, particularly as follows:
Detect whether the current value flowing to drain from the source electrode of memory element is more than pre-set current value, the most described
The current state of memory element is for have wiped successfully.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106782651A (en) * | 2017-01-05 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of method for deleting of flash memory |
| CN106971760A (en) * | 2017-04-01 | 2017-07-21 | 北京兆易创新科技股份有限公司 | Threshold voltage method of calibration, device and NAND memory device based on nand flash memory |
| CN109119108A (en) * | 2018-08-15 | 2019-01-01 | 杭州阿姆科技有限公司 | A method of improving the Nand service life |
| CN109390016A (en) * | 2017-08-10 | 2019-02-26 | 北京兆易创新科技股份有限公司 | The method for deleting and device of NOR type flash memory |
| CN109542345A (en) * | 2018-11-16 | 2019-03-29 | 广州锦红源电子科技有限公司 | The data write-in of flash storage and read method, device |
| CN109979510A (en) * | 2017-12-27 | 2019-07-05 | 北京兆易创新科技股份有限公司 | A kind of method, apparatus reducing non-volatile flash memory block erasing operation leakage current |
| CN111951862A (en) * | 2019-05-14 | 2020-11-17 | 北京兆易创新科技股份有限公司 | Nonvolatile memory erasing processing method and device |
| CN112542203A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | Bad block repairing method and device for nonvolatile memory, storage medium and terminal |
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