CN107665724A - A kind of method for deleting of memory cell - Google Patents
A kind of method for deleting of memory cell Download PDFInfo
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- CN107665724A CN107665724A CN201610602969.5A CN201610602969A CN107665724A CN 107665724 A CN107665724 A CN 107665724A CN 201610602969 A CN201610602969 A CN 201610602969A CN 107665724 A CN107665724 A CN 107665724A
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- Prior art keywords
- erasing
- memory cell
- voltage
- current erasure
- verification
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Abstract
The invention discloses a kind of method for deleting of memory cell, this method includes：Erasing verification is carried out to memory cell corresponding to current erasure address；Judge whether the erasing verification succeeds, if not, erasing operation is carried out to memory cell corresponding to current erasure address using based on setting voltage steps ladder type incremental initial erasing voltage, and the operation for performing and to memory cell corresponding to current erasure address wipe verification is returned, until wiping successfully.The method for deleting of memory cell provided in an embodiment of the present invention, erasing operation is carried out to memory cell corresponding to current erasure address by using based on setting voltage steps ladder type incremental initial erasing voltage, destructive influences caused by reducing the memory cell more active to electronics, improve the reliability of flash products.
Description
Technical field
The present embodiments relate to technical field of memory, and in particular to a kind of method for deleting of memory cell.
Background technology
Nonvolatile flash memory medium (nor flash/nand flash) is a kind of very common storage chip, has concurrently and deposits at random
Reservoir (Random Access Memory, RAM) and the advantages of read-only storage (Read-Only Memory, ROM), data are fallen
Electricity will not be lost, be it is a kind of can carry out the erasable memory of electricity in system, while its high integration and low cost make it
The market mainstream.Flash chip is made up of internal thousands of individual memory cell, and each storage element stores a data,
Multiple memory cell form page, multiple pages of blockings, just because of the special physical arrangement, in nor flash/nand
It is progress read/write (erasing operation) data in units of page in flash, carries out wiping data in units of block.
In flash chip, a memory cell can see a metal oxide semiconductcor field effect transistor as
(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET).Fig. 1 is a kind of common
MOSFET structure figure, including grid 20, source electrode 21, drain electrode 22, p-type trap 23, N-type trap 25, P-type silicon Semiconductor substrate 26 and tunnel
Oxide layer 24 is worn, its mutual connection is：P-type silicon Semiconductor substrate 26 diffuses out two N-type regions, and the top of p-type trap 23 covers
One layer of tunnel oxide 24, two holes are finally made by the method for corrosion above N-type region, distinguished by the method for metallization
Three electrodes are made on the insulating layer and in two holes：Grid 20, source electrode 21 and drain electrode 22, source electrode 21 and drain electrode 22 correspond to respectively
Two N-type regions and grid 20 are the wordline of memory cell, and drain electrode 22 is the bit line of memory cell.Further, grid 20 wraps again
Control gate 201, IPD 202 (Inter-Poly Dielectric, IPD), floating grid 203 are included, and it is floating
Moving grid pole 203 can store electric charge.When carrying out erasing operation to a memory cell, respectively to grid 20 and p-type trap 23
Apply corresponding erasing voltage, when the electronics of p-type trap 23 reaches certain amount, this memory cell is just wiped free of success, i.e., this
Memory cell is successfully write 1.Existing method for deleting is：Erasing operation is carried out using identical erasing voltage every time, until
Wipe successfully.But the problem of due to flash chip manufacture craft, it is preceding wipe several times when, have some memory cell
Electronics it is more active, if apply the memory cell that stronger erasing voltage can be more active to these electronics produce it is destructive
Influence, such as by memory cell puncture etc., greatly affected the reliability of flash products.And memory cell is being passed through
After the erasing operation of certain number, it can more be not easy to wipe successfully, if also carried out using erasing voltage as before
Erasing, the overall time of erasing can be had a strong impact on.
Therefore, it is necessary to a kind of method for deleting of new memory cell is designed, to improve the reliability of flash products, and
Shorten the overall erasing time.
The content of the invention
The present invention provides a kind of method for deleting of memory cell, to improve the reliability of flash products, and shortens overall
Erasing time.This method includes：
Erasing verification is carried out to memory cell corresponding to current erasure address；
Judge whether the erasing verification succeeds, if it is not, using based on the incremental initial erasing electricity of setting voltage steps ladder type
Pressure carries out erasing operation to memory cell corresponding to current erasure address, and returns to execution to storage corresponding to current erasure address
Unit wipe the operation of verification, until wiping successfully.
Further, when judging the erasing verification failure, in addition to：
Judge whether the memory cell is the failure of erasing verification for the first time, if so, then performing using based on setting voltage
The operation that the initial erasing voltage of step increments is wiped memory cell corresponding to current erasure address；
Otherwise, the maximum increase erasing voltage based on initial erasing voltage, using the erasing voltage after increase as current
Erasing voltage, and erasing operation is carried out to memory cell corresponding to current erasure address using the current erasure voltage.
Further, the ladder quantity of the corresponding staged erasing voltage used of each memory cell, each ladder are corresponding
Magnitude of voltage and each ladder corresponding to magnitude of voltage duration it is identical or different.
Further, the maximum increase erasing voltage based on initial erasing voltage, including：Erasing voltage is according to such as
Lower formula is increased：
Vi=V0+ (N-1) * Δs v
Wherein, ViRepresent that the erasing voltage V0 after increase represents the maximum of initial erasing voltage, N is represented to described current
The number that memory cell corresponding to erasing address is wiped, Δ v represent the incrementss of voltage.
Further, when judging the erasing verification failure, in addition to：
The number that failure is wiped memory cell corresponding to the current erasure address by wiping counter adds up；
Judge whether the erasing frequency of failure reaches the default erasing frequency of failure, if so, then terminating erasing operation.
Preferably, the default erasing frequency of failure is the positive integer less than or equal to 2000.
Further, after wiping successfully memory cell corresponding to the current erasure address, in addition to：
Judge whether the current erasure address is last erasing address, if then exiting erasing operation, is otherwise changed
The current erasure address, continue to carry out erasing operation to others erasing block, and carry out erasing verification, until all storages
Unit completes erasing operation.
Exemplarily, the erasing operation includes：
The grid to the memory cell and p-well apply erasing voltage respectively.
Exemplarily, the erasing voltage scope applied to the grid of the memory cell arrives -10V for -7V, to the storage
The erasing voltage scope that the p-well of unit applies is 6V to 10V.
Exemplarily, it is described that erasing verification is carried out to memory cell corresponding to current erasure address, be specially：
Whether the current value detected from the source electrode flow direction drain electrode of memory cell is more than pre-set current value, if so, then described deposit
Storage unit erasing verifies successfully.
The method for deleting of a kind of memory cell provided in an embodiment of the present invention, first to storage corresponding to current erasure address
Unit carries out erasing verification；Then judge whether the erasing verification succeeds, if it is not, being incremented by using based on setting voltage steps ladder type
Initial erasing voltage to corresponding to current erasure address memory cell carry out erasing operation, and return execution to current erasure
Memory cell corresponding to location wipe the operation of verification, until wiping successfully；Passed by using based on setting voltage steps ladder type
The initial erasing voltage increased carries out erasing operation to memory cell corresponding to current erasure address, reduces more active to electronics
Memory cell caused by destructive influences, improve the reliabilities of flash products.
Brief description of the drawings
Fig. 1 is a kind of structure chart of metal oxide semiconductcor field effect transistor as memory cell in flash chip；
Fig. 2 is a kind of method for deleting flow chart of memory cell in the embodiment of the present invention one；
Fig. 3 is the schematic diagram of the specific staged erasing voltage in the embodiment of the present invention one；
Fig. 4 is a kind of method for deleting flow chart of memory cell in the embodiment of the present invention two；
Fig. 5 is the schematic diagram of the specific erasing voltage in the embodiment of the present invention two；
Fig. 6 is a kind of method for deleting flow chart of memory cell in the embodiment of the present invention three；
Fig. 7 is a kind of method for deleting flow chart of memory cell in the embodiment of the present invention four.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention rather than entire infrastructure are illustrate only in description, accompanying drawing.
Embodiment one
Fig. 2 is a kind of method for deleting flow chart for memory cell that the embodiment of the present invention one provides, and the present embodiment is applicable
In to the more active memory cell progress erasing operation of some electronics.Referring to the wiping of Fig. 2, the present embodiment memory cell provided
Except method specifically comprises the following steps：
110th, erasing verification is carried out to memory cell corresponding to current erasure address.
Wherein, the essence for carrying out wiping verification to the memory cell is to carry out a read operation to the memory cell,
It more specifically can be understood as examining whether the numerical value read from the memory cell is 1, if 1 explanation storage
Unit has wiped success.
Exemplarily, erasing verification is carried out to memory cell corresponding to current erasure address, be specifically as follows：
Whether the current value detected from the source electrode flow direction drain electrode of memory cell is more than pre-set current value, if so, then described deposit
Storage unit erasing verifies successfully.Now think there has been the state of the electronics, now memory cell of abundance in the p-well of memory cell
For 1.The pre-set current value needs to be changed according to the difference of the manufacture craft of each flash chip, it is preferred that can be 20 μ A
Or 30 μ A, other numerical value are can also be certainly.
120th, judge whether the erasing verification succeeds, if it is not, performing step 130.
130th, using based on the incremental initial erasing voltage of setting voltage steps ladder type to storage corresponding to current erasure address
Unit carries out erasing operation, and returns and perform step 110, continues to carry out erasing school to memory cell corresponding to current erasure address
The operation tested, until wiping successfully.
It should be noted that the ladder quantity of each corresponding staged erasing voltage used of memory cell, each ladder
Magnitude of voltage duration corresponding to corresponding magnitude of voltage and each ladder is identical or different.If the electronics ratio of memory cell
It is more active, then it can use that ladder quantity is relatively more, magnitude of voltage corresponding to each ladder is relatively low and each ladder pair
The relatively small number of staged erasing voltage of magnitude of voltage duration answered, to reduce too high erasing voltage as far as possible to these electricity
The more active memory cell of son produces destructive influences.The schematic diagram of specific staged erasing voltage may refer to Fig. 3
It is shown, apply staged erasing voltage if memory cell is not wiped successfully after erasing verification (i.e. verify) every time.
The method for deleting of traditional memory cell is to be wiped every time using identical erasing voltage, until being erased into
Work(.But the problem of due to flash chip manufacture craft, it is preceding wipe several times when, have the electronics of some memory cell
Compare actively, if applying the destructive shadow of memory cell generation that stronger erasing voltage can be more active to these electronics
Ring, for example, by memory cell puncture etc., greatly affected the reliability of flash products.Therefore, the technology of the embodiment of the present invention
Scheme carries out erasing operation by using the erasing voltage of step increments, considerably reduces the storage more active to electronics
Damaging influence caused by unit, improve the reliability of flash products.
By writing program code flash memory can be controlled to carry out three big primary operationals, be read operation respectively, write behaviour
Make and erasing operation, wherein erasing operation are specifically completed to write 1 operation to memory cell.Erasing operation is carried out to memory cell
General principle be that corresponding erasing voltage is applied by the grid and p-well respectively to memory cell, apply the erasing electricity
Electric current is had after pressure and flows to drain electrode from source electrode, electronics understands some and flow to p-well, when in p-well from the way that drain electrode flows to source electrode
Electronics when reaching certain amount, this memory cell is just wiped free of success, i.e., this memory cell is successfully write 1.Erasing operation
Essence is to accumulate a certain amount of electronics by the p-well in memory cell, so as to which the threshold voltage of memory cell is pulled down into setting
Value, complete the erasing operation of memory cell.The concrete structure of memory cell may refer to the structural representation shown in Fig. 1.
Exemplarily, the erasing operation can be specifically that the grid to the memory cell and p-well apply erasing respectively
Voltage.Typically, the erasing voltage applied to the grid of the memory cell can be any number that -7V is arrived between -10V,
The erasing voltage applied to the p-well of the memory cell can be any number between 6V to 10V.Those skilled in the art are
Know, the voltage range -7V to -10V- being applied on the grid of memory cell and the electricity being applied in the p-well of memory cell
It is preferable exemplary value scope to press scope 6V to 10V, and is not limited thereof.
The method for deleting of a kind of memory cell provided in an embodiment of the present invention, first to storage corresponding to current erasure address
Unit carries out erasing verification；Then judge whether the erasing verification succeeds, if it is not, being incremented by using based on setting voltage steps ladder type
Initial erasing voltage to corresponding to current erasure address memory cell carry out erasing operation, and return execution to current erasure
Memory cell corresponding to location wipe the operation of verification, until wiping successfully；Passed by using based on setting voltage steps ladder type
The initial erasing voltage increased carries out erasing operation to memory cell corresponding to current erasure address, reduces more active to electronics
Memory cell caused by destructive influences, improve the reliabilities of flash products.
Embodiment two
Fig. 4 is a kind of method for deleting flow chart for memory cell that the embodiment of the present invention two provides, and the present embodiment is being implemented
Further optimized on the basis of example one, when judging the erasing verification failure, added：Judging the memory cell is
It is no to fail for erasing verification for the first time, if it is not, the increase erasing voltage of the maximum based on initial erasing voltage, by the wiping after increase
Memory cell corresponding to current erasure address is carried out except voltage is as current erasure voltage, and using the current erasure voltage
The operation of erasing.The benefit so optimized is not still wiped after can improving the erasing operation for having already passed through certain number
The erasing speed of successful memory cell, shorten the whole erasing cycle.It is specific to may refer to Fig. 4, methods described specifically include as
Lower step：
210th, erasing verification is carried out to memory cell corresponding to current erasure address.
220th, judge whether the erasing verification succeeds, if it is not, performing step 230.
230th, judge whether the memory cell is the failure of erasing verification for the first time, if so, performing step 240, otherwise, is held
Row step 250.
240th, using based on the incremental initial erasing voltage of setting voltage steps ladder type to storage corresponding to current erasure address
Unit carries out erasing operation, and returns and perform step 210.
250th, the maximum increase erasing voltage based on initial erasing voltage, is wiped using the erasing voltage after increase as current
Erasing operation is carried out to memory cell corresponding to current erasure address except voltage, and using the current erasure voltage, and returned
Perform step 210.
Exemplarily, the maximum increase erasing voltage based on initial erasing voltage, can include：Erasing voltage according to
Increased according to equation below：
Vi=V0+ (N-1) * Δs v
Wherein, ViRepresent that the erasing voltage V0 after increase represents the maximum of initial erasing voltage, N is represented to described current
The number that memory cell corresponding to erasing address is wiped, Δ v represent the incrementss of voltage.
If wiped successfully it should be noted that memory cell is still no after the erasing operation of certain number, that
Erasing operation is carried out to these memory cell again afterwards, is more difficult to wipe successfully, therefore in order to improve overall erasing speed,
It can be realized by the intensity of the erasing voltage after raising.The erasing voltage of higher-strength, again meeting are used if starting
The memory cell more active to electronics produces destructive influences, therefore first time erasing operation can be used based on setting electricity
The initial erasing voltage of step increments is pressed, when the memory cell of erasing failure be present, then increasing the intensity of erasing voltage, coming
Improve overall erasing speed.Certain those skilled in the art both knows about, and erasing voltage is also impossible to unconfined increase, when
When erasing voltage increases to the limiting value of permission, or the memory cell of erasing failure be present, be then used uniformly maximum afterwards
Erasing voltage carries out erasing operation, and erasing voltage does not continue to increase.The schematic diagram of the specific erasing voltage used can join
As shown in Figure 5, after erasing verification (i.e. verify) failure for the first time, then staged erasing voltage is applied, afterwards erasing verification
Fail again and then apply bigger erasing voltage, wiped after erasing voltage increases to maximum using maximum erasing voltage
Division operation.
The method for deleting of a kind of memory cell provided in an embodiment of the present invention, on the basis of above-described embodiment technical scheme
On, when judging the erasing verification failure, add：Judge whether the memory cell is the failure of erasing verification for the first time,
If it is not, the maximum increase erasing voltage based on initial erasing voltage, using the erasing voltage after increase as current erasure voltage,
And the operation wiped using the current erasure voltage memory cell corresponding to current erasure address；Reach and reduced
Damaging influence caused by the memory cell more active to electronics, while improving the reliability of flash products, improve wiping
Except speed, the whole purpose for wiping the cycle is shortened.
Embodiment three
Fig. 6 is a kind of method for deleting flow chart for memory cell that the embodiment of the present invention three provides, and the present embodiment is above-mentioned
Further optimized on the basis of embodiment, when judging the erasing verification failure, added：By wiping counter pair
The number of memory cell erasing failure carries out accumulative operation corresponding to the current erasure address, and the benefit so optimized is,
Avoid and unrestrictedly erasing operation is carried out to memory cell corresponding to current erasure address, whole program is absorbed in endless loop.
Specific to may refer to Fig. 6, the method for deleting for the memory cell that the present embodiment provides specifically comprises the following steps：
310th, erasing verification is carried out to memory cell corresponding to current erasure address.
320th, judge whether the erasing verification succeeds, if it is not, then performing step 330.
330th, judge whether the memory cell is the failure of erasing verification for the first time, if so, step 340 is then performed, otherwise,
Perform step 350.
340th, using based on the incremental initial erasing voltage of setting voltage steps ladder type to storage corresponding to current erasure address
The operation that unit is wiped, and return and perform step 310.
350th, the number that failure is wiped memory cell corresponding to the current erasure address by wiping counter is carried out
It is accumulative.
360th, judge whether the erasing frequency of failure reaches the default erasing frequency of failure, if so, step 370 is performed, it is no
Then, step 380 is performed.
A number for allowing erasing to fail is set for memory cell corresponding to each erasing address, when to certain erasing address
When the corresponding erasing frequency of failure reaches the number for allowing erasing to fail, now then compulsory withdrawal erasing operation, no longer right
The erasing address carries out erasing operation, continues to wipe other erasing addresses for not having to carry out erasing operation in erasing region
Operation.Typically, the default erasing frequency of failure is the positive integer less than or equal to 2000.Certainly, the technology of this area
Personnel both know about, and the default erasing frequency of failure is not limited to some or certain some fixed numbers, it is necessary to according to reality
The manufacture craft of operational circumstances and flash chip selectes suitable numerical value.
Aforesaid operations still verify primarily directed to when a memory cell by multiple erasing operation not over erasing
Situation, in order to prevent program enter " erasing-erasing verification-erasing " endless loop in, set erasing counter to erasing lose
The number lost carries out number that is accumulative, in particular to wiping current erasure address failure and counted.
370th, erasing operation is terminated.
380th, the maximum increase erasing voltage based on initial erasing voltage, is wiped using the erasing voltage after increase as current
Erasing operation is carried out to memory cell corresponding to current erasure address except voltage, and using the current erasure voltage, and returned
Perform step 310.
The method for deleting of a kind of memory cell provided in an embodiment of the present invention, on the basis of above-mentioned technical proposal, when sentencing
During the disconnected erasing verification failure, the number of failure is wiped memory cell corresponding to current erasure address by wiping counter
Added up, and judge whether the erasing frequency of failure is the default erasing frequency of failure, if so, then terminating erasing operation；It is logical
Setting erasing counter is crossed, realizes the endless loop for preventing program from entering " erasing verification-erasing-erasing verification ".
Example IV
Fig. 7 is a kind of method for deleting flow chart for memory cell that the embodiment of the present invention four provides, and the present embodiment is above-mentioned
Further optimized on the basis of each embodiment, add and judge whether the current erasure address is last erasing address
Operation, the benefit so optimized is can to quickly complete the erasing operation to whole erasing region.Referring to Fig. 7, this implementation
The method for deleting for the memory cell that example provides specifically comprises the following steps：
410th, erasing verification is carried out to memory cell corresponding to current erasure address.
420th, judge whether the erasing verification succeeds, if so, then performing step 430, otherwise, perform step 440.
430th, judge whether the current erasure address is last erasing address, if so, then performing step 450, otherwise
Perform step 460.
440th, using based on the incremental initial erasing voltage of setting voltage steps ladder type to storage corresponding to current erasure address
Unit carries out erasing operation, and returns and perform step 410.
450th, erasing operation is exited.
460th, the current erasure address is changed, and returns and performs step 410, continues to carry out erasing behaviour to new erasing block
Make.
A kind of method for deleting of memory cell provided in an embodiment of the present invention, on the basis of the various embodiments described above, works as inspection
When memory cell corresponding to testing current erasure address is wiped successfully, judge whether the current erasure address is last erasing
Location, if then exiting erasing operation, the current erasure address is otherwise changed, continue to carry out erasing behaviour to others erasing block
Make, and carry out erasing verification, until erasing block all in erasing region completes erasing operation, realizing to quickly complete
To the erasing operation in whole erasing region.
Pay attention to, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other more equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
- A kind of 1. method for deleting of memory cell, it is characterised in that including：Erasing verification is carried out to memory cell corresponding to current erasure address；Judge whether the erasing verification succeeds, if it is not, using based on the incremental initial erasing voltage pair of setting voltage steps ladder type Memory cell corresponding to current erasure address carries out erasing operation, and returns to execution to memory cell corresponding to current erasure address Wipe the operation of verification, until wiping successfully.
- 2. according to the method for claim 1, it is characterised in that when judging the erasing verification failure, in addition to：Judge whether the memory cell is the failure of erasing verification for the first time, if so, then performing using based on setting voltage ladder The operation that the incremental initial erasing voltage of formula is wiped memory cell corresponding to current erasure address；Otherwise, the maximum increase erasing voltage based on initial erasing voltage, using the erasing voltage after increase as current erasure Voltage, and erasing operation is carried out to memory cell corresponding to current erasure address using the current erasure voltage.
- 3. method according to claim 1 or 2, it is characterised in that the corresponding staged erasing used of each memory cell Magnitude of voltage duration corresponding to magnitude of voltage corresponding to the ladder quantity of voltage, each ladder and each ladder is identical or not Together.
- 4. according to the method for claim 2, it is characterised in that the maximum increase erasing based on initial erasing voltage Voltage, including：Erasing voltage is increased according to equation below：Vi=V0+ (N-1) * Δs vWherein, ViRepresent that the erasing voltage V0 after increase represents the maximum of initial erasing voltage, N is represented to the current erasure The number that memory cell corresponding to address is wiped, Δ v represent the incrementss of voltage.
- 5. method according to claim 1 or 2, it is characterised in that when judging the erasing verification failure, in addition to：The number that failure is wiped memory cell corresponding to the current erasure address by wiping counter adds up；Judge whether the erasing frequency of failure reaches the default erasing frequency of failure, if so, then terminating erasing operation.
- 6. according to the method for claim 5, it is characterised in that it is described it is default erasing the frequency of failure be less than or equal to 2000 positive integer.
- 7. method according to claim 1 or 2, it is characterised in that single to being stored corresponding to the current erasure address After member is wiped successfully, in addition to：Judge whether the current erasure address is last erasing address, if then exiting erasing operation, otherwise described in change Current erasure address, continue to carry out erasing operation to others erasing block, and carry out erasing verification, until all memory cell Complete erasing operation.
- 8. method according to claim 1 or 2, it is characterised in that the erasing operation includes：The grid to the memory cell and p-well apply erasing voltage respectively.
- 9. according to the method for claim 8, it is characterised in that the erasing voltage model applied to the grid of the memory cell Enclose and arrive -10V for -7V, the erasing voltage scope applied to the p-well of the memory cell is 6V to 10V.
- 10. method according to claim 1 or 2, it is characterised in that described to memory cell corresponding to current erasure address Erasing verification is carried out, is specially：Whether the current value detected from the source electrode flow direction drain electrode of memory cell is more than pre-set current value, if so, then the storage is single Member erasing verifies successfully.
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| CN110838329B (en) * | 2018-08-17 | 2022-04-01 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN112786094A (en) * | 2019-11-08 | 2021-05-11 | 上海复旦微电子集团股份有限公司 | Method for executing operation on storage device |
| CN112786094B (en) * | 2019-11-08 | 2023-08-18 | 上海复旦微电子集团股份有限公司 | Method for executing operation on storage device |
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Application publication date: 20180206 |