JP2008293616A - Erasing method for nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an erasing method to reliably complete erasure in consideration of an amount of decrease and increase of a threshold voltage due to collective erasure and due to restorative write processing. <P>SOLUTION: All or part of a reference erasing step, which includes an erasure verifying step and a collective erasing step for all memory cells and is configured to be repeated, includes an over-erasure verifying step of determining an over-erasure state, and a restoring step of restoring the over-erasure state to an erasure state. The second and the subsequent collective erasing steps are configured to perform collective erasure using an erasure voltage pulse in which at least either of an amplitude or a pulse width of an erasure voltage pulse in the previous collective erasing step is increased, or the second and the subsequent restoring steps are configured to perform restore and write processing using a restoring and writing voltage pulse in which at least either of an amplitude or a pulse width of a restoring and writing voltage pulse in the previous restoring step is reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for erasing a nonvolatile semiconductor memory device.

  2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory device such as a flash memory generally includes a memory cell array including a predetermined number of memory cell blocks including a plurality of memory cells, and includes a predetermined number of memory cells. Read processing in units of addresses, write processing in units of addresses, and batch erase processing in units of memory cell blocks composed of a plurality of addresses.

  Hereinafter, the configuration and processing operation of the flash memory according to the prior art will be described with reference to FIGS.

  First, a configuration example of a flash memory according to the prior art will be briefly described with reference to FIGS. Here, FIG. 9 shows a schematic configuration example of a memory cell array according to the prior art, and FIG. 10 shows a schematic configuration of a memory cell of a general ETOX type flash memory.

  Specifically, as shown in FIG. 9, the flash memory according to the prior art is configured to include a predetermined number of memory cell blocks configured by arranging a plurality of memory cells in a matrix in the row and column directions. The memory cell array is configured. For the sake of explanation, FIG. 9 shows the configuration of one memory cell block in the memory cell array.

  As shown in FIG. 10, the memory cell M is a region adjacent to a lower region of the control gate 1001 and the floating gate 1002 formed on the P-type semiconductor substrate 1005 via the floating gate 1002. A drain 1003 and a source 1004 which are N-type diffusion regions formed in the region 1005 are provided.

  The floating gate 1002 is electrically insulated from the control gate 1001, the P-type semiconductor substrate 1005, and the like, and the characteristics of the memory cell, that is, the storage state, change depending on the amount of charges accumulated in the floating gate 1002.

  Here, FIG. 11 schematically shows an example of the threshold voltage distribution of the binary memory cell. In the binary memory cell shown in FIG. 11, when a relatively low voltage is applied to the control gate 1001, a channel region can be generated in the region in the P-type semiconductor substrate 1005 between the drain 1003 and the source 1004. The state where the threshold voltage is low is the erase state “1”, and the state where the threshold voltage is high is the write state “0”. More specifically, in the case of the binary memory cell shown in FIG. 11, the memory cell M whose threshold voltage is in the range of voltages Ve0 to Ve is in the erased state “1” and the threshold voltage is equal to or higher than the voltage Vw. The memory cell M is classified into the write state “0”.

  In FIG. 11, the case where “1” is assigned to the erased state and “0” is assigned to the written state has been described, but the value assigned to each state is arbitrary. The reference voltage Vr indicates the value of the reference voltage used for determining the storage state of the memory cell in the read process.

  FIG. 12 schematically shows a threshold voltage distribution of a quaternary memory cell as an example of a multi-value memory cell configured to be able to store information of three or more values corresponding to an erase state and a plurality of write states. Yes. In the quaternary memory cell shown in FIG. 12, the quaternary memory cell having the lowest threshold voltage within the range of voltages Ve0 to Ve is in the erased state “11”, and the threshold voltage is a region where Vw10 is the lower limit. The quaternary memory cell in the write state “10”, the threshold voltage of the quaternary memory cell in the region where Vw01 is the lower limit value is in the write state “01”, and the threshold voltage is the voltage Vw00 or higher. The quaternary memory cell is classified into the write state “00”.

  In FIG. 12, “11” is assigned to the erased state, and “10”, “01”, and “00” are assigned to each written state in ascending order of threshold values. Is optional. Further, the reference voltage VrL, the reference voltage VrM, and the reference voltage VrH indicate reference voltage values used for determining the storage state of the memory cell in the read process.

  As shown in FIG. 9, the memory cell array is configured by arranging m × n memory cells M in a matrix, and by connecting the control gates 1001 of the memory cells M in the same row to each other, a common word Lines WL0 to WLm-1 (m is an integer greater than or equal to 2), and drains 1003 of memory cells M in the same column are connected to each other to form common bit lines BL0 to BLn-1 (n is an integer greater than or equal to 2). . Furthermore, the source 1004 of the memory cell M is connected to a common source line SL.

  Although not shown, each row address included in the address signal is decoded around the memory cell array, and each selected word line connected to the control gate 1001 of the memory cell M to be read or written is processed. A row decoder that applies a voltage set according to processing, a column decoder that decodes a column address included in an address signal and selects a bit line to be processed, a source switch that switches an applied voltage to the source line SL, and the like are provided. Yes.

  Next, the operation principle of the read process, write process, and batch erase process for the memory cell array according to the prior art will be briefly described with reference to FIG. Hereinafter, for the sake of simplicity, a reading process for a binary memory cell in an address unit, a writing process in an address unit, and a batch erasing process in a memory cell block unit composed of a plurality of addresses will be described. Here, FIG. 13 shows voltage conditions in the read process, write process, and batch erase process for the binary memory cell.

  In the read process, as shown in FIG. 13, the row decoder applies a positive control gate voltage of 5 V to the selected word line specified by the row address included in the address signal, and the non-selected other than the selected word line is selected. 0V is applied to the word line. The source switch applies a source voltage of 0 V to the source line SL. The column decoder connects a bit line connected to a memory cell to be read out of each of the bit lines BL0 to BLn-1 to a sense amplifier, and applies a positive drain voltage of 1V. For memory cells connected to unselected word lines that are not subject to read processing, 0 V is applied to the control gate and source, so that there is almost no voltage difference between the gate and source. No current flows regardless of the storage state, and the read process is hardly affected.

  More specifically, in the above read process, 5 V is applied to the control gate 1001 of the memory cell M shown in FIG. 10, 1 V is applied to the drain 1003, and 0 V is applied to the source 1004. At this time, a channel region is generated in a region in the P-type semiconductor substrate 1005 between the drain 1003 and the source 1004 and a current flows. However, when the memory cell M is in the erased state, the threshold voltage is low, so the drain 1003 A relatively large current flows between the sources 1004. On the other hand, when the memory cell M is in the write state, since the threshold voltage is high, only a relatively small current flows between the drain 1003 and the source 1004. As a result, in the sense amplifier circuit, the storage state can be determined based on the threshold voltage of the memory cell M obtained from the value of the current flowing through the memory cell M.

  For example, in the case of the binary memory cell shown in FIG. 11, if the value of the threshold voltage of the memory cell M is smaller than the reference voltage Vr in the read process, it is determined that the erase state is “1” and the reference voltage Vr If it is larger, it is determined that the write state is “0”.

  In the write process, as shown in FIG. 13, the row decoder applies a positive control gate voltage of 10 V to the selected word line connected to the control gate 1001 of the write target memory cell M to be written, 0 V is applied to the unselected word line connected to the control gate 1001 of the memory cell M that is not the target of the writing process. The source switch applies a source voltage of 0 V to the source line SL. The column decoder applies a positive drain voltage of 5 V to the selected bit line to be written in each of the bit lines BL0 to BLn-1. As in the case of the read process, 0 V is applied to the control gate and source of the non-selected memory cell, so that the characteristics of the non-selected memory cell are not affected.

  More specifically, in the above-described writing process, 10 V is applied to the control gate 1001 of the memory cell M shown in FIG. 10, 5 V is applied to the drain 1003, and 0 V is applied to the source 1004. By applying a high positive voltage to the drain 1003, high-energy hot electrons are generated in the channel region in the vicinity of the source 1004. Further, by applying a positive voltage higher than that of the drain 1003 to the control gate 1001, hot electrons are generated. It is injected into the floating gate 1002 with a certain probability. This writing process is called a CHE method (channel hot electron method). In this write process, in FIG. 11, when the value of the threshold voltage of the memory cell M exceeds the value of the voltage Vw, it is determined that the write process has been completed normally.

  In the batch erase process, as shown in FIG. 13, the row decoder applies a negative control gate voltage of −10 V to all the word lines WL0 to WLm−1 of the erase target memory cell block that is the target of the batch erase process. Apply. The source switch applies a high positive source voltage of 10 V to the source line SL of the memory cell block to be erased. As a result, all m × n memory cells constituting the memory cell block to be erased are erased collectively.

  More specifically, in the batch erase process described above, −10 V is applied to the control gate 1001 and 10 V is applied to the source 1004 of the memory cell M shown in FIG. When a voltage is applied under such conditions, the charge accumulated in the floating gate 1002 escapes to the source 1004 due to the tunnel effect. This phenomenon is called an FN tunnel phenomenon (Fowler Nordheim Tunneling). In the batch erasing process, when the threshold voltage value of the memory cell M becomes smaller than the voltage Ve in FIG. 11, it is determined that the batch erasing process is normally completed.

  By the way, in the batch erasing process in a nonvolatile semiconductor memory device such as a flash memory, the amount of charge in the floating gate 1002 is very small, and the threshold voltage value is the lower limit value of the threshold voltage in the erased state, for example, In FIG. 11, an overerased memory cell (overerased memory cell) smaller than the voltage Ve0 may occur.

  If an overerased memory cell exists, there may be a problem in execution of read processing and write processing. Specifically, for example, when executing a read process for another memory cell connected to a bit line connected to an overerased memory cell, a memory cell connected to an unselected word line that is not subject to the read process As described above, 0 V is applied to the control gate and the source. At this time, there is almost no voltage difference between the gate and source of a normal unselected memory cell, but in the case of a memory cell connected to an overselected unselected word line, the threshold voltage becomes a negative voltage. Therefore, the current is not completely turned off and a current that cannot be ignored may flow. This current causes erroneous reading in the reading process.

  Also, for example, when executing a write process to another memory cell connected to the same bit line as the overerased memory cell, a high voltage is applied to the bit line (drain), but the overerased state is not selected. There is a possibility that the bit line voltage decreases due to the current flowing through the memory cell, and the writing process to the memory cell to be written cannot be executed normally.

  In recent years, overerased memory cells are easily generated due to various factors. Specifically, for example, the number of memory cells in the memory cell block to be erased in the batch erasing process due to the miniaturization of the processing process and the increase in the number of memory cells accompanying the increase in the storage capacity as a factor of increasing the occurrence rate of overerased memory cells There is an increase.

  As the miniaturization progresses, the variation in memory cell characteristics due to manufacturing variations generally increases, and the variation in erasing speed of memory cells in the batch erasing process increases. Further, when the number of memory cells in the memory cell block to be erased increases, the number of memory cells with large variations also increases. In the batch erase process, since the erase process is executed in units of memory cell blocks, the same number of erase processes are performed on both the memory cells that are in the erased state relatively early and the memory cells that are in the erased state relatively late. Will be executed. For this reason, if the batch erase process is repeatedly executed until the memory cells that are in the erased state relatively late are in the erased state, the memory cells that are in the erased state relatively quickly are erased more than necessary after the erased state. It will be executed, and it will be in an over-erased state.

  For this reason, in the conventional nonvolatile semiconductor memory device, in order to prevent problems in the read process and write process by the over-erased memory cell, for example, the over-erased memory cell generated in the batch erase process is over-stored. Some perform a repair writing process for restoring from an erased state to an erased state.

  Hereinafter, the processing procedure of the batch erasing process when executing the repair writing process will be described with reference to FIG. Here, FIG. 14 is a flowchart illustrating an example of a processing procedure of the batch erasure process when the repair writing process is executed. Here, for the sake of simplicity, description will be made assuming that the memory cell of the memory cell block to be erased is the binary memory cell shown in FIG.

  First, the nonvolatile semiconductor memory device initializes the value of an address variable indicating the current processing target address (step # 1001). Here, the start address of the memory cell block to be erased is set in the address variable. Next, an erase voltage pulse is applied to all the memory cells in the memory cell block to be erased under a predetermined erase voltage condition to execute batch erase processing (step # 1002).

  Subsequently, an erase verify process for determining whether or not the storage state of the memory cell is an unerased state is executed for each of the memory cells in the memory cell block to be erased (step # 1003). The erase verify process here is configured to be executed in units of addresses, and it is determined whether or not each of the memory cells M at the address indicated by the address variable is in an unerased state. The determination as to whether or not the memory cell M is in the unerased state is made by comparing the threshold voltage of each memory cell M with the reference voltage Ve shown in FIG. When it is larger than Ve, it is determined that the state is not erased.

  If the memory cell M that has been erase-verified in step # 1003 includes at least one unerased memory cell that has been determined to be in an unerased state, the process proceeds to step # 1002 (in step # 1004). No branch), again, the erase voltage pulse amplitude, pulse width, and the like are reset according to the erase voltage condition, and the batch erase process is executed by applying the reset erase voltage pulse (step # 1002).

  If the memory cell M that has been erase-verified in step # 1003 does not include an unerased memory cell determined to be in an unerased state (Yes branch in step # 1004), the process proceeds to step # 1005, The value of the address variable is incremented (step # 1005). If there is an address in the erase target memory cell block for which the erase verify process has not been completed (No branch at step # 1006), the process proceeds to step # 1002 to erase erase process for the memory cell M at the address indicated by the address variable. Execute.

  When the batch erase process for all addresses in the erase target memory cell block is completed (Yes in step # 1006), the value of the address variable is initialized and the start address of the erase target memory cell block is set (step # 1007). . Subsequently, an overerase verify process for determining whether or not the memory cell in the erase target memory cell block is in an overerase state is executed (step # 1008). The overerase verify process here is configured to be executed in units of addresses, and it is determined whether or not each of the memory cells M at the address indicated by the address variable is in an overerase state. The determination as to whether or not the memory cell M is in the over-erased state is specifically made by comparing the threshold voltage of each memory cell M with the reference voltage Ve0 shown in FIG. When it is smaller than Ve0, it is determined that the over-erased state is established.

  If there is a memory cell M that has been determined to be in an overerased state in the memory cell M that has been subjected to the overerase verify process in step # 1008 (Yes branch in step # 1009), a repair write to the overerased memory cell M The process is executed (step # 1010), and then the process proceeds to step # 1008. Here, as the repair write process, a weak write process using a repair write voltage pulse having a smaller voltage amplitude or pulse width than the write voltage pulse in the normal write process is executed. As described above, in the over-erased state, for example, in FIG. 10, the amount of charge in the floating gate 1002 of the memory cell M becomes very small, and the threshold voltage is too low to be lower than the voltage Ve0 shown in FIG. It is in a state. Therefore, the memory state of the memory cell can be restored from the overerased state to the erased state by increasing the amount of charge in the floating gate 1002 and increasing the threshold voltage to be higher than the voltage Ve0 by the weak write process. it can. Note that if normal write processing is performed on an overerased memory cell, the threshold voltage increases excessively and may exceed the upper limit value Ve of the erased state threshold voltage. In order to write in the range Ve0 to Ve, weak write processing is executed.

  If the memory cell M that has been subjected to the overerase verify process in step # 1008 has no memory cell that is determined to be in the overerase state (No branch in step # 1009), the value of the address variable is incremented and updated ( In Step # 1011), when the value of the address variable indicates an address for which the over-erase verify process in the memory cell block to be erased has not been executed (No branch in Step # 1012), the process proceeds to Step # 1008. Overerase verify processing is executed for the memory cell M at the address indicated by. When the overerase verify process is executed for all addresses in the erase target memory cell block (Yes in step # 1012), the process ends.

  In the flowchart shown in FIG. 14, the number of executions of the batch erase process in step # 1002 may be counted, and if the erase process is not completed within a predetermined number of times, the process may be terminated and an error output may be output. .

FIG. 15 shows the transition of the control gate voltage of the selected memory cell to be erased and the transition of the current consumption of the device in the batch erase process, erase verify process, overerase verify process and repair write process shown in FIG. The voltage V _GND indicates the ground voltage.

At the initial setting of time t0 to te1 (step # 1001 in FIG. 14), the gate voltage of the control gate 1001 of the memory cell M shown in FIG. 10 is 0 V (voltage V _GND ) as shown in FIG. . When the batch erase process is started at time te1 (step # 1002 in FIG. 14), a negative erase voltage pulse Vn1 is applied to the control gates 1001 of all the memory cells M in the memory cell block to be erased. . Since the current consumption Wn1 at this time is dominant when the erasing process is performed under the voltage condition shown in FIG. 13, the band-to-band current from the source 1004 to the semiconductor substrate 1005 is dominant. Decrease depending on

  Subsequently, when the erase verify process is started at time tev1 (step # 1003 in FIG. 14), a positive erase verify voltage pulse Vev1 is applied to the control gate of the memory cell in the memory cell block to be erased. Note that the consumption currents Wev1 to Wevk (k is an integer of 1 or more) in the erase verify process are larger than the consumption currents Wn1 to Wnk in the batch erase process because the sense amplifier is driven. Similarly, the batch erase process and the erase verify process are repeatedly executed until it is determined that all the memory cells in the erase target memory cell block are not in the unerased state.

  When the overerase verify process is started at time toev1 (step # 1008 in FIG. 14), a positive overerase verify voltage pulse Voev1 is applied to the control gate of the memory cell targeted for the overerase verify process. . In the overerase verify process, the threshold voltage of the memory cell is compared with a reference voltage Ve0 lower than the reference voltage Ve in the erase verify process. Here, since the over-erased state is determined using the same reference voltage as the reference voltage used in the erase verify process, the over-erase verify voltage pulse is determined according to the relationship between the voltage Ve0 and the voltage Ve. The voltage amplitude of Voev1 is set larger than the voltage amplitude of the erase verify voltage pulses Vev1 to Vevk (voltage Voev> voltage Vev). Further, as shown in FIG. 15, the current consumption Woev1 in the overerase verify process is such that the voltage amplitude of the overerase verify voltage pulse Voev1 is set larger than the voltage amplitude of the erase verify voltage pulses Vev1 to Vevk. It becomes larger than current consumption Wev1 to Wevk in the process.

  When the repair write process is started at time toep1 (step # 1010 in FIG. 14), a positive repair write voltage pulse Voep is applied to the control gate of the overerased memory cell that is the target of the repair write process. The voltage amplitude and pulse width of the repair write voltage pulse Voep are set according to the characteristics of the memory cell. The current consumption Woep1 in the repair write process is that the number of overerased memory cells to be subjected to the repair write process is smaller than the number of memory cells to be subjected to the batch erase process, the erase verify process, and the overerase verify process. It becomes smaller than the current consumption in other processes. Similarly, the overerase verify process and the repair write process are repeatedly executed until no overerased memory cell is determined.

  As shown in FIG. 15, the batch erase process and the erase verify process are repeatedly executed before the time toev1, and the overerase verify process and the repair write process are repeatedly executed after the time toev1, so before and after the time toev1. The processing contents can be clearly discriminated by the voltage fluctuation of the control gate of the memory cell.

  Other techniques for preventing problems in read processing and write processing by overerased memory cells include, for example, a positive voltage on a selected word line in order to cut off leakage current of overerased memory cells in read processing, There is a nonvolatile semiconductor memory device that applies a negative voltage to an unselected word line (see, for example, Patent Document 2). In addition, for example, an off-voltage generating unit that generates an off-voltage that can be forcibly turned off in any state of memory cells is provided, and control of memory cells that are not subjected to over-erase verification processing when over-erase verification processing is performed There is a nonvolatile semiconductor memory device that applies an off voltage to a gate (see, for example, Patent Document 3).

  Further, for example, the batch erase process and the erase verify process are repeatedly performed, and during the batch erase process, a leak check is performed at a predetermined time interval. If the result of the leak check is NG, the batch erase process is interrupted. There is a non-volatile semiconductor memory device that performs over-erase verify processing and weak write processing, and resumes the interrupted batch erase processing after execution of over-erase verify processing and weak write processing ends (see, for example, Patent Document 1). ). Note that in the nonvolatile semiconductor memory device described in Patent Document 1, during the repetition of the batch erase process and the erase verify process, the execution of the batch erase process is interrupted and the over erase verify process and the weak write process are performed. Generation of an erase memory cell can be detected and eliminated at an earlier stage.

JP 2000-260189 A JP-A-6-162787 JP-A-7-169286

  However, in the nonvolatile semiconductor memory device collectively erased by the erase processing procedure shown in FIG. 14 and the nonvolatile semiconductor memory device described in Patent Document 1, the amount of decrease in the threshold voltage of the memory cell to be erased by the batch erase processing In addition, the balance of the increase amount of the threshold voltage of the overerased memory cell due to the repair writing process (weak writing process) is not taken into consideration. For this reason, there is a possibility that a memory cell that is over-erased by the batch erase process and becomes an unerased state by the weak write process may be generated. There is a problem that there is a possibility that the erasing process cannot be completed normally.

  The present invention has been made in view of the above problems, and its purpose is to reduce the amount of decrease in the threshold voltage of the memory cell due to batch erase processing and the amount of increase in the threshold voltage of the memory cell due to repair write processing. In view of balance, it is an object to provide an erasing method of a nonvolatile semiconductor memory device that can complete erasure processing more reliably and normally.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells, and can execute batch erase processing in units of a memory cell group including a predetermined number of memory cells. A method for erasing a nonvolatile semiconductor memory device, wherein a determination is made as to whether or not the storage state of the memory cell is an unerased state for each of the memory cells of a memory cell group to be erased that is a target of batch erase processing. When there is an erase verify process for executing the erase verify process and the memory cells determined to be in the unerased state in the erase verify process, all the memory cells constituting the erase target memory cell group On the other hand, a batch erase process for executing a batch erase process for applying an erase voltage pulse based on a predetermined erase voltage condition, and the erasure target memo An overerase verify process for executing an overerase verify process for determining whether or not the storage state of the memory cell is an overerase state for each of the memory cells of the cell group; and the overerase verify process in the overerase verify process. When there is the memory cell determined to be in the erased state, a repair write voltage pulse is applied to the memory cell in the overerased state based on a repair voltage condition for repairing the overerased state A repair process that executes a writing process, and repeatedly executing a reference erase process including the erase verify process and the batch erase process, or only when a predetermined repair execution condition is met. The over-erase verify process and the repair process are executed in the reference erase process, and in the batch erase process after the second time, Executing the batch erase process using the erase voltage pulse in which at least one of the amplitude or the pulse width of the erase voltage pulse in the previous batch erase step is increased based on a last voltage condition; It is characterized by.

  In order to achieve the above object, an erasing method of a nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells, and performs batch erasing processing for each memory cell group including a predetermined number of memory cells. An erasing method for a non-volatile semiconductor memory device that can be executed, wherein whether or not the memory cell is in an unerased state with respect to each of the memory cells of a memory cell group to be erased that is a target of batch erase processing An erase verify process for executing an erase verify process for determining whether or not there is the memory cell determined to be in the unerased state in the erase verify process, and all the memory cells constituting the erase target memory cell group A batch erase process for executing a batch erase process for applying an erase voltage pulse to a memory cell based on a predetermined erase voltage condition; An overerase verify process for executing an overerase verify process for determining whether or not the storage state of the memory cell is an overerase state for each of the memory cells of the target memory cell group; and When there is the memory cell determined to be in the over-erased state, a repair write voltage pulse is applied to the memory cell in the over-erased state based on a repair voltage condition for repairing the over-erased state A repair process for executing a repair write process, and when the reference erase process including the erase verify process and the batch erase process is repeatedly executed, every time or only when a predetermined repair execution condition is met The over-erase verify process and the repair process are executed in the reference erase process, and in the second and subsequent repair processes. Executing the repair write process using the repair write voltage pulse in which at least one of the amplitude and the pulse width of the repair write voltage pulse in the previous repair process is decreased based on the repair voltage condition. The second feature.

  According to the erasing method of the nonvolatile semiconductor memory device of the present invention having the above characteristics, the amplitude or pulse of the erase voltage pulse in the previous batch erase step based on the erase voltage condition in the second and subsequent batch erase steps. A third feature is that the batch erase process is executed using the erase voltage pulse in which at least one of the widths is increased.

  In the nonvolatile semiconductor memory device erasing method according to the present invention having any one of the above characteristics, in the repairing step, the repairing write voltage pulse is simultaneously applied to the plurality of the memory cells in the over-erased state to perform the repairing. The fourth feature is to execute the writing process.

  The non-volatile semiconductor memory device erasing method according to the present invention having any one of the above features is characterized in that, in the over-erase verify process, the over-erase verify process results in a predetermined buffer circuit in the over-erase verify process. According to a fifth feature of the present invention, the repair write process is executed based on the result of the over-erase verify process stored in the buffer circuit.

  An erasing method of a nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics is configured such that the memory cell can store information of three or more values corresponding to an erased state and a plurality of write states, and the nonvolatile semiconductor The memory device is configured to include a sense amplifier circuit including a sense amplifier group including a plurality of sense amplifiers that determine a storage state of the memory cell in a binary manner for each predetermined memory cell. In the erase verify step, For each of the target memory cells, the erase verify process is executed using one of the sense amplifiers constituting the corresponding sense amplifier group, and in the over-erase verify process, for each of the memory cells to be erased Among the sense amplifiers constituting the corresponding sense amplifier group, the sense amplifiers used in the erase verify process Using another one sense amplifier, except, the over-erase verify process, and sixth aspect of the executing simultaneously with the erase verify process.

  According to the erasing method of the nonvolatile semiconductor memory device having the above characteristics, the reference erasing process including the erasing verify process and the batch erasing process is repeatedly executed, and further, all or a part of the reference erasing process is over-erase verify. Each time the reference erase process is executed, the amount of decrease in the threshold voltage of the memory cell in the batch erase process is the amount of increase in the threshold voltage of the memory cell in the repair write process. On the other hand, since it is configured so as to increase in a relative and stepwise manner, the storage state of the memory cell can be more reliably brought into the erased state.

  Specifically, for example, a conventional non-volatile semiconductor memory device collectively erased by an erase process procedure shown in FIG. 14 or a memory cell in a batch erase process, such as the non-volatile semiconductor memory devices described in Patent Documents 1 to 3. When the relationship between the amount of decrease in the threshold voltage of the memory cell and the amount of increase in the threshold voltage of the memory cell in the repair writing process is fixedly set, depending on the characteristics of the memory cell to be erased, the reference erase process When the above is repeated, it may be difficult for the storage state to reciprocate between the over-erased state and the non-erased state to make it an erased state. In contrast, in the nonvolatile semiconductor memory device having the above characteristics, the amount of decrease in the threshold voltage of the memory cell in the batch erase process and the increase in the threshold voltage of the memory cell in the repair write process each time the reference erase process is executed. Since the relationship between the amounts is variably configured, the storage state can be more reliably brought into the erased state regardless of the characteristics of the memory cell to be erased by repeatedly executing the reference erase step.

  In addition, according to the erasing method of the nonvolatile semiconductor memory device having the above characteristics, the setting of the decrease amount of the threshold voltage of the memory cell in the batch erasing process or the increase amount of the threshold voltage of the memory cell in the repair writing process Is configured to be adjusted by the voltage amplitude or the pulse width, so that the apparatus of the present invention can be constructed relatively easily without complicating the apparatus configuration.

  Further, if the repair write process is executed not in units of memory cells but in units of buffers consisting of a plurality of memory cells as in the nonvolatile semiconductor memory device erasing method of the fifth feature, the repair write process can be performed. Such time can be reduced. Further, in the case of a nonvolatile semiconductor memory device capable of executing buffer write processing, if the buffer circuit for buffer writing is diverted to the repair write processing, there is no need to newly provide a dedicated buffer circuit and the chip area is increased. I will not let you.

  As described in the sixth feature of the nonvolatile semiconductor memory device erasing method, the memory cell array is composed of multi-level memory cells capable of storing information of three or more values, and a sense amplifier for performing binary determination on one memory cell is provided. If multiple sense amplifiers are provided, if one sense amplifier is used for the erase verify process and the other sense amplifier is used for the over erase verify process, the erase verify process and the over erase verify process can be executed simultaneously. Is possible. As a result, the processing time can be shortened in the entire erase verify process and over-erase verify process.

  Embodiments of a method for erasing a nonvolatile semiconductor memory device according to the present invention (hereinafter referred to as “method of the present invention” where appropriate) will be described below with reference to the drawings.

<First Embodiment>
1st Embodiment of the method of this invention is described based on FIGS.

  First, the configuration of a nonvolatile semiconductor memory device to which the method of the present invention is applied will be briefly described with reference to FIG. Here, FIG. 1 shows a schematic partial configuration example of a portion related to execution of the method of the present invention in the nonvolatile semiconductor memory device 1.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 1 includes a memory cell array 70 including a predetermined number of memory cell blocks configured by arranging a plurality of memory cells in a matrix in the row and column directions. An input / output buffer 10 for receiving a control signal from the outside via a control line L2, an address signal via an address line L3, and exchanging data signals via a data line L4, and a memory cell to be written during a write process A buffer circuit 40 that stores expected value data indicating the expected value of the sense amplifier, and a sense amplifier circuit 60 that includes a sense amplifier group that includes one or a plurality of sense amplifiers that determine the storage state of a memory cell by binary determination for each bit line The external command is received via the input / output buffer 10, and the external command is decoded and the write state machine 30 and the buffer are decoded. An internal control signal group is received from a UI (User Interface) circuit 20 and a UI circuit 20 that control the factory circuit 40, and each internal circuit in the apparatus is controlled via the control register circuit 50 based on the internal control signal group. A write state machine 30 that performs control such as writing processing and erasing processing on the memory cell array 70 is provided.

  The configuration of the memory cell array 70 of the nonvolatile semiconductor memory device 1 is the same as the configuration of the conventional memory cell array shown in FIG. 9 described above, and the configuration of the memory cells constituting the memory cell array 70 is shown in FIG. This is the same as the configuration of the conventional memory cell M shown. Specifically, as shown in FIG. 9, the memory cell array 70 is configured by arranging m × n memory cells M in a matrix, and the control gates 1001 of the memory cells M in the same row are connected to each other. The common word lines WL0 to WLm-1 (m is an integer equal to or greater than 2) are connected to each other, and the drains 1003 of the memory cells M in the same column are connected to each other to connect the common bit lines BL0 to BLn-1 (n is 2). It is an integer above. Furthermore, the source 1004 of the memory cell M is connected to a common source line SL.

  Next, the processing procedure of the method of the present invention in this embodiment will be described with reference to FIGS. Here, FIG. 2 shows a processing procedure of the method of the present invention in the present embodiment.

  The nonvolatile semiconductor memory device 1 of the present embodiment includes an erase verify process (erase verify process) in units of addresses composed of a plurality of memory cells and a batch erase process (collective erase process) in units of memory cells composed of a plurality of addresses. ) Is repeatedly executed. Further, in the present embodiment, in the reference erase process, an over-erase verify process (over-erase verify process) in units of addresses and a repair write process (repair process) in units of memory cells or addresses are executed each time.

  In the nonvolatile semiconductor memory device 1, when the UI circuit 20 receives an erase request for a predetermined memory cell block by an external command, first, the write state machine 30 performs initial setting (step # 101). Specifically, in this embodiment, in an erase verify process or an over-erase verify process executed in units of addresses, an address variable indicating the current process target address is added to an erase target memory cell block ( The value of the top address of the memory cell group to be erased) is set.

  Subsequently, the nonvolatile semiconductor memory device 1 executes batch erase processing for applying an erase voltage pulse to all the memory cells constituting the memory cell block to be erased based on a predetermined erase voltage condition (step # 102). Batch erase process). Here, FIG. 3 shows the erase voltage condition in the present embodiment. Specifically, for example, in the first batch erase process, in the erase target memory cell block shown in FIG. 9, each of the word lines WL0 to WLm-1 connected to the control gates of the memory cells is set to a negative voltage of -10V. A positive voltage of 2 V is applied to the source line SL connected to the source of the memory cell.

  Subsequently, the nonvolatile semiconductor memory device 1 executes an erase verify process for determining whether or not the storage state of the memory cell is an unerased state for each memory cell of the memory cell block to be erased (step # 103). , Erase verify process). Here, in the present embodiment, the erase verify process is configured to be executed in units of addresses. If at least one of the memory cells at the address indicated by the address variable has an unerased memory cell determined to be in an unerased state (Yes branch at step # 104), a re-indicating that a batch erase process is necessary again An erase flag is set (step # 105).

  Subsequently, the nonvolatile semiconductor memory device 1 performs an overerase verify process for determining whether or not the storage state of the memory cell is an overerase state for each of the memory cells in the memory cell block to be erased (step) # 106, over-erase verify process). Here, in the present embodiment, the over-erase verify process is configured to be executed in units of addresses.

  Subsequently, when there is an overerased memory cell that is determined to be in the overerased state in the overerase verify process in step # 106 (Yes branch in step # 107), the nonvolatile semiconductor memory device 1 stores the overerased memory. A repair write process for applying a repair write voltage pulse to the cell based on a repair voltage condition for repairing the over-erased state is executed (step # 108, repair process). In this embodiment, the amplitude and pulse width of the repair write voltage pulse are fixedly set in advance. Furthermore, after executing the repair process in step # 108, considering that the overerased memory cell may be in an unerased state due to the repair write process in the repair process, the process proceeds to step # 103 and the memory cell with the same address is transferred. An erase verify process is executed for each of them. In the method of the present invention of this embodiment, the erase verify process of step # 103 is executed after the repair process of step # 108. Therefore, even if an overerased memory cell that becomes an unerased state is generated by the repair write process, the process is again performed. Since the batch erasure process is executed, the process can be completed more reliably and normally.

  If there is no overerased memory cell determined to be in the overerased state in the overerase verify process of step # 106 (No branch in step # 107), the value of the address variable is incremented (step # 109), and the erase target Until all of the memory cells in the memory cell block are erase verified (step # 103), over-erased verified (step # 106), and repaired and written (# 108) (No branch at step # 110), step # Steps 103 to 108 are repeatedly executed.

  When the erase verify process (step # 103), the over-erase verify process (step # 106), and the repair write process (# 108) are completed for all the memory cells in the erase target memory cell block (Yes branch at step # 110), the nonvolatile memory When the re-erase flag indicating that it is necessary to execute the batch erase process is set (Yes in step # 111), the volatile semiconductor memory device 1 again performs the reference erase process (steps # 102 to # 111). ), The amplitude of the erase voltage pulse used in the next batch erase process (step # 102) is reset based on the erase voltage condition (step # 112). Here, the address variable is further initialized.

  More specifically, in this step # 112, the second and subsequent batch erase processing is set. In the erase voltage condition shown in FIG. 3, the amplitude of the erase voltage pulse applied to the source is set to increase every time the batch erase process is executed. More specifically, in the erase voltage condition shown in FIG. 3, in the second to fifth batch erase steps (step # 102), the amplitude of the erase voltage pulse applied to the source is set to increase by 2V. Yes. In the fifth and subsequent reference erase steps, the amplitude of the erase voltage pulse applied to the source is set not to increase due to restrictions on the peak value of the voltage amplitude of the applied voltage pulse in the nonvolatile semiconductor memory device 1.

  By setting the erase voltage condition in this way, the amount of decrease in the threshold voltage of the memory cell due to the batch erase process can be increased every time the batch erase process is executed. That is, in the method of the present invention, each time the reference erase process is executed, the amount of decrease in the threshold voltage of the memory cell due to the batch erase process is relatively less than the amount of increase in the threshold voltage of the memory cell in the repair write process. Can be increased. As a result, in the nonvolatile semiconductor memory device 1 to which the method of the present invention is applied, the level of the over-erased state is sequentially increased in the reference erasing process. It is possible to more effectively prevent the memory cell storage state from reciprocating between the over-erased state and the unerased state, and the memory cell to be erased can be more surely brought into the erased state.

  As shown in FIG. 2, the nonvolatile semiconductor memory device 1 proceeds to step # 102 when the resetting of the erase voltage pulse or the like in the second and subsequent batch erase processing is completed in step # 112, and batch erase again. Processing (step # 102) is executed.

  In step # 111, when the re-erase flag indicating that the batch erase process needs to be executed is not set (No branch in step # 111), the nonvolatile semiconductor memory device 1 is in the memory cell block to be erased. It is determined that there are no over-erased and unerased memory cells and all the memory cells are in an erased state, and the process is terminated.

  In the present embodiment, the configuration for increasing the amplitude of the erase voltage pulse has been described. However, the present invention is not limited to this. For example, not the voltage amplitude but the pulse width may be increased, or both the amplitude and the pulse width may be increased. For example, first, the voltage amplitude may be increased in accordance with the erase voltage condition shown in FIG. 3, and the pulse width may be increased after the fifth time. Furthermore, in this embodiment, the amount of increase in the amplitude of the erase voltage pulse is set to a constant amount (2 V), but it may be configured to increase under other conditions, such as increasing by a constant rate. The initial value and increase amount of the voltage amplitude and pulse width of the erase voltage pulse are set according to the manufacturing process and the characteristics of the memory cell.

Hereinafter, the nonvolatile semiconductor memory in the case where the reference erase process (step # 102 to step # 112, batch erase process, erase verify process, overerase verify process and repair write process) is repeatedly executed by the method of the present invention of the present embodiment The current consumption of the device 1 will be described. Here, FIG. 4 shows the transition of the control gate voltage of the selected memory cell to be erased and the transition of the consumption current of the nonvolatile semiconductor memory device 1 when the reference erase process in this embodiment is repeatedly executed. In FIG. 4, periods C1 to Cx (x is an integer equal to or greater than 1) correspond to each reference processing step, and the voltage V _GND indicates the ground voltage.

As shown in FIG. 4, in the initial setting of time t0 to te1 (step # 101), the control gate voltage of the selected memory cell in the memory cell block to be erased is 0 V (V _GND ).

  When execution of the batch erase process (step # 102) is started at time te1, a negative erase voltage pulse Vn1 (−10 V in this embodiment) is applied to the control gates of all memory cells in the memory cell block to be erased. Is applied. In the batch erase process of the present embodiment, since the batch erase process is performed under the voltage conditions shown in FIG. 3, the current consumption Wn1 in the batch erase process is the same as in the prior art between the bands from the source of the selected memory cell to the semiconductor substrate. The current becomes dominant and decreases according to the elapsed time from the start of application of the erase voltage pulse Vn1.

  Subsequently, when execution of the erase verify process (step # 103) is started at time tv10, a positive voltage is applied to the control gate of the memory cell to be erase verified, that is, the memory cell at the address indicated by the address variable. An erase verify voltage pulse Vev10 is applied. The consumption currents Wev10 to Wevx0 in the erase verify process are larger than the consumption currents Wn1 to Wnx in the batch erase process because the sense amplifier is driven.

  Subsequently, when execution of the overerase verify process (step # 106) is started at time tov10, the control gate of the memory cell to be subjected to the overerase verify process, that is, the memory cell at the address indicated by the address variable, A positive over-erase verify voltage pulse Vov10 is applied. In the present embodiment, the voltage amplitude of the overerase verify voltage pulse Vov10 is set larger than the voltage amplitude of the erase verify voltage pulse Vev10 (voltage Vov10> voltage Vev10), as in the case of the prior art. As shown in FIG. 4, the current consumption Wov10 in the overerase verify process is such that the voltage amplitude of the overerase verify voltage pulse Vov10 is set larger than the voltage amplitude of the erase verify voltage pulse Vev10. It becomes larger than Wev10.

  Similarly, in other reference erase steps, the voltage amplitude of the overerase verify voltage pulse is set to be larger than the voltage amplitude of the erase verify voltage pulse between the processes included in the same reference erase step. The current consumption in is larger than the current consumption in the erase verify process.

  If an overerased memory cell is detected in the overerase verify process (step # 106), a repair process (step # 108) is executed. In the repair process at time top10, a positive repair write voltage pulse Vop10 is applied to the control gate of the overerased memory cell to be repaired. The voltage amplitude and pulse width of the repair write voltage pulse Vop10 are set according to the characteristics of the memory cell. As in the case of the prior art, the current consumption Wop10 in the repair writing process is such that the number of overerased memory cells to be subjected to the repair writing process is the memory to be processed by the batch erase process, the erase verify process, and the overerase verify process. Since it is smaller than the number of cells, it is smaller than the current consumption in other processes.

  In the reference erase process C1 of FIG. 4, all of the batch erase process (step # 102), the erase verify process (step # 103), the overerase verify process (step # 106), and the repair process (step # 108) are executed. For example, when an overerased memory cell is not detected in the overerase verify process (step # 106), the repair process (step # 108) is not executed as shown in the reference erase process Cx.

  In this embodiment, the overerase verify process (step # 106) and the repair process (step # 108) are executed after the erase verify process (step # 103). However, the overerase verify process (step # 106) is performed. ) And the repair process (step # 108), the erase verify process (step # 103) may be executed. The current consumption in this case has the same correspondence as the case shown in FIG.

Second Embodiment
A second embodiment of the method of the present invention will be described with reference to FIGS. In the present embodiment, the case where the setting of the erase voltage pulse used in the batch erase process and the repair write voltage pulse used in the repair process are different from those in the first embodiment will be described. Specifically, in the first embodiment, the case where the setting of the repair write voltage pulse is fixed and the setting of the erase voltage pulse used in the batch erase process is changed every reference erase process has been described. A case will be described in which the setting of the erase voltage pulse is fixed and the setting of the repair write voltage pulse used in the repair process is changed for each reference erase process.

  In the present embodiment, the configuration of the nonvolatile semiconductor memory device 1 to which the method of the present invention is applied is the same as the configuration of the nonvolatile semiconductor memory device 1 of the first embodiment shown in FIG.

  The method of the present invention of this embodiment will be described with reference to FIGS. Here, FIG. 5 shows a processing procedure of the method of the present invention in the present embodiment.

  The nonvolatile semiconductor memory device 1 of this embodiment is configured to repeatedly execute a reference erase process including an erase verify process and a batch erase process, as in the first embodiment. Each time, an over-erase verify process and a repair process are executed. Further, the processing procedures of steps # 101, # 103 to # 107, and # 109 to # 111 shown in FIG. 5 are the same as those in the first embodiment.

  In the nonvolatile semiconductor memory device 1, when the UI circuit 20 receives an erase request for a predetermined memory cell block by an external command, first, the write state machine 30 performs initial setting (step # 101). Here, as in the first embodiment, the value of the start address of the memory cell block to be erased is set in the address variable.

  Subsequently, the nonvolatile semiconductor memory device 1 executes batch erase processing for applying an erase voltage pulse to all the memory cells constituting the memory cell block to be erased based on a predetermined erase voltage condition (step # 201). Batch erase process). In this embodiment, the amplitude and pulse width of the erase voltage pulse used in the batch erase process are fixedly set. Specifically, the batch erase process is performed using the same erase voltage pulse as that of the nonvolatile semiconductor memory device according to the prior art shown in FIG. Therefore, here, a negative voltage of −10 V is applied to the word lines WL0 to WLm−1 connected to the control gates of the memory cells, and a positive voltage of 10 V is applied to the source line SL connected to the sources of the memory cells.

  Subsequently, the nonvolatile semiconductor memory device 1 executes an erase verify process for each of the memory cells at the address indicated by the address variable in the memory cell block to be erased (step # 103, erase verify process). If there is at least one unerased memory cell determined to be in an unerased state by the erase verify process (Yes in step # 104), a re-erase flag is set to indicate that a batch erase process is required again (Step # 105).

  Subsequently, the non-volatile semiconductor memory device 1 performs overerase verify processing on each of the memory cells at the address indicated by the address variable in the erase target memory cell block (step # 106, overerase verify process).

  Subsequently, when there is an overerased memory cell that is determined to be in the overerased state in the overerase verify process in step # 106 (Yes branch in step # 107), the nonvolatile semiconductor memory device 1 stores the overerased memory. A repair write process for applying a repair write voltage pulse to the cell based on a repair voltage condition for repairing the over-erased state is executed (step # 202, repair process). Here, FIG. 6 shows repair voltage conditions in the present embodiment. Specifically, for example, in the first repair writing process, in the erase target memory cell block shown in FIG. 9, a positive voltage of 3.5 V is applied to the word lines WL0 to WLm−1 connected to the control gates of the memory cells. A positive voltage of 5V is applied to the bit lines BL0 to BLn-1 connected to the drain of the memory cell to be repaired and the source line SL connected to the source of each memory cell is connected to the ground voltage of 0V. After executing the repair process of step # 202, the process proceeds to step # 103, and the erase verify process is executed for each memory cell having the same address.

  If there is no overerased memory cell determined to be in the overerased state in the overerase verify process of step # 106 (No branch in step # 107), the value of the address variable is incremented (step # 109), and the erase target Steps until the erase verify process (step # 103), the over-erase verify process (step # 106) and the repair write process (step # 202) are completed for all the memory cells in the memory cell block (No branch at step # 110). Steps # 103 to # 107 and # 202 are repeatedly executed.

  When the erase verify process (step # 103), the over-erase verify process (step # 106), and the repair write process (# 202) are completed for all the memory cells in the erase target memory cell block (Yes branch at step # 110), the nonvolatile memory When the re-erase flag indicating that it is necessary to execute the batch erase process is set (Yes in step # 111), the volatile semiconductor memory device 1 again performs the reference erase process (steps # 102 to # 111). ), The amplitude of the repair write voltage pulse used in the next repair process (step # 202) is reset based on the repair voltage condition (step # 203), and the address variable is initialized.

  Specifically, in step # 203, the second and subsequent repair processes are set. The repair voltage condition shown in FIG. 6 is set so as to reduce the amplitude of the repair write voltage pulse applied to the control gate of the overerased memory cell every time the repair write process is executed. Specifically, in the repair voltage condition shown in FIG. 6, in the second to fourth repair steps (step # 202), the amplitude of the repair write voltage pulse applied to the control gate of the over-erased memory cell is 0.5V each. It is set to decrease. In the present embodiment, it is not practical to set the amplitude of the repair write voltage pulse applied to the control gate to a value smaller than 2 V due to the restriction of the applied voltage in the write process, etc. In the erasing process, the repair process is not executed. In the present embodiment, the repair voltage condition shown in FIG. 6 is used. However, the present invention is not limited to this. The initial value and the decrease amount of the repair write voltage pulse are set according to the manufacturing process and the characteristics of the memory cell. .

  By setting the repair voltage condition in this way, the amount of increase in the threshold voltage of the memory cell due to the repair write process can be reduced every time the repair write process is executed. As a result, the method of the present embodiment of the present embodiment reduces the threshold voltage of the memory cell by the batch erase process with respect to the increase amount of the threshold voltage of the memory cell in the repair write process every time the reference erase process is executed. An effect similar to that of the first embodiment in which the amount is relatively increased can be obtained.

  In the present embodiment, the configuration for reducing the amplitude of the repair write voltage pulse applied to the control gate of the memory cell has been described. However, the present invention is not limited to this. For example, not the voltage amplitude but the pulse width may be decreased, or both the voltage amplitude and the pulse width may be decreased. Further, for example, the voltage amplitude may be first reduced according to the repair voltage condition shown in FIG. 6, and then the pulse width may be sequentially reduced. Furthermore, in this embodiment, the amount of decrease in the amplitude or pulse width of the repair write voltage pulse is set to a constant amount (0.5 V), but it is configured to decrease under other conditions, such as decreasing by a constant rate. May be.

  As shown in FIG. 5, the nonvolatile semiconductor memory device 1 proceeds to step # 201 upon completion of resetting of the repair write voltage pulse and the like in the second and subsequent repair write processes in step # 203, and once again in a batch. An erasing process (step # 201) is executed.

  In step # 111, when the re-erase flag indicating that the batch erase process needs to be executed is not set (No branch in step # 111), the nonvolatile semiconductor memory device 1 is in the memory cell block to be erased. It is determined that there are no over-erased and unerased memory cells and all the memory cells are in an erased state, and the process is terminated.

<Third Embodiment>
A third embodiment of the method of the present invention will be described with reference to FIGS. In the present embodiment, a case where the execution procedure of the erase verify process and the overerase verify process is different from the first and second embodiments will be described. Specifically, in the first and second embodiments, the case where the erase verify process and the overerase verify process are sequentially executed has been described. However, in this embodiment, the erase verify process and the overerase verify process are performed in parallel. Will be described.

  First, the configuration of the nonvolatile semiconductor memory device 1 to which the method of the present invention is applied will be briefly described with reference to FIGS.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 1 of this embodiment includes a memory cell array 70, an input / output buffer 10, a buffer circuit 40, a sense amplifier circuit 60, a UI circuit 20, a control register circuit 50, and a write state. A machine 30 is provided. The configurations of the input / output buffer 10, the buffer circuit 40, the UI circuit 20, and the control register circuit 50 are the same as those in the first embodiment.

  The memory cell array 70 of the present embodiment includes a plurality of multi-value memory cells configured to be able to store information of three or more values corresponding to an erase state and a plurality of write states. Hereinafter, description will be made assuming a quaternary memory cell configured to be able to store information corresponding to the erased state and the three written states. The configuration of the quaternary memory cell is the same as the configuration of the quaternary memory cell shown in FIG.

  The sense amplifier circuit 60 of the present embodiment is configured to include a sense amplifier group including a plurality of sense amplifiers for binary determination of the storage state of the memory cell for each bit line. Here, FIG. 7 shows a schematic configuration example of the sense amplifier circuit 60 of the present embodiment. In FIG. 7, for the sake of simplicity, one sense amplifier group among a plurality of sense amplifier groups constituting the sense amplifier circuit 60 is shown.

  Specifically, as shown in FIG. 7, the sense amplifier circuit 60 of this embodiment includes three sense amplifiers for each bit line of the memory cell array 70 in order to determine the storage state of the quaternary memory cell. Has been. Each of the sense amplifiers 610, 620, and 630 determines the storage state of the memory cell to be processed by binary determination that compares the reference voltage serving as a reference for binary determination and the threshold voltage of the memory cell to be processed. It is configured as follows.

  More specifically, the sense amplifier 610 includes a differential amplifier circuit 611 and a latch circuit 612. The input node SEN of the differential amplifier circuit 611 is input to the drain of the quaternary memory cell to be processed. The node Vr1 is connected to a drain of a reference memory cell having a reference voltage threshold voltage (for example, the voltage VrL in the reading process) that serves as a criterion for binary determination. Similarly, the sense amplifier 620 includes a differential amplifier circuit 621 and a latch circuit 622. The input node SEN of the differential amplifier circuit 621 is connected to the drain of the quaternary memory cell to be processed at the input node Vr2. Are respectively connected to the drains of the reference memory cells having a reference voltage threshold voltage (for example, the voltage VrM in the reading process) that serves as a criterion for binary determination. The sense amplifier 630 includes a differential amplifier circuit 631 and a latch circuit 632. The input node SEN of the differential amplifier circuit 631 is the drain of the quaternary memory cell to be processed, and the input node Vr3 is 2 Each is connected to the drain of a reference memory cell having a reference voltage threshold voltage (for example, voltage VrH in the reading process) that serves as a reference for value determination. In the reading process, the drains of the three reference memory cells having the threshold voltages VrL, VrM, and VrH shown in FIG. 12 are used as the input node Vr1 of the differential amplifier circuit 611 and the input of the differential amplifier circuit 621. By connecting the node Vr2 and the input node Vr3 of the differential amplifier circuit 631, respectively, three binary determinations are executed simultaneously to determine the storage state.

  Further, in the present embodiment, erase verify processing is executed using one of the sense amplifiers 610, 620, 630 of the sense amplifier circuit 60, and one other sense amplifier excluding the sense amplifier 610 used in the erase verify processing. The over-erase verify process is executed using 620. As a result, the erase verify process and the over-erase verify process can be executed simultaneously. In the present embodiment, in order to set the reference voltage for the erase verify process or overerase verify process in the erase verify process or overerase verify process, the threshold voltage for the erase verify process or overerase verify process is set. Although the description will be made on the assumption that the reference memory cell is switched to a configuration having a reference memory cell, a configuration in which the number of reference memory cells is controlled or a configuration in which the voltage applied to the control gate of the reference memory cell is controlled may be employed.

  Next, the method of the present invention of this embodiment will be described with reference to FIG. Here, FIG. 8 shows a processing procedure of the method of the present invention in the present embodiment.

  Note that the nonvolatile semiconductor memory device 1 of the present embodiment is configured to repeatedly execute a reference erase process including an erase verify process and a batch erase process, as in the first and second embodiments. Further, in the reference erase process, an over-erase verify process and a repair process are executed each time. Further, the processing procedures of steps # 101, # 102, # 104, # 105, and # 107 to # 112 shown in FIG. 8 are the same as those in the first embodiment.

  In the nonvolatile semiconductor memory device 1, when the UI circuit 20 receives an erase request for a predetermined memory cell block by an external command, first, the write state machine 30 performs initial setting (step # 101). Here, as in the first embodiment, the value of the start address of the memory cell block to be erased is set in the address variable.

  Subsequently, the nonvolatile semiconductor memory device 1 executes batch erase processing for applying an erase voltage pulse to all the memory cells constituting the memory cell block to be erased based on a predetermined erase voltage condition (step # 102). Batch erase process). The erase voltage condition of this embodiment is the same as the erase voltage condition of the first embodiment shown in FIG.

  Subsequently, the nonvolatile semiconductor memory device 1 simultaneously executes the erase verify process and the overerase verify process for each of the memory cells at the address indicated by the address variable in the erase target memory cell block (step # 301, erase verify process). And over-erase verify process). Specifically, in this embodiment, for example, the reference voltage Ve is applied to the input node Vr1 of the differential amplifier circuit 611 constituting the sense amplifier 610 of the sense amplifier circuit 60 shown in FIG. A drain of a reference memory cell having a threshold voltage is connected. Further, in order to execute the overerase verify process, the drain of the reference memory cell having the threshold voltage of the reference voltage Ve0 is connected to the input node Vr2 of the differential amplifier circuit 621 constituting the sense amplifier 620. As a result, the result of the erase verify process is output to the output node DATL, and the result of the over-erase verify process is output to the output node DATM. Although the sense amplifier 610 is used for the erase verify process and the sense amplifier 620 is used for the over erase verify process here, the sense amplifier used in the erase verify process and the over erase verify process can be arbitrarily selected.

  Subsequently, if there is any non-erased memory cell that is determined to be in an unerased state by the erase verify process in the nonvolatile semiconductor memory device 1 (Yes in step # 104), the batch erase process is required again. Then, a re-erasure flag indicating that this is set is set (step # 105).

  Subsequently, when there is an overerased memory cell that is determined to be in the overerased state in the overerase verify process in step # 301 (Yes branch in step # 107), the nonvolatile semiconductor memory device 1 stores the overerased memory. A repair write process for applying a repair write voltage pulse to the cell based on a repair voltage condition for repairing the overerased state is executed (step # 108, repair process), and then the process proceeds to step # 301. The repair voltage condition of the present embodiment is the same as the repair voltage condition of the first embodiment.

  If there is no overerased memory cell determined to be in the overerased state in the overerase verify process of step # 301 (No branch in step # 107), the value of the address variable is incremented (step # 109), and the erase target Steps # 301, # until all of the memory cells in the memory cell block are erase verified, overerased verified (step # 301), and repaired and written (step # 108) are finished (No branch at step # 110). 104, # 105, # 107, and # 108 are repeatedly executed.

  When all of the memory cells in the memory cell block to be erased have completed the erase verify process and over-erase verify process (step # 301) and the repair write process (step # 108) (Yes branch at step # 110), the nonvolatile semiconductor memory If the re-erasure flag indicating that it is necessary to execute the batch erasure process is set (Yes in step # 111), the apparatus 1 executes the reference erasure process (steps # 102 to # 111) again. Therefore, the amplitude of the erase voltage pulse used in the next batch erase process (step # 102) is reset based on the erase voltage condition (step # 112), and the address variable is initialized.

  In the present embodiment, since the erase verify process and the over-erase verify process are executed at the same time, the time required for executing the reference erase process can be shortened. Further, as shown in FIG. 7, in the case of the nonvolatile semiconductor memory device 1 having a plurality of sense amplifiers for determining the storage state of one memory cell, the present invention is not added to the present invention without newly adding a sense amplifier. A method can be applied, and an increase in chip area can be suppressed.

  In the present embodiment, in the case of the first embodiment, that is, in the case where the setting of the erase voltage pulse used in the batch erase process is changed for each reference erase process, the erase verify process and the overerase verify process are executed simultaneously. Although the case has been described, the present invention is not limited to this. In the case of the second embodiment, that is, when the setting change of the repair write voltage pulse used in the repair process is performed for each reference erase process, or the setting change of the erase voltage pulse used in the batch erase process for each reference erase process; When both the setting change of the repair write voltage pulse used in the repair process is performed simultaneously or in combination, the erase verify process and the overerase verify process may be executed simultaneously.

<Fourth embodiment>
A fourth embodiment of the method of the present invention will be described with reference to the drawings. In the present embodiment, a case where the configuration of the repair writing process is different from the first to third embodiments will be described. Specifically, in the first to third embodiments, the case where the repair writing process is executed in units of addresses has been described, but in this embodiment, the repair writing process is executed in units of buffers consisting of a plurality of addresses. Will be described.

  The configuration of the nonvolatile semiconductor memory device 1 in this embodiment will be described with reference to FIG.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 1 of the present embodiment has a memory cell array 70, an input / output buffer 10, a buffer circuit 40, a sense amplifier circuit 60, a UI, as in the first to third embodiments. The circuit 20 and the light state machine 30 are provided. The configurations of the memory cell array 70, the input / output buffer 10, the sense amplifier circuit 60, the UI circuit 20, and the control register circuit 50 of the nonvolatile semiconductor memory device 1 are the same as those in the first to third embodiments.

  The buffer circuit 40 of the present embodiment is configured to be able to record the expected value data used in the writing process in units of buffers, and to store the result of the overerase verify process when executing the overerase verify process.

  The write state machine 30 of the present embodiment is configured to be able to execute write processing in units of buffers. In the writing process in units of buffers, the expected value data stored in the buffer circuit 40 in units of buffers are collectively written into the memory cell array 70 with one external command.

  Further, the write state machine 30 of the present embodiment includes an erase verify process (step # 103 in FIGS. 2 and 5 and step # 301 in FIG. 8) and a repair write process (step # in FIGS. 2 and 5) in the reference erase process. 106, step # 301) of FIG. 8 can be executed in units of buffers. In the overerase verify process, an overerase verify process is executed in units of buffers, and the result is stored in the buffer circuit 40 in units of buffers. Further, in the repair process (step # 108 in FIGS. 2 and 8, step # 202 in FIG. 5 and FIG. 8), the result of the overerase verify process stored in the buffer circuit 40 in the overerase verify process and the repair voltage condition Based on this, a repair write voltage pulse is simultaneously applied to a plurality of over-erased memory cells to be repaired.

  In the present embodiment, since the reference erase process is performed in units of buffers, it is possible to shorten the execution time of the repair process for the over-erased memory cells. Thus, for example, it is possible to cope with an increase in the execution time of the repair process due to an increase in the number of overerased memory cells detected due to an increase in the size of the memory cell array 70 or the like. Note that the writing process in units of buffers is effective in increasing the writing speed, and is therefore mounted in many conventional nonvolatile semiconductor memory devices. Therefore, in the case of a nonvolatile semiconductor memory device equipped with a function of performing writing processing in units of buffers, the method of the present invention can be easily applied without increasing the amount of change of the device configuration from the past.

<Another embodiment>
<1> In the first to fourth embodiments, in the reference erase process, in addition to the erase verify process (erase verify process) and the batch erase process (collective erase process), an over erase verify process (over erase verify process) is performed each time. In the above description, the repair writing process (repair process) is executed. However, the present invention is not limited to this.

  The over-erase verify process and the repair process may be executed only when predetermined repair execution conditions are met. Specifically, for example, an execution period and a non-execution period for executing the over-erase verification process and the repair process may be set. In this case, for example, in the relatively early reference erasure process in which the number of overerased memory cells is considered to be very small, the overerase verify process and the repair process are not executed, and the number of overerased memory cells is somewhat It is set so that the overerase verify process and the repair process are executed in the reference erase process at the stage of occurrence.

  Further, for example, the over-erase verify process and the repair process may be executed every predetermined number of reference erase processes. Further, as the number of executions of the reference erase process increases, the ratio of the reference erase process for executing the overerase verify process and the repair process may be increased, or a combination of these multiple repair execution conditions. Anyway.

  <2> In the first and third embodiments, the setting of the erase voltage pulse in the batch erase process is changed for each reference erase process. In the second embodiment, the repair in the repair write process is performed for each reference erase process. Although the case where the setting of the write voltage pulse is changed has been described, the present invention is not limited to this.

  In the first to fourth embodiments, for example, for each reference erase process, both the erase voltage pulse setting change in the batch erase process and the repair write voltage pulse setting change in the repair write process are executed simultaneously. Also good.

  Further, for example, according to a predetermined selection condition, either or both of the setting change of the erase voltage pulse in the batch erasing process and the setting change of the repair writing voltage pulse in the repair writing process may be selectively executed. good. In this case, for example, first, the setting of the erase voltage pulse according to the first embodiment shown in FIG. 3 is changed, and the amplitude and pulse width of the erase voltage pulse are increased due to restrictions on the peak value of the voltage amplitude of the applied voltage pulse. It may be configured to change the setting of the repair write voltage pulse according to the second embodiment shown in FIG.

1 is a block diagram showing a schematic partial configuration example of a nonvolatile semiconductor memory device to which an erasing method according to the present invention is applied. The flowchart which shows the process sequence in 1st Embodiment of the erasing method based on this invention. Table showing erase voltage conditions in the first embodiment of the erase method according to the present invention 6 is a graph showing the relationship between the control gate voltage and current consumption of a memory cell in each reference erase step in a nonvolatile semiconductor memory device to which the erase method according to the present invention is applied. The flowchart which shows the process sequence in 2nd Embodiment of the erasing method based on this invention. Table showing repair voltage conditions in the second embodiment of the erasing method according to the present invention A circuit diagram showing an example of schematic composition of a sense amplifier circuit in a 3rd embodiment of a nonvolatile semiconductor memory device to which an erasing method concerning the present invention is applied. The flowchart which shows the process sequence in 3rd Embodiment of the erasing method based on this invention. Schematic partial circuit diagram showing a partial schematic configuration example of a memory cell array Conceptual diagram showing a schematic configuration example of a memory cell of an ETOX type flash memory Schematic explanatory diagram showing an example of threshold voltage distribution of a binary memory cell Schematic explanatory diagram showing an example of threshold voltage distribution of a quaternary memory cell Table showing an example of voltage conditions for read processing, write processing, and erase processing for binary memory cells The flowchart which shows an example of the process sequence of the erasing method based on a prior art The graph which shows the relationship between the control gate voltage of a memory cell and current consumption in the non-volatile semiconductor memory device which applied the erasing method based on a prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 10 Input / output buffer 20 UI circuit 30 Write state machine 40 Buffer circuit 50 Control register circuit 60 Sense amplifier circuit 70 Memory cell array 610 Sense amplifier 620 Sense amplifier 630 Sense amplifier 611 Differential amplifier circuit 621 Differential amplifier circuit 631 Differential amplifier circuit 612 Latch circuit 622 Latch circuit 632 Latch circuit 1001 Control gate 1002 Floating gate 1003 Drain 1004 Source 1005 Semiconductor substrate M Memory cell WL Word line BL Bit line SL Source line

Claims (6)

A non-volatile semiconductor memory device erasing method comprising a memory cell array including a plurality of memory cells and capable of performing batch erasing processing in units of a memory cell group composed of a predetermined number of the memory cells,
An erase verify process for executing an erase verify process for determining whether or not the storage state of the memory cell is an unerased state for each of the memory cells of the memory cell group to be erased that is the target of the batch erase process;
When there is the memory cell that is determined to be in the unerased state in the erase verify step, the erase voltage is applied to all the memory cells constituting the erase target memory cell group based on a predetermined erase voltage condition. A batch erase process for executing a batch erase process to apply a pulse;
An overerase verify step for performing an overerase verify process for determining whether or not the storage state of the memory cell is an overerase state for each of the memory cells of the erase target memory cell group;
When there is the memory cell that is determined to be in the overerased state in the overerase verify step, the memory cell in the overerase state is based on a repair voltage condition for repairing the overerase state. A repair process for executing a repair write process for applying a repair write voltage pulse, and
When the reference erase process including the erase verify process and the batch erase process is repeatedly performed, the overerase verify process and the repair process are performed as the reference erase every time or only when a predetermined repair execution condition is met. Execute in the process,
In the second and subsequent batch erase steps, using the erase voltage pulse in which at least one of the amplitude or the pulse width of the erase voltage pulse in the previous batch erase step is increased based on the erase voltage condition. An erase method for a nonvolatile semiconductor memory device, wherein the batch erase process is executed. A non-volatile semiconductor memory device erasing method comprising a memory cell array including a plurality of memory cells and capable of performing batch erasing processing in units of a memory cell group composed of a predetermined number of the memory cells,
An erase verify process for executing an erase verify process for determining whether or not the storage state of the memory cell is an unerased state for each of the memory cells of the memory cell group to be erased that is the target of the batch erase process;
When there is the memory cell that is determined to be in the unerased state in the erase verify step, the erase voltage is applied to all the memory cells constituting the erase target memory cell group based on a predetermined erase voltage condition. A batch erase process for executing a batch erase process to apply a pulse;
An overerase verify step for performing an overerase verify process for determining whether or not the storage state of the memory cell is an overerase state for each of the memory cells of the erase target memory cell group;
When there is the memory cell that is determined to be in the overerased state in the overerase verify step, the memory cell in the overerase state is based on a repair voltage condition for repairing the overerase state. A repair process for executing a repair write process for applying a repair write voltage pulse, and
When the reference erase process including the erase verify process and the batch erase process is repeatedly performed, the overerase verify process and the repair process are performed as the reference erase every time or only when a predetermined repair execution condition is met. Execute in the process,
In the second and subsequent repair steps, using the repair write voltage pulse in which at least one of the amplitude or the pulse width of the repair write voltage pulse in the previous repair step is reduced based on the repair voltage condition A method for erasing a nonvolatile semiconductor memory device, wherein the repair writing process is executed.   In the second and subsequent batch erase steps, using the erase voltage pulse in which at least one of the amplitude or the pulse width of the erase voltage pulse in the previous batch erase step is increased based on the erase voltage condition. The method for erasing a nonvolatile semiconductor memory device according to claim 2, wherein the batch erasing process is executed.   4. The repair write process is performed by applying the repair write voltage pulse to a plurality of the memory cells in the over-erased state at the same time in the repair process. 5. A method for erasing a nonvolatile semiconductor memory device according to claim 1. In the overerase verify process, in the execution of the overerase verify process, the result of the overerase verify process is stored in a predetermined buffer circuit;
5. The nonvolatile memory according to claim 1, wherein, in the repair process, the repair write process is executed based on a result of the over-erase verify process stored in the buffer circuit. 6. A method of erasing a semiconductor memory device. The memory cell is configured to be capable of storing information of three or more values corresponding to an erase state and a plurality of write states,
The nonvolatile semiconductor memory device includes a sense amplifier circuit including a sense amplifier group including a plurality of sense amplifiers that determine a storage state of the memory cell in a binary manner for each predetermined memory cell.
In the erase verify step, for each of the memory cells to be erased, the erase verify process is executed using one of the sense amplifiers constituting the corresponding sense amplifier group,
In the over-erase verify step, one sense amplifier other than the sense amplifier used in the erase verify process is used among the sense amplifiers constituting the corresponding sense amplifier group for each memory cell to be erased. 6. The method of erasing a nonvolatile semiconductor memory device according to claim 1, wherein the overerase verify process is executed simultaneously with the erase verify process.

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