JP2007102923A - Nonvolatile semiconductor storage device and its data erasing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a period of data erasing operation of a flash memory. <P>SOLUTION: The flash memory of which the data are collectively erased in a block unit with respect to a memory cell array wherein the blocks including a plurality of memory cells are arranged, is equipped with: a first step to collectively erase the data by applying erase voltages to the memory cells in the block; a second step to confirm whether the memory cell having the threshold higher than a first voltage EV does not exist with respect to the memory cells in the block; a third step, when the memory cell having the threshold higher than the EV exists as the result of above confirmation, to confirm whether the memory cell having the threshold higher than the EV does not exist, by changing the erase voltage at least once among from its initial value to the maximum value and collectively erasing them; and a fourth step, when the memory cell having the threshold higher than the EV exists as the above result, to confirm whether the memory cell having the threshold higher than the EV does not exist, by collectively erasing the erase voltage while keeping the maximum value after the erase voltage value becomes maximum. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a data erasing method thereof, and more particularly to an erasing voltage control circuit at the time of batch erasing operation in which erasing is performed in units of blocks having a plurality of memory cells. Type flash memory.

  For example, in a NOR type flash memory that performs erasing in units of blocks having a plurality of memory cells, by specifying a bit line and a word line and applying a voltage during a data write operation (operation for injecting electrons into the memory cell) It is possible to specify a memory cell to be written in 1-bit units. In an actual product, a plurality of bits may be written simultaneously in order to speed up writing. On the other hand, in the data erasing operation (operation for removing injected electrons from the memory cell), all memory cells having a common well region by applying a bias to the word line and the well region (usually in block units). Erase all at once.

  In the data erase operation in the NOR type flash memory, first, pre-erase programming (Pre-Program) is performed, then batch erase is performed, and whether or not all memory cells are below the threshold voltage EV (Erase Verify Level). Judgment (verify operation) is performed. This batch erase and verify operation is repeated until all memory cells are equal to or lower than the threshold voltage EV. Normally, the voltage application time for batch erase is set so that the batch erase and verify operations are repeated a plurality of times.

  When batch erasing is repeatedly performed as described above, conventionally, the voltage applied to the word line and the well region is constant. At this time, each memory cell actually varies in various dimensions, film thickness, and the like, and when the batch erase operation ends, memory cells (overerased cells) that have disappeared excessively are generated. Since this overerased cell has a large leakage current, it causes read failure and write failure.

  Therefore, a weak write (Weak Program) operation is performed on a memory cell that has disappeared more than the threshold voltage OEV (Over Erase Verify Level). In this weak write operation, it is determined for each memory cell in the block whether or not the threshold voltage is greater than or equal to OEV. Do weak writing. Weak writing means writing performed by applying a lower voltage to the drain and gate rather than applying a high voltage to write in the “0” state.

  As described above, after performing weak writing to the memory cell, the verify operation is performed again. Again, if the threshold value of the memory cell is lower than OEV, weak writing is performed again. Thus, verify and weak writing are repeated until the threshold value of the memory cell becomes equal to or higher than OEV. When the threshold value of the memory cell becomes equal to or higher than the voltage OEV, the process proceeds to the next memory cell.

  After the weak writing to all the memory cells in the block is completed, it is confirmed whether or not the threshold value of all the memory cells exceeds the threshold voltage EV. If there is no cell exceeding the EV, The erase operation ends. If there is a cell exceeding EV, the processing after the batch erase described above is performed again.

  However, the following series of operations as described above have the following problems. First, the erase operation has three steps, namely, pre-erase write, batch erase, and weak write, so that the erase time becomes longer. In order to shorten the erasing time, it is necessary to delete any of the above three steps. However, since the batch erasing is an erasing operation itself, it cannot be deleted. Also, weak writing cannot be deleted because it compensates for variations in memory cells. When programming before erasure is deleted, batch erasure is performed from a state in which a “1” state and a “0” state coexist as memory cell states. Therefore, while the “0” state memory cell becomes lower than the threshold voltage EV, the threshold value of the “1” state memory cell also decreases as a whole. The distribution of memory cells becomes larger on the lower threshold side. As a result, the number of memory cells that become lower than the threshold voltage OEV increases, which causes an increase in erase time or an erase operation that does not end within a specified time and ends abnormally.

In Patent Document 1, it is determined whether or not there is an over-erased memory cell transistor for each of a plurality of digit lines after all the memory cell transistors are collectively erased, and there is an over-erased memory cell transistor. When it is determined that the memory cell transistor is in an over-erased state, a shallow writing is performed only on the over-erased memory cell transistor.
Japanese Patent Laid-Open No. 8-255489

  The present invention has been made to solve the above-described conventional problems, and an object thereof is to provide a nonvolatile semiconductor memory device and a data erasing method thereof that can shorten the data erasing operation time.

  The nonvolatile semiconductor memory device of the present invention performs writing to a memory cell array in which at least one block including a plurality of memory cells is arranged, and a plurality of memory cells included in a selected block in the memory cell array. And a write / erase circuit for collectively erasing a plurality of memory cells included in the selected block, and a control circuit for controlling a write operation and an erase operation in the write / erase circuit, A means for confirming whether or not there is a memory cell having a threshold higher than a first predetermined voltage for the plurality of memory cells, and among the plurality of memory cells included in the selected block, When there is a memory cell whose threshold is higher than the specified voltage, the erase voltage erase voltage is set to the initial value every time batch erase is performed once or multiple times. Erasing in batches until reaching the maximum value, and checking whether there is a memory cell having a threshold higher than the first predetermined voltage, and after the erase voltage reaches the maximum value, When there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the selected block, the erase is performed at the same time while the erase voltage remains at the maximum value, and the threshold value is set higher than the first predetermined voltage. Means for checking whether or not there is a high memory cell.

  According to the nonvolatile semiconductor memory device data erasing method of the present invention, at least one block is selected from a memory cell array in which at least one block including a plurality of memory cells is arranged, and is included in the selected block. In a data erasing method of a nonvolatile semiconductor memory device that erases data held in a plurality of memory cells at once, batch erasing is performed by applying an erasing voltage to a plurality of memory cells included in the selected block. A first step of performing, a second step of confirming whether or not there is a memory cell having a threshold value higher than a first predetermined voltage for a plurality of memory cells included in the selected block, and the selected block If there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the memory cell, the erase voltage is set to the initial value. A third step of performing batch erasure by changing at least once up to the maximum value and checking whether or not there is a memory cell having a threshold higher than the first predetermined voltage, and the erase voltage reaches the maximum value After that, if there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the selected block, batch erasure is performed with the erase voltage kept at the maximum value, and the first predetermined And a fourth step of checking whether or not there is a memory cell having a threshold value higher than the voltage.

  According to the nonvolatile semiconductor device and the data erasing method of the present invention, a series of erasing operations can be performed without performing pre-erase writing during the data erasing operation, and the data erasing operation time can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a flash memory according to a first embodiment of a nonvolatile semiconductor memory device of the present invention. The flash memory includes a command user interface (CUI) 11, a central processing unit (CPU) 12, a read-only memory (ROM) 13, an input / output circuit (I / I). O) 14, a decoder 15, a sense amplifier (S / A) 16, a memory cell array (Main Cell) 17, and a write / erase circuit (Prog / Erase Circuit) 18.

  The CUI 11 receives externally input signals such as a chip enable signal (CE) and a write enable signal (WE), an address signal (Address), and data (Data), processes them, and outputs them to the CPU 12. The CPU 12 controls the entire operation such as writing, erasing, and reading in the flash memory. The ROM 13 is a memory for storing a control program used by the CPU 12. For example, when the CPU 12 receives power supply, it loads firmware (control program) stored in the ROM 13 and executes predetermined processing to create various tables or write commands from the CUI 11 In response to the read command and the erase command, the corresponding area on the memory cell array 17 is accessed.

  The input / output circuit 14 inputs and outputs data with the outside. The decoder 15 selects a word line connected to the memory cell in the memory cell array 17 according to the address signal. The sense amplifier 16 reads the signal stored in the memory cell and outputs it to the holding circuit. The write / erase circuit 18 writes data into the memory cell or erases data stored in the memory cell. The memory cell array 17 includes at least one (a plurality in this example) block, and each block has a plurality of memory cells.

  FIG. 2 is a plan view showing a layout of a memory cell array of a NOR flash memory as an example of the memory cell array 17 in FIG. As shown in FIG. 2, control gate lines (word lines) CG9, CG10, CG11, CG12, and CG13 are formed in the row direction, and source lines SL10, SL11, and SL12 are formed so as to be parallel thereto. Yes. An active region is formed so as to be orthogonal to these control gate lines. In the region where the control gate line and the active region intersect, the memory cells M11 (1), M11 (2),..., M11 (6), the memory cells M12 (1), M12 (2),. 6) and other memory cells are formed. Further, bit line contact plugs BC are arranged in the row direction between the control gate lines CG10 and CG11 and on the drain region between the control gate lines CG12 and CG13.

  FIG. 3 is a circuit diagram showing a partial region T in the memory cell array 17 in FIG.

Each of the memory cells M11 (1), M11 (2), M12 (1), and M12 (2) is configured by a field effect transistor having a floating gate. A control gate line CG10 is connected to the gates of the memory cells M11 (1) and M11 (2). Similarly, a control gate line CG11 is connected to the gates of the memory cells M12 (1) and M12 (2). One end (drain) of the current path of the memory cell M11 (1) is connected to one end (drain) of the current path of the memory cell M12 (1), and the bit line BL10 is connected to this connection point. Similarly, one end (drain) of the current path of the memory cell M11 (2) and one end (drain) of the current path of the memory cell M12 (2) are connected, and the bit line BL11 is connected to this connection point. Yes. Further, a source line SL10 is connected to the other end (source) of the current path of the memory cell M11 (1) and the other end (source) of the current path of the memory cell M11 (2). Similarly, a source line SL11 is connected to the other end (source) of the current path of the memory cell M12 (1) and the other end (source) of the current path of the memory cell M12 (2).

  In the NOR flash memory shown in FIG. 2, 1-bit data is stored in each memory cell. It is possible to store “0” data or “1” data by changing the threshold value of the memory cell by injecting (writing) or removing (erasing) electrons into the memory cell. Note that in the case of a multi-value memory cell that stores more information than 1-bit data, for example, 2-bit data, in one memory cell, the threshold value of the memory cell is changed to form four states. A control program for controlling the erase operation is stored in the ROM 13. The CPU 12 reads a control program for controlling the erase operation from the ROM 13 and executes the erase operation. At this time, the erase operation is performed simultaneously or sequentially on some or all of the plurality of blocks.

  FIG. 4 is a flowchart showing a first example of a series of erase operations in the NOR flash memory according to the present embodiment. FIG. 5A and FIG. 5B show two examples of changes in the erase voltage during batch erase. FIGS. 6A to 6D show changes in threshold (data) distribution due to erasing / writing of the memory cells in the NOR flash memory shown in FIG.

Next, a first example of the erasing operation in the NOR flash memory according to the present embodiment will be described with reference to FIGS. 4, 5A, and 6A to 6D. In the block selected in the memory cell array 17, for example, as shown in FIG. 6A, memory cells in the “1” state (erased state) and “0” state (written state) are present randomly. Assume a case. First, batch erasure is performed once for all the memory cells in the selected block without performing pre-erase programming (Pre-Program) (step S1). The voltage applied to the well region is set to a voltage lower than the maximum set value. As shown in FIG. 6B, the threshold distribution of the memory cells in this state decreases as a whole in the threshold value of the memory cells in the “0” state, but the threshold value of the memory cells in the “1” state is almost the same. Does not fluctuate.

  Next, a determination (verify) operation is performed to determine whether or not the threshold values of all the memory cells are equal to or lower than an erase verify voltage EV (Erase Verify Level) (step S2). Normally, the voltage application time for batch erase is set so that the batch erase and verify operations are repeated a plurality of times, so the second batch erase operation is started. When the batch erase and the verify operation are repeated, the erase voltage (= positive voltage applied to the well region−negative voltage applied to the word line) is increased stepwise as shown in FIG. 5A, for example. That is, as shown in FIG. 5A, the voltage applied to the well region in the second batch erase is higher than the first voltage and lower than the maximum set value. After the second batch erase, it is similarly determined whether or not the threshold values of all the memory cells are equal to or lower than EV. The batch erase and verify operation are repeated until the threshold values of all the memory cells become EV or less. At this time, as shown in FIG. 5A, the voltage applied to the well region is increased stepwise with the number of batch erasures, and when the maximum set value is reached, the well region is erased at the subsequent batch erase. The voltage applied to is kept at the maximum value.

  At this time, as a method of increasing the erase voltage stepwise, if the negative voltage applied to the word line is lowered stepwise to increase the erase voltage stepwise instead of the voltage applied to the well region, In some cases, the voltage applied to the region is increased stepwise, and the negative voltage applied to the word line is decreased stepwise to increase the erase voltage stepwise.

  FIG. 6C shows a threshold distribution of memory cells in a state where the threshold values of all memory cells are equal to or lower than EV. As can be seen from FIG. 6C, when the batch erase operation is finished, each memory cell is overerased due to variations in various dimensions, film thickness, and the like (that is, overerasure in which the threshold is too low). Cell). Since this overerased cell has a large leakage current, it causes read failure and write failure. Therefore, weak writing (Weak Program) is performed on the memory cell whose threshold is lower than the overerase voltage OEV (Over Erase Verify Level). This weak write operation is as follows. It is determined for each memory cell in the block whether or not the threshold value is OEV or more (step S3). When the threshold value of the memory cell is lower than OEV, that is, if it has disappeared too much, weak writing is performed on the memory cell (step S4).

  Thus, after performing weak writing to the memory cell, the verify operation is performed again (step S3). Again, if the threshold value of the memory cell is lower than OEV, weak writing is performed again (step S4). Thus, verify and weak writing are repeated until the threshold value of the memory cell becomes equal to or higher than OEV. When the threshold value of the memory cell becomes equal to or higher than OEV, the process proceeds to the next memory cell.

  After weak writing is completed for all the memory cells in the block (step S5), it is confirmed whether the thresholds of all the memory cells do not exceed EV (step S6). If there is no memory cell whose threshold value exceeds EV, all erase operations are completed here. If there is a memory cell having a threshold value exceeding EV, the process returns to step S1 again, and the processes after batch erase are performed again. FIG. 6D shows the threshold distribution of the memory cells in a state where the threshold values of all the memory cells are EV or less and OEV or more.

  As described above, according to the first embodiment, in a series of data erasing operations, the data erasing operation time is shortened by increasing the erasing voltage in a batch erasing operation stepwise without performing pre-erase writing. be able to.

  Next, a second example of the erasing operation in the NOR flash memory according to the present embodiment will be described with reference to FIGS. 4, 5B, and 6A to 6D. In the block selected in the memory cell array 17, for example, as shown in FIG. 6A, memory cells in the “1” state (erased state) and “0” state (written state) are present randomly. Assume a case. First, batch erasure is performed once for all the memory cells in the selected block without performing pre-erase programming (Pre-Program) (step S1). The voltage applied to the well region is set to a voltage lower than the maximum set value. As shown in FIG. 6B, the threshold distribution of the memory cells in this state decreases as a whole in the threshold value of the memory cells in the “0” state, but the threshold value of the memory cells in the “1” state is almost the same. Does not fluctuate.

  Next, a determination (verification) operation is performed to determine whether or not the threshold values of all the memory cells are equal to or lower than the erase verification voltage EV (step S2). Normally, the voltage application time for batch erase is set so that the batch erase and verify operations are repeated multiple times, so the second batch erase operation is entered, and after the second batch erase, all memory cells are the same as the previous time. It is determined whether or not the threshold value is less than EV. The batch erase and verify operation are repeated until the threshold values of all the memory cells become EV or less.

  When the batch erase and verify operations are repeated in this way, the erase voltage (= positive voltage applied to the well region−negative voltage applied to the word line) is set to the number of times of batch erase, for example, as shown in FIG. Is increased stepwise each time it is repeated a plurality of times (in this example, twice), and when the maximum value of the set value is reached, the voltage applied to the well region is kept at the maximum value during subsequent batch erasure. At this time, as a method of increasing the erase voltage stepwise, if the negative voltage applied to the word line is lowered stepwise to raise the erase voltage stepwise instead of the voltage applied to the well region, In some cases, the voltage applied to the region is increased stepwise, and the negative voltage applied to the word line is decreased stepwise to increase the erase voltage stepwise.

  FIG. 6C shows a threshold distribution of memory cells in a state where the threshold values of all memory cells are equal to or less than EV. At the end of the batch erase operation, memory cells that have disappeared too much (over-erased cells), that is, memory cells whose thresholds have decreased too much, are generated due to variations in various dimensions and film thicknesses. Since this overerased cell has a large leakage current, it causes read failure and write failure. Therefore, weak writing is performed on the memory cell whose threshold value is lower than OEV. This weak write operation is as follows. It is determined for each memory cell in the block whether or not the threshold value is OEV or more (step S3). When the threshold value of the memory cell is lower than OEV, that is, if it has disappeared too much, weak writing is performed on the memory cell (step S4).

  Thus, after performing weak writing to the memory cell, the verify operation is performed again (step S3). Again, if the threshold value of the memory cell is lower than OEV, weak writing is performed again (step S4). Thus, verify and weak writing are repeated until the threshold value of the memory cell becomes equal to or higher than OEV. When the threshold value of the memory cell becomes equal to or higher than OEV, the process proceeds to the next memory cell.

  After weak writing is completed for all the memory cells in the block (step S5), it is confirmed whether the threshold values of all the memory cells exceed the voltage EV (step S6). If there is no cell exceeding the voltage EV, all the erase operations are finished here. If there is a cell whose threshold exceeds EV, the process returns to step S1 again, and the processes after the batch erase are performed again. FIG. 6D shows the threshold distribution of the memory cells in a state where the threshold values of all the memory cells are EV or less and OEV or more.

  As described above, according to the second embodiment, by increasing the erase voltage stepwise, a series of erase operations can be performed without performing a pre-erase write operation, and the data erase operation time is shortened. be able to. At this time, which of the first embodiment and the second embodiment is actually adopted, and the initial value of the erase voltage and the voltage value to be increased stepwise should be selected in accordance with the characteristics of the memory cell. Can do. In some cases, it is possible to make selection using an option ROM or the like in the product test process.

1 is a block diagram of a flash memory according to a first embodiment of the present invention. FIG. 2 is a plan view showing a layout of a memory cell array of a NOR flash memory as an example of the memory cell array in FIG. 1. FIG. 3 is an equivalent circuit diagram of a partial region in the memory cell array in FIG. 2. 3 is a flowchart showing a first embodiment of the erase operation of the flash memory of FIG. 1. FIG. 3 is a diagram showing two examples of changes in erase voltage during batch erase in the erase operation of the flash memory of FIG. 1. FIG. 4 is a diagram showing changes in threshold distribution of memory cells in the erase operation of the flash memory of FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Command user interface, 12 ... Central processing unit, 13 ... Read-only memory, 14 ... Input-output circuit, 15 ... Decoder, 16 ... Sense amplifier, 17 ... Memory cell array, 18 ... Write / erase circuit.

Claims (6)

A memory cell array in which at least one block including a plurality of memory cells is disposed;
A write / erase circuit that writes to a plurality of memory cells included in a selected block in the memory cell array and erases the plurality of memory cells included in the selected block in a batch;
A control circuit for controlling a write operation and an erase operation in the write / erase circuit,
The control circuit confirms whether there is no memory cell having a threshold higher than a first predetermined voltage for the plurality of memory cells;
When there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the selected block, the erase voltage erase voltage is set to the initial value every time batch erase is performed once or a plurality of times. Means for performing batch erasing in stages until reaching the maximum value, and checking whether there is a memory cell having a threshold value higher than the first predetermined voltage;
If there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the selected block after the erase voltage reaches the maximum value, batch erase is performed with the erase voltage remaining at the maximum value. And a means for confirming whether or not there is a memory cell having a threshold value higher than the first predetermined voltage. The control circuit includes:
A voltage lower than that during normal data writing is applied to each memory cell having a threshold value lower than a second predetermined voltage lower than the first predetermined voltage among the plurality of memory cells included in the selected block. Means for performing weak writing, and repeating the weak writing until a threshold value of the memory cell becomes equal to or higher than the second predetermined voltage;
It is confirmed whether or not there is a memory cell having a threshold higher than the first predetermined voltage with respect to the plurality of memory cells, and when there is a memory cell having a threshold higher than the first predetermined voltage, 2. The nonvolatile semiconductor memory device according to claim 1, further comprising means for returning to means for setting a threshold value of the memory cell to be equal to or lower than the first predetermined voltage. For a memory cell array in which at least one block including a plurality of memory cells is arranged, at least one block is selected, and data held in the plurality of memory cells included in the selected block is erased collectively. In the data erasing method of the nonvolatile semiconductor memory device,
A first step of performing batch erase by applying an erase voltage to a plurality of memory cells included in the selected block;
A second step of confirming whether or not there is a memory cell having a threshold value higher than a first predetermined voltage for the plurality of memory cells included in the selected block;
When there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the selected block, the erase voltage is changed at least once from the initial value to the maximum value to perform batch erase And a third step of confirming whether or not there is a memory cell having a threshold value higher than the first predetermined voltage;
If there is a memory cell having a threshold value higher than the first predetermined voltage among the plurality of memory cells included in the selected block after the erase voltage reaches the maximum value, batch erase is performed with the erase voltage remaining at the maximum value. And a fourth step of confirming whether or not there is a memory cell having a threshold higher than the first predetermined voltage. A method for erasing data in a nonvolatile semiconductor memory device.   4. The nonvolatile memory according to claim 3, wherein the third step performs batch erase by increasing the erase voltage stepwise from an initial value to a maximum value every time batch erase is performed once or a plurality of times. A method for erasing data in a semiconductor memory device. A voltage lower than that during normal data writing is applied to each memory cell having a threshold value lower than a second predetermined voltage lower than the first predetermined voltage among the plurality of memory cells included in the selected block. A fifth step of performing weak writing and repeating the weak writing until a threshold value of the memory cell becomes equal to or higher than the second predetermined voltage;
For a plurality of memory cells included in the selected block, it is confirmed whether or not there is a memory cell having a threshold higher than the first predetermined voltage, and a memory cell having a threshold higher than the first predetermined voltage exists. And a sixth step of returning to a third step of setting thresholds of a plurality of memory cells included in the selected block to be equal to or lower than the first predetermined voltage. Or a data erasing method of the nonvolatile semiconductor memory device according to 4;   The memory cell is composed of a field effect transistor having a control gate, a floating gate, a source, and a drain, and a positive voltage applied to a well region of the field effect transistor when performing the erase voltage in the batch erase stepwise. 6. The method according to claim 3, further comprising: stepwise increasing the maximum value of the set value and / or decreasing stepwise the negative voltage applied to the word line to the minimum value of the set value. A data erasing method of the nonvolatile semiconductor memory device according to claim.

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