TW200425162A - Circuits and methods for changing page length in a semiconductor memory device - Google Patents

Circuits and methods for changing page length in a semiconductor memory device Download PDF

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Publication number
TW200425162A
TW200425162A TW92131236A TW92131236A TW200425162A TW 200425162 A TW200425162 A TW 200425162A TW 92131236 A TW92131236 A TW 92131236A TW 92131236 A TW92131236 A TW 92131236A TW 200425162 A TW200425162 A TW 200425162A
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Taiwan
Prior art keywords
memory
control signal
address
block
memory device
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TW92131236A
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Chinese (zh)
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TWI233619B (en
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Yun-Sang Lee
One-Gyun La
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Samsung Electronics Co Ltd
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Priority claimed from KR10-2002-0072093A external-priority patent/KR100510496B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
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Publication of TWI233619B publication Critical patent/TWI233619B/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Abstract

A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

Description

200425162 玫、發明說明： 相關申請案之交互參考 本申請案係為聲稱對2002年11月1 9曰於韓國智筹、財產局 提出之韓國專利申請案第2〇〇2_72〇93號之優先權。 【發明所屬之技術領域】 本發明指向一種半導體記憶裝置，其架構讓使用者得以 改變半導體裝置分頁長度。此外，本發明尚指向用以改變 半導體裝置分頁長度之電路與方法，其中定址機制與控制 私路系統可啟動記憶單元陣列之記憶單元陣列區塊之一哎 夕條對應字元線（具相同列位址），藉以依律定操作模式改變 分頁長度。 【先前技術】 目丽半導體記憶裝置提供具廣泛應用之各類操作模式。 例如同步半導體記憶裝置（諸如SDRAM(同㈣態隨機存取 記憶體））可利用模式暫存器組（MRS)支援可變行位址頻閃 觀測潛伏（CL)與突波長度（BL)模式。這些半導體記憶裝 置係用於各種裝置與應用中，諸如電子設備、網路系統、 通訊系統、控制系統、多媒體應用集PC(個人電腦）之主記 憶體。 圖1A至1C闡釋依先前技藝之半導體記憶裝置之階層記 憶架構。如圖1A所示，半導體記憶裝置1〇〇包含複數個記憶 庫100A、1咖、⑽c、1QGD。各記憶庫均代表例如⑼中 之記憶體之邏輯單元，且各庫均可由—或多個記憶模組組 成（例如DIMM(雙線中記憶模組）、SIMM(單線中記憶模200425162 Description of the invention: Cross-reference to related applications This application claims to have priority over Korean Patent Application No. 2000-72〇93 filed with Korea Intellectual Property and Property Office on November 19, 2002. . [Technical field to which the invention belongs] The present invention is directed to a semiconductor memory device whose architecture allows a user to change the page length of a semiconductor device. In addition, the present invention is directed to a circuit and method for changing the paging length of a semiconductor device, in which the addressing mechanism and the memory cell array block that control the bootable memory cell array of the private circuit system are corresponding word lines (with the same column) Address) to change the page length in accordance with the operating mode. [Previous Technology] Moly Semiconductor memory devices provide various operating modes with wide applications. For example, synchronous semiconductor memory devices (such as SDRAM (homogeneous random access memory)) can use the mode register group (MRS) to support variable line address strobe observation latent (CL) and surge length (BL) modes. . These semiconductor memory devices are used in various devices and applications, such as the main memory of electronic equipment, network systems, communication systems, control systems, and multimedia application PCs (personal computers). 1A to 1C illustrate a hierarchical memory architecture of a semiconductor memory device according to the prior art. As shown in FIG. 1A, the semiconductor memory device 100 includes a plurality of memory banks 100A, 1c, 1c, 1QGD. Each memory bank represents, for example, a logical unit of memory in the memory, and each bank can be composed of—or multiple memory modules (such as DIMM (memory module in dual lines), SIMM (memory module in single line)

O:\89\89113.DOC 200425162 組））。各§己憶庫100A、ιοοΒ、l〇〇c、i〇〇D進一步邏輯分割 為複數個5己憶單元陣列區塊。例如：圖1B之示例性具體實 施例所示，記憶庫100A包括四記憶單元陣列區塊1〇〇a、 100b、100c、l〇〇d 〇 此外’各5己憶單元陣列區塊1 〇 〇 a、1 〇 Qb、1 Q 〇 c、1⑼d進 步途輯刀割為複數個次記憶单元陣列區塊，其中各次記 憶單元陣列區塊均受控於相關控制電路系統。例如··圖i C 之示例性具體實施例所示，記憶單元陣列區塊100a包括四 個-人3己fe單元陣列區塊11 〇、12 〇、1 3 〇、14 0。記憶單元陣 列區塊100a進一步包括複數個字元線驅動器m、m、 131、 141，其中各字元線驅動器均與次記憶單元陣列區塊 110、120、130、140之一以及複數個次解碼器112、122、 132、 142和一列解碼器150有關。 圖1A-C中所示記憶架構一般係於部分啟動之半導體記憶 裝置中施行，例如快速循環動態隨機存取記憶體 (FCRAM) ’藉以利用例如行區塊位址（CBAs)啟動次記憶單 元陣列區塊110、120、130、140之一，俾施行資料存取或 更新操作。 由範例可知，為施行記憶體存取操作，響應於預定庫位 址，初始選擇記憶庫110A、1〇〇B、1〇〇c、i〇〇d之一，接著 響應於預定位址（例如列位址），於所選之記憶庫内選擇一記 憶單元陣列區塊l〇〇a、100b、1〇〇c、1〇〇d。接著響應於例 如一行區塊位址（CBA)，選擇一次記憶單元陣列區塊（在所 選之記憶單兀陣列區塊中）。例如在圖丨c之示例性具體實施O: \ 89 \ 89113.DOC 200425162 group)). Each §memory library 100A, ιοοΒ, 100c, and 100D is further logically divided into a plurality of 5memory cell array blocks. For example, as shown in the exemplary embodiment of FIG. 1B, the memory bank 100A includes four memory cell array blocks 100a, 100b, 100c, and 100d. In addition, each of the five memory cell array blocks 1 is provided. a, 1 〇Qb, 1 Q 〇c, 1⑼d progressive path cutting is divided into a plurality of secondary memory cell array blocks, wherein each secondary memory cell array block is controlled by the relevant control circuit system. For example, as shown in the exemplary embodiment of FIG. IC, the memory cell array block 100a includes four-human 3 and fe cell array blocks 11 0, 12 0, 1 30, and 14 0. The memory cell array block 100a further includes a plurality of word line drivers m, m, 131, 141, where each word line driver is connected to one of the secondary memory cell array blocks 110, 120, 130, 140 and a plurality of times of decoding The decoders 112, 122, 132, 142 are related to a list of decoders 150. The memory architecture shown in Figs. 1A-C is generally implemented in a partially activated semiconductor memory device, such as a fast-cycle dynamic random access memory (FCRAM) 'to enable the use of, for example, row block addresses (CBAs) to activate a secondary memory cell array One of the blocks 110, 120, 130, and 140 performs data access or update operations. As can be seen from the example, in order to perform a memory access operation, in response to a predetermined bank address, one of the banks 110A, 100B, 100c, and 100d is initially selected, and then responded to the predetermined address (for example, Column address), select a memory cell array block 100a, 100b, 100c, 100d in the selected memory bank. Then, in response to, for example, a row block address (CBA), a memory cell array block is selected once (in the selected memory cell array block). For example, the example implementation in Figure

O:\89\89113.DOC 200425162 例中由於σ己丨思單元陣列區塊1 00a包括四個次記憶區塊 110 120 I30、14〇，故利用兩行區塊位址（CBAS)選擇次 記憶區塊之一。 更特別吕之，在寫入或讀取操作期間（記憶體存取），將 一列位址ΚΑΐ(1==2,3，···，η)輸入列解碼器150並解碼之。接 著，根據解碼結|，列解碼器15〇將啟動對應於輸入列位址 RAi之複數個正規字元線致動信號（nwe)之一。響應於另一 列位址RAi(i = 〇，l)與CBA，此解碼器112、122、132、⑷之 -將產生具預定提昇位準之字元線電源信號，並輸出字元 線電源信號至字元線驅動器m、121、131、141中相對應 者。響應於字線電源信?虎與字元線致動信號NEw，字元 線經一預疋切換電路（未圖示）啟動字元線WL —〇、、 WL_2 WL-3中對應者。只要字元線一啟動所選之次記憶 單兀陣列區塊，即輸入行位置並將之解碼，以讀取或寫入 資料於所選之次記憶區塊。 在具有如圖1A_1C所示記憶架構之DRAM中，由於在任何 …疋時間下，僅可啟動次記憶單元陣列區塊11 〇、1、1 、 140之一，故半導體裝置之分頁長度固定。如此技藝中已知 者刀頁係牦可自一列位址存取之位元數，且行位置數 可决疋刀頁大小。例如：在圖lc之記憶單元陣列區塊1〇如 中’假以卜部輸入位址總數為η，則用以選擇各次記憶單元 陣列區塊之行選擇線（咖）之行位址總數為卜2。此係因利 用兩行位址選擇四個次記憶單元陣列區塊购、祕、 100c lGGd之-所致。故對應於—所選次記憶單元陣列區O: \ 89 \ 89113.DOC 200425162 In the example, since the σself-thinking cell array block 1 00a includes four secondary memory blocks 110 120 I30, 1440, two rows of block addresses (CBAS) are used to select the secondary memory. One of the blocks. More specifically, during a write or read operation (memory access), a column of addresses ΚΑΐ (1 == 2, 3, ..., η) is input to the column decoder 150 and decoded. Next, according to the decoding result, the column decoder 15 will activate one of a plurality of regular word line activation signals (nwe) corresponding to the input column address RAi. In response to another column address RAi (i = 0, l) and CBA, this decoder 112, 122, 132, and ⑷-will generate a word line power signal with a predetermined boost level, and output a word line power signal To the corresponding one of the word line drivers m, 121, 131, and 141. In response to the word line power supply signal tiger and the character line actuation signal NEW, the character line activates the corresponding one of the word lines WL — 0, WL_2, WL-3 via a pre-switching circuit (not shown). As soon as the word line activates the selected secondary memory array block, the row position is input and decoded to read or write data to the selected secondary memory block. In a DRAM having a memory structure as shown in FIGS. 1A_1C, since only one of the secondary memory cell array blocks 11 0, 1, 1, and 140 can be activated at any time, the page length of the semiconductor device is fixed. Known in this art is the number of bits that can be accessed from a row of addresses, and the number of row positions determines the size of the blade. For example, in the memory cell array block 10 in FIG. 1c, if the total number of input addresses of the memory cell array is η, the total number of the row address of the row selection line (coffee) used to select each memory cell array block is Bu 2. This is due to the use of two rows of addresses to select four secondary memory cell array block purchases, secrets, 100c lGGd-. Corresponds to-selected secondary memory cell array area

O:\89\89U3.DOC 200425162 塊之一啟動字元線之分 1 C所示架構而提供2^2 置與具有例如2n* 2nM SDRAM)不相容。 頁長度固定為广2。因此，具有如圖 固定分頁長度之習知半導體記憶裝 分頁長度之半導體記憶裝置（例如 爰此，具有可針對给 之架構之半 &、、、口疋應用而調整分頁長度 導體記憶裝置之高度優點。 、又 【發明内容】 不货明才日向一種丰導_ ^r卜立壯班 , 牛導體Zk裝置，其架構讓使用者 改變半導體裝置分頁長度…卜，本發明尚指向用以改變 半導體裝置分頁長度之電路與方法1中定址機制與控制 電路糸統可啟動記憶單元陣狀記憶單元陣列區塊之一或 多條對應字元線（具相同列位址），藉以依律定操作模式改變 分頁長度。 俊占在於藉由刀頁長度之得以改變’本發明適於在具有 不同分寅長度之半導體裝置間運作。 -種依本發明之半導體裝置包括_被邏輯分割為複數個 記憶區塊之記憶單元陣列’丨中各記憶區塊均為—對應區 塊位址所定址；複數個字元線控制電路，#中各字元線控 制：：均與該等記憶區塊之一有關’以啟動相關記憶區塊 子元線’ &帛a選擇控制該等字元線控帝』電路之控 制電路’俾啟動具相同列位址之一或多條對應字元線，以 改變一該半導體記憶裝置之分頁長度。 較佳為該控制電路接收一行區塊位址（例如一行區塊位 置）與一第一控制信號為輸入，並接著產生一第二控制信號O: \ 89 \ 89U3.DOC 200425162 One of the start word lines is divided into 1 2C architecture and 2 ^ 2 is not compatible with having 2n * 2nM SDRAM). The page length is fixed to wide 2. Therefore, a semiconductor memory device having a conventional semiconductor memory with a fixed page length as shown in the figure (for example, a semiconductor memory device with a page length that can be adjusted for the application of the half & ,,, and other applications). Advantages. [Summary of the invention] It is not available until tomorrow. It is a kind of rich guide. ^ R Bu Li Zhuang class, cattle conductor Zk device, its structure allows users to change the length of the semiconductor device paging ... Bu, the present invention is also directed to change the semiconductor device paging The circuit and method of the length of the addressing mechanism and control circuit 1 can start one or more corresponding word lines (with the same column address) of the memory cell array memory cell array block, so as to change the paging according to the regular operation mode The length is based on the fact that the length of the blade can be changed. The present invention is suitable for operating between semiconductor devices with different lengths.-A type of semiconductor device according to the present invention includes:-It is logically divided into a plurality of memory blocks. Each memory block in the memory cell array is the address of the corresponding block address; a plurality of word line control circuits, # 中Control of each character line: It is related to one of these memory blocks' to start the relevant memory block sub-element line '& 帛 a choose to control these character line control emperor's control circuit' 俾 starter One or more corresponding word lines of the same column address to change the page length of a semiconductor memory device. Preferably, the control circuit receives a row of block addresses (such as a row of block positions) and a first control signal. As input and then generates a second control signal

O:\89\89113.DOC -9- 200425162 以選擇啟動一或多個念- 中，塑靡於二t 凡線控制電路。在-具體實施例 曰心於預定指令與外部位址，利用；^ #在％ 產生第-控制信號。在其它呈體，=式暫存，態 入碎 、匕具驵戶、轭例中，藉由線接合、 接合或炫絲切割造成之控制信號產生器程式化而固定 第一控制信號。 U疋 在本發明之另^一呈妒者a a丨山 。 八體只轭例中，記憶系統包括具有 輯分割為複數個記憶區塊之記憶單元陣列之第__記_裝 其中各記憶區塊均為一對應區塊位址所定址；複數個 I兀線控制電路，其中各字元線控制電路均與該等記憶區 塊之一有關，以啟動相關記憶區塊之—字元線，·及—用以 選擇控制該等字元線控制電路之控制電路，俾啟動具相同 =位址之-或多條對應字元線，以改變—該 置之分頁長度。 我 在本發明之另-具體實施例中，提供一種用以改變一具 有被邏輯分割為複數個記憶區塊之記鮮 記憶裝置之分頁長度之方，、“甘… 干』之牛導體 /八中各兄憶區塊係由一對應 區塊位址所定址。兮古、、土 — ^ 疋止$方法包括產生一律定複數個分頁長产 操作模式之第—控制信號，·以及根據該第-控制信號及Γ 區塊位址產生一第二控制信號。響應於該 選擇啟動具-相同列位址之該等記憶區塊中之：二 元線以提供一對肩於兮強· +八I e —, 、 ΐ應於式律疋分頁長度操作模式之該半導體 記憶裝置之分頁長度。 即將描述本發明之這些及其它具體實施例、態樣、特徵 及優點’參閱隨附圖式即可瞭解下列較佳具體實施例之詳O: \ 89 \ 89113.DOC -9- 200425162 Choose to activate one or more concepts, which will be used to control the two t-line control circuits. In the specific embodiment, focusing on the predetermined instruction and the external address, use; ^ # 在 ％ Generates the-control signal. In other forms, == temporary storage, state breaks, dagger users, and yoke examples, the first control signal is fixed by programming the control signal generator caused by wire bonding, bonding, or wire cutting. U 疋 is another jealous man in the present invention. In the example of the eight-body yoke, the memory system includes a memory cell array having a memory cell array divided into a plurality of memory blocks. Each memory block is addressed by a corresponding block address; Line control circuit, in which each word line control circuit is related to one of these memory blocks to activate the word line of the relevant memory block, and-to control the control of these word line control circuits Circuits, start with-or multiple corresponding word lines with the same = address to change-the page length of the set. In another embodiment of the present invention, I provide a method for changing the page length of a memory device that is logically divided into a plurality of memory blocks. The various blocks in China are addressed by a corresponding block address. The ancient method of ^ 产生 定 分 $ method includes generating the first-control signal of a plurality of paged long-production operation modes, and according to the first -The control signal and the Γ block address generate a second control signal. In response to the selection, the start-up device-in the memory blocks of the same column address: a binary line is provided to provide a pair of shoulders. I e —, ,, and the paging length of the semiconductor memory device in a paging length operation mode. These and other specific embodiments, aspects, features, and advantages of the present invention will be described shortly. Learn more about the following preferred embodiments

O:\89\89ll3 DOC 200425162 細敛述。 【實施方式】 本發明指向一種半導俨 °己憶衣置，其架構讓使用者得以 改受半導體裝置分頁 — 、又更特別言之，依本發明之較佳 具體實施例之電路盥方法 〃 /ir係根據得以選擇啟動記憶單元 區塊之次記憶單元區塊 或多條對應字元線（具相同列 位址）’以依律定操作桓+ 乂 乍棋式改史半導體記憶裝置分頁長度。 圖2係依本發明之一呈體奋 σσ ^ 一篮灵&例之記憶早元陣列架構之 高階簡圖，其可改變半導體ν 一 卞守體°己氐裝置分頁長度。可將圖2之 示例性具體實施例损為[g| ] r - 』祝馬圖lc所不記憶架構之延伸，其中控 制與疋址機制致使分頁長度得以改變（與具固定分頁長度 之圖1C架構相反）。參閱圖2,半導體記憶裝置包括具有被 邏輯分割為複數個次記憶單元陣列區塊11〇、i2〇、13〇、 M0(或”次記憶區塊”）之記憶陣列之記憶單元陣列區塊 200(或"記憶區塊”），其中各次記憶區塊均為一對應區塊位 址（例如CBA(行區塊位址））所定址。在示例性具體實施例 中，所示4個次記憶區塊（區塊〇、1、2與3)係供闡釋之用， 但已知記憶區塊2〇〇可包括較多或較少次記憶區塊。 記憶區塊200進一步包括複數個字元線驅動器m、121、 131、141，其中各字元線驅動器1U、12i、Hi、M1均與 複數個次記憶區塊110、120、130、140之一以及複數個次 解碼器212、222、232、242有關，其中各次解碼器212、222、 232、242均與字元線驅動器111、12卜131、141之一有關。 各對應之次解碼器/字元線驅動器對均具一用以啟動一相 O:\89\89113 DOC -11 - 200425162 關次記憶區塊之一字元線之字元線控制電路。 概言之，控制電路250選擇控制字元線控制電路，以選擇 啟動列位址與列解碼器150解碼之列位址相同之次記憶區 塊110 120、130、140之一或多條對應字元線WL—〇、WLJ、 WL—2、WL—3，藉以改變半導體記憶裝置之分頁長度。更 特別言之，列解碼器15〇接收並解碼一第二輸入列位址 RAi(其中1==2,3, ···，!!），並根據解碼結果，啟動一對應於該輸 入歹j位置之正規予元線致動信號（nwe)。控制電路接收 行區塊位址（CBA)與一控制信號為輸入，並因之響應輸出 對應之控制信號至次解碼器212、222、232、242。次解碼 态212、222、232、242接收來自控制電路25〇之控制信號與 第列位aRAl(其中i=〇與1)，並接著產生輸出至字元線 驅動器111、121、131、141之控制信號。 根據來自次解瑪器212、222、232、242之控制信號以及 來自列解碼器15〇之NWE信號，字元線驅動器⑴、121、 13卜141將選擇啓動具相同列位址之次記憶區塊h〇、丨2〇、 〇 14〇之一或多條對應字元線WL—0、WL— 1、WL—2、 WL—3 ’以改變半導體記憶裝置之分頁長度。例如在圖：之 不例性具體實施例中，假設各次記憶區塊之行位址數為 η 2，接著⑴可啟動次記憶區塊之一之字元線以獲得广2分 頁長度，（11)可啟動兩個次記憶區塊之對應字元線以獲得 2η 1分頁長度；（iii)可啟動所有四個次記憶區塊之對應字元 線以獲得2n分頁長度。 欠在圖2之不例性具體實施例中，可根據控制信號以及至O: \ 89 \ 89ll3 DOC 200425162 Concise description. [Embodiment] The present invention is directed to a semi-conducting device, the structure of which allows users to change the paging of semiconductor devices—and, more particularly, a circuit washing method according to a preferred embodiment of the present invention. / ir is based on the secondary memory cell block or multiple corresponding character lines (with the same column address) that can be selected to activate the memory cell block. . FIG. 2 is a high-level schematic diagram of a memory early element array architecture according to one embodiment of the present invention, which can change the page length of a semiconductor device. The exemplary embodiment of FIG. 2 can be reduced to [g |] r-”An extension of the memory structure not wished by Matuma lc, where the control and addressing mechanism causes the page length to be changed (as shown in Figure 1C with a fixed page length) The architecture is the opposite). Referring to FIG. 2, a semiconductor memory device includes a memory cell array block 200 having a memory array logically divided into a plurality of secondary memory cell array blocks 1110, i20, 1330, M0 (or "secondary memory block"). (Or " memory block "), where each memory block is addressed by a corresponding block address (such as a CBA (line block address)). In the exemplary embodiment, four are shown The secondary memory blocks (blocks 0, 1, 2 and 3) are for explanation, but it is known that the memory block 2000 may include more or less secondary memory blocks. The memory block 200 further includes a plurality of memory blocks. Word line drivers m, 121, 131, 141, wherein each word line driver 1U, 12i, Hi, M1 is associated with one of a plurality of secondary memory blocks 110, 120, 130, 140 and a plurality of secondary decoders 212, 222, 232, and 242, and each of the secondary decoders 212, 222, 232, and 242 is related to one of the character line drivers 111, 12 and 131, 141. Each corresponding secondary decoder / character line driver pair has A character used to start a phase O: \ 89 \ 89113 DOC -11-200425162 A character of a character line in the off-time memory block Control circuit. In summary, the control circuit 250 selects the control word line control circuit to select one or more of the secondary memory blocks 110 120, 130, and 140 having the same column address as the column address decoded by the column decoder 150. Corresponding word lines WL-0, WLJ, WL-2, WL-3, thereby changing the page length of the semiconductor memory device. More specifically, the column decoder 15 receives and decodes a second input column address RAi ( Where 1 == 2,3, ···, !!), and according to the decoding result, start a normal pre-element activation signal (nwe) corresponding to the position of the input 歹 j. The control circuit receives the row block address (CBA) is input with a control signal, and accordingly the corresponding control signal is output to the secondary decoders 212, 222, 232, and 242. The secondary decoding state 212, 222, 232, and 242 receives the control signal from the control circuit 25 And the first column aRAl (where i = 0 and 1), and then generate control signals output to the word line drivers 111, 121, 131, 141. According to the control signals from the secondary resolvers 212, 222, 232, 242 And the NWE signal from the column decoder 15, the word line driver ⑴, 121 13 141 141 will choose to activate one or more corresponding word lines WL-0, WL-1, WL-2, WL-3 with the next memory block with the same column address. 'To change the page length of the semiconductor memory device. For example, in the example of the specific embodiment shown in the figure, it is assumed that the number of row addresses of each memory block is η 2, and then the word of one of the memory blocks can be activated. Meta-lines to obtain a wide 2 page length, (11) the corresponding character lines of two secondary memory blocks can be activated to obtain a 2η 1 page length; (iii) the corresponding character lines of all four secondary memory blocks can be activated Get 2n page length. Owing to the exemplary embodiment shown in FIG. 2, according to the control signal and to

O:\89\89113.DOC -12· 控制電路250之CBA輸入之如人 , _ 之、、且3，以控制電路250選擇驅動 一或多個字元線驅動器丨丨 i2i l31、141。故可調整具 體記 目同歹彳位址之啟動字开綠者 # 、’泉數，猎以如所期般改變半導 憶裝置分頁長度。 帝圖3係依本發明之—具體實施例之記憶單元陣列區塊之 :路圖’其可㈣根據律定操作模式改變半導體記憶裝置 分頁長度。圖3之電路圖闡釋圖2之—般架構之—特別施 仃。例如圖3閣释圖2之控制電路25〇之一具體實施例。此 卜在圖3中，利用MRS(模式暫存器組）產生輸人至控制電 之控制L號，其中可由使用者設定與控制自MRS輪出之 控制信號’以如所期般改變分頁長度。 更特別言之，參閱圖3 ,半導體記憶裝置之記憶區塊3〇〇 包括邏輯分割為複數個次記憶體區塊110、12〇、13〇、14〇 之記憶陣列，其中可利用區塊位址CBA0、CBA1將次記憶 區塊定址。在示例性具體實施例中，所示4個次記憶區塊（區 塊〇 1、2與3)係供闡釋之用，但已知記憶區塊3〇〇可具較 多或較少次記憶區塊。 冗憶區塊300進一步包括複數個字元線驅動器m、ι21、 131 141 ’其中各子元線驅動器ui、121、131、141均與 複數個次記憶區塊11〇、12〇、130、140之一以及複數個次 解碼器312、322、332、342有關，其中各次解碼器312、322、 3 3 2、342均與字元線驅動器111121、1 3 1、141之一有關。 各對應之次解碼器/字元線驅動器對均具一字元線控制電 路，俾根據自控制電路360輸出之控制信號啟動一相關次記 O:\89\89U3.DOC -13- 200425162 憶區塊之一字元線。 概言之，控制電路360選擇控制字元線控制電路，以 啟動列位址與列解碼器15()解碼 < 列位址相同之次記憶區 鬼10 120 13〇、14〇之一或多條對應字元 WL—2、WL」，藉以改變半導體記憶裝置之分頁長度。更 特別a之，列解碼器15()接收並解碼一第二輪入列位址 W其中1=2,3，···，η)’並根據解碼結果’啟動一對應於該輸 入列位置之正規字元線致動信號（NWE)。控制電路36〇接收 行區塊位址CBA0與CBA丨以及由控制信號產生器35〇產生 之控制信號PL0B與PL1B為輸入，並接著根據輸入區塊位址 與控制信號輸出控制信號至次解碼器312、322、332、342。 -人解碼器312、322、332、342接收來自控制電路36〇之控制 信號與一第一列位址RAi(其中i=〇與1)，並接著產生輸出至 字元線驅動器111、121、131、141之控制信號。 根據來自次解碼器312、322、332、342之控制信號以及 來自列解碼器150之NWE信號，字元線驅動器ill、121、 131、141將選擇啓動具相同列位址之次記憶區塊11〇、12〇、 130、140之一或多條對應字元線WL—0、WL—1、WL—2、 WL—3，以改變半導體記憶裝置之分頁長度。 控制信號產生器350包括一指令缓衝器351、一位址缓衝 器352及一模式暫存器組（MRS) 353。一記憶體控制器（或例 如CPU)傳遞一預定指令信號及位址信號至控制信號產生器 350。指令緩衝器351接收預定指令信號，位址緩衝器352自 記憶體控制器接收外部位址信號。MRS 353自指令緩衝器 O:\89\89113.DOC -14- 200425162 3 51與位址緩衝器352接收指令與位址信號，接著根據輸入 指令與位址信號輸出控制信號PL0B與PL1B。O: \ 89 \ 89113.DOC -12 · The CBA input of the control circuit 250 is as human, _, and 3, and the control circuit 250 selects to drive one or more word line drivers i2i l31, 141. Therefore, you can adjust the number of starting words #, ‘spring’ of the start word of the specific record address, and change the page length of the memory device as expected. Figure 3 is a road map of a memory cell array block according to a specific embodiment of the present invention, which can change the page length of a semiconductor memory device according to a law operation mode. The circuit diagram of FIG. 3 illustrates the general structure of FIG. 2-a special implementation. For example, FIG. 3 illustrates a specific embodiment of the control circuit 25 of FIG. 2. In Fig. 3, the MRS (Mode Register Group) is used to generate the control L number for input to the control circuit. The user can set and control the control signal from the MRS wheel to change the page length as expected . More specifically, referring to FIG. 3, the memory block 300 of the semiconductor memory device includes a memory array logically divided into a plurality of secondary memory blocks 110, 120, 13 and 14 in which a block bit can be utilized. The addresses CBA0 and CBA1 address the secondary memory block. In the exemplary embodiment, the four secondary memory blocks (blocks 0, 2, and 3) are shown for explanation, but it is known that the memory block 300 can have more or less secondary memories. Block. The remembrance block 300 further includes a plurality of word line drivers m, ι21, 131 141 ', where each of the sub-line driver ui, 121, 131, 141 and a plurality of secondary memory blocks 11, 12, 10, 130, 140 One of the sub-decoders 312, 322, 332, and 342 is related, and each of the sub-decoders 312, 322, 3 3, and 342 is related to one of the word line drivers 111121, 1 3, and 141. Each corresponding decoder / character line driver pair has a character line control circuit, and a related record is started according to the control signal output from the control circuit 360. O: \ 89 \ 89U3.DOC -13- 200425162 Memories Block one character line. In summary, the control circuit 360 selects the control word line control circuit to enable the column address to be the same as the column decoder 15 () decoding < one or more of the secondary memory area ghost 10 120 13 30, 14 14 The bar corresponds to the characters WL-2, WL ", thereby changing the page length of the semiconductor memory device. More specifically, the column decoder 15 () receives and decodes a second round of column address W (where 1 = 2, 3, ..., η) 'and starts a position corresponding to the input column according to the decoding result. Normal word line activation signal (NWE). The control circuit 36 receives as input the row block addresses CBA0 and CBA 丨 and the control signals PL0B and PL1B generated by the control signal generator 35o, and then outputs a control signal to the secondary decoder according to the input block address and the control signal. 312, 322, 332, 342. -The human decoders 312, 322, 332, 342 receive the control signals from the control circuit 36 and a first column address RAi (where i = 0 and 1), and then generate outputs to the word line drivers 111, 121, 131, 141 control signals. According to the control signals from the secondary decoders 312, 322, 332, 342 and the NWE signal from the column decoder 150, the word line drivers ill, 121, 131, 141 will select to activate the secondary memory block with the same column address 11 One or more corresponding word lines WL-0, WL-1, WL-1, WL-2, and WL-3 of 〇, 120, 130, 140 to change the page length of the semiconductor memory device. The control signal generator 350 includes an instruction buffer 351, a bit address buffer 352, and a mode register group (MRS) 353. A memory controller (or, for example, a CPU) transmits a predetermined instruction signal and an address signal to the control signal generator 350. The instruction buffer 351 receives a predetermined instruction signal, and the address buffer 352 receives an external address signal from the memory controller. MRS 353 self-instruction buffer O: \ 89 \ 89113.DOC -14- 200425162 3 51 and address buffer 352 receive the instruction and address signal, and then output control signals PL0B and PL1B according to the input instruction and address signal.

控制電路360較佳包括複數個反相器361、362、365、366 及複數個NAND電路3 63、3 64、3 67、3 68。反相器361接收 一行區塊位址補數為輸入，反相器3 6 2接收一行區塊位址 CBA0為輸入。NAND電路363接收反相器361之輸出信號及 控制信號PL0B與PL1B為輸入。NAND電路364接收反相器 362之一輸出信號及控制信號PL0B與PL1B為輸入。反相器 365接收一行區塊位址補數CBA1B為輸入，反相器366接收 一行區塊位址CBA1為輸入。NAND電路367接收反相器365 之一輸出信號及控制信號PL1B為輸入。NAND電路368接收 反相器366之一輸出信號及控制信號PL1B為輸入。The control circuit 360 preferably includes a plurality of inverters 361, 362, 365, 366 and a plurality of NAND circuits 3 63, 3 64, 3 67, and 68. Inverter 361 receives a row of block address complements as input, and inverter 3 6 2 receives a row of block address CBA0 as input. The NAND circuit 363 receives the output signals of the inverter 361 and the control signals PL0B and PL1B as inputs. The NAND circuit 364 receives as input an output signal from one of the inverters 362 and control signals PL0B and PL1B. The inverter 365 receives a row of block address complements CBA1B as an input, and the inverter 366 receives a row of block address CBA1 as an input. The NAND circuit 367 receives an output signal of an inverter 365 and a control signal PL1B as inputs. The NAND circuit 368 receives as input an output signal from one of the inverters 366 and a control signal PL1B.

記憶區塊300進一步包括一預解碼器375、複數個行解碼 器371、372、3 73、374及複數個邏輯電路381、382、383、 3 84、39i、392、393、394、395、3 96、397、3 98，以下將 闡釋其功能。除供行區塊位址用之位址外，預解碼器375接 收並預解碼一行位址。例如在圖3之示例性具體實施例中， 假設位址總數為η，則因兩位址係供CB A使用，故輸入n-2 個行位址於預解碼器375。 邏輯電路392接收行區塊位址CBA0B與CBA1B為輸入。邏 輯電路394接收行區塊位址CBA0與CBA1B為輸入。邏輯電 路3 96接收行區塊位址〇3八03與€3八1為輸入。邏輯電路398 接收行區塊位址CBA0與CBA1為輸入。邏輯電路392、394、 396與398分別為反相器391、393、395與397反相。 O:\89\89113.DOC -15 - 200425162 邏輯電路38 1接收反相器391之—輸 例^ 15唬與預解碼器 375之一輸出信號為輸入，並輸出—信號至與第—次記憶體 區塊1 ίο有關之行解碼器371。邏輯電路382接收反相器: ^ 一輸出信號與預解碼器375之—輸出信號為輸人，並輸出 一信號至與第二次記憶體區塊12〇有關之行解瑪器372。邏 ^電路383接收反相器395之一輸出信號與預解碼器奶之 -輸出信號為輸入，並輸出一信號至與第三次記憶體區塊 130有關之行解碼器373。邏輯電路384接收反相器％7之一 輸出信號與預解碼器375之—輸出信號為輸人，並輸出一信 號至與第四個次記憶體區塊140有關之行解碼器374。 在上述圖3之示例性具體實施例中，利用在控制信號產生 : 350中之MRS 353產生之控制信號之改變，以如所期般調 整分頁長度。MRS 353將控制電路360處理過之控制信 出’俾如控制信號產生器350自記憶體控制器或例如接 收之外σ卩‘令與位址之律定，施行一操作模式。 藉由範例可知，圖4A_4C闡釋各種操作模式，其中圖3之 半導體記憶裝置分頁長度可根據控制信號PL0B與PL1B而 變。特別言之，圖4A係用以闡釋一操作模式之表，其中兩 控制信號PL0B與PL1B均被關閉/切斷（例如邏輯位準高），俾 獲得分頁長度，其中視所示行區塊位址CBA0與CBA1之 L輯位準，僅啟動次記憶體區塊之一。此外，圖係用以 闡釋一操作模式之表，其中僅啟動/開啟控制信號PL0B(例 如邏輯位準低），俾獲得2n-l分頁長度，其中當行區塊位址 CBA1之邏輯位準低時，啟動兩個次記憶體區塊〇與1，或者The memory block 300 further includes a pre-decoder 375, a plurality of row decoders 371, 372, 3 73, 374, and a plurality of logic circuits 381, 382, 383, 3 84, 39i, 392, 393, 394, 395, 3 96, 397, 3 98, whose functions will be explained below. In addition to the address for the row block address, the pre-decoder 375 receives and pre-decodes a row of addresses. For example, in the exemplary embodiment of FIG. 3, assuming that the total number of addresses is n, since two bits are used by CB A, n-2 row addresses are input to the pre-decoder 375. The logic circuit 392 receives the row block addresses CBA0B and CBA1B as inputs. The logic circuit 394 receives the row block addresses CBA0 and CBA1B as inputs. Logic circuit 3 96 receives the row block addresses of 038 and 381 as inputs. The logic circuit 398 receives the row block addresses CBA0 and CBA1 as inputs. Logic circuits 392, 394, 396, and 398 are inverters 391, 393, 395, and 397, respectively. O: \ 89 \ 89113.DOC -15-200425162 Logic circuit 38 1Receive the inverter 391-input example ^ 15 and one of the pre-decoder 375 output signal as input, and output-signal to and first-time memory The block 1 is related to the decoder 371. The logic circuit 382 receives the inverter: ^ one of the output signal and the pre-decoder 375-the output signal is input, and outputs a signal to the decoder 372 related to the second memory block 120. The logic circuit 383 receives an output signal of one of the inverters 395 and a pre-decoder-output signal as inputs, and outputs a signal to the decoder 373 related to the third memory block 130. The logic circuit 384 receives one of the inverter% 7 output signal and the pre-decoder 375-the output signal is input, and outputs a signal to the row decoder 374 related to the fourth memory block 140. In the above-mentioned exemplary embodiment of FIG. 3, the change of the control signal generated by the MRS 353 in the control signal generation: 350 is used to adjust the page length as expected. The MRS 353 executes the control signal processed by the control circuit 360 ', such as the control signal generator 350 from the memory controller or, for example, outside the receiving σ 卩' order and address law, and implements an operation mode. As can be seen from the examples, FIGS. 4A-4C illustrate various operation modes, in which the page length of the semiconductor memory device of FIG. 3 can be changed according to the control signals PL0B and PL1B. In particular, FIG. 4A is a table for explaining an operation mode, in which two control signals PL0B and PL1B are turned off / cut off (for example, the logic level is high), and the page length is obtained. The L-levels of addresses CBA0 and CBA1 enable only one of the secondary memory blocks. In addition, the diagram is a table used to explain an operation mode, in which only the control signal PL0B is enabled / disabled (for example, the logic level is low), and a page length of 2n-1 is obtained, in which the logic level of the row block address CBA1 is low , Start two secondary memory blocks 0 and 1, or

O:\89\89113.DOC •16- 200425162 田行區塊位址CB A1之邏輯位準高時，啟動兩個次記憶體區 鬼2與3(在此模式下，與CBA〇無涉）。此外，圖化係用以闡 釋一操作模式之表，其中僅啟動/開啟控制信號PL1B(例如 邏輯位準低），俾獲得2n分頁長度，其中所有的次記憶體區 塊（〇、1、2與3)均啟動，與行區塊位址CB0A及CBA1之邏輯 位準無涉。 即將參閱圖3與圖4A、4B及4C之示例性具體實施例，進 一步詳述依本發明之半導體記憶裝置之各操作模式。參閱 圖3，控制信號產生器35〇接收一外部指令與位址，並利用 MRS 3 53響應於指令與位址產生預定控制信號孔⑽與 PL1B。控制電路36〇接收行區塊位址CBA〇與cBAl#及控制 化號PL0B與PL 1B，接著輸出控制信號至次解碼器3丨2、 322、332、342。次解碼器312、322、332、342根據來自控 制黾路360之控制#號以及一第一列位址(其中卜〇、1)， 選擇啟秦對應之字元線驅動器ill、m、。當自 列解碼器150產生正規字元線致動信號NWE時，啟動之次解 馬°°輸出子元線電源信號（PXI)至一對應之字元線驅動 器，俾啟動所選次記憶區塊之一對應字元線WL 〇、WL i、 —— 一2 WL—3。換吕之，字元線驅動器u ；[、12 1、13 1、141 曰應於自列解碼器35〇產生之正規字元線致動信號驟五，將 對應之次解碼器312、322、332、342之輸出信號切換至一 被啟動之字元線，藉以啟動相關次記憶區塊之一字元線。 以下將參閱圖5與6進一步詳述依本發明之次解碼器與字元 線驅動器之示例性具體實施例，例如可於圖3之裝置中施行O: \ 89 \ 89113.DOC • 16- 200425162 When the logical level of the Tianxing block address CB A1 is high, two secondary memory areas Ghosts 2 and 3 are activated (in this mode, it has nothing to do with CBA〇) . In addition, the diagram is used to explain a table of operating modes, in which only the control signal PL1B is activated / enabled (for example, the logic level is low), and 2n page length is obtained, in which all secondary memory blocks (0, 1, 2 And 3) are both activated, and have no relation to the logical levels of the row block addresses CB0A and CBA1. 3 and 4A, 4B, and 4C, which will be described in detail, each operation mode of the semiconductor memory device according to the present invention will be further detailed. Referring to FIG. 3, the control signal generator 35 receives an external instruction and address, and uses MRS 3 53 to generate a predetermined control signal hole ⑽ and PL1B in response to the instruction and address. The control circuit 36 receives the row block addresses CBA0 and cBAl # and the control numbers PL0B and PL 1B, and then outputs control signals to the secondary decoders 3, 2, 322, 332, and 342. The secondary decoders 312, 322, 332, and 342 select the character line driver ill, m, corresponding to Qiqin based on the control # number from the control loop 360 and a first column address (where 〇, 1). When the in-line decoder 150 generates a normal word line activation signal NWE, the second time the horsepower is activated, the sub-line power signal (PXI) is output to a corresponding word line driver, and the selected memory block is started. One corresponds to the character line WL 0, WL i, —— 2 WL-3. In other words, the character line driver u; [, 12 1, 13, 1, 141, said that the normal character line actuation signal that should be generated by the inline decoder 35o is five, which will correspond to the secondary decoder 312, 322, The output signals of 332 and 342 are switched to an activated character line, thereby activating one character line of the relevant secondary memory block. Hereinafter, exemplary embodiments of the decoder and the word line driver according to the present invention will be described in further detail with reference to FIGS. 5 and 6. For example, it can be implemented in the device of FIG.

O:\89\89I13.DOC -17- 200425162 者0 一種具圖3示例性架構之半導體記憶裝置之操作模式可 選擇啟動次記憶區塊110、丨20、130、140之一，以獲得2n-2 分頁長度。特別言之，當關閉控制信號PL0B與PL 1B時（例 如邏輯π高”狀態），僅有次記憶區塊11〇、12〇、130、140之 一根據行區塊位址CBA0與CBA1之邏輯狀態關閉，示如圖 4Α。此外’在此操作模式下，根據行區塊位址⑶^與⑶^ 之邏輯狀態啟動行解碼器371、372、373、374之一。 藉由示例，假設兩控制信號PL0B與PL1B均關閉（例如在 邏輯高狀態），且行區塊位址CBA0與CBA1均處於邏輯，，低” 狀態。在此情況下，NAND閘363與367之輸出將為邏輯，，高，，， 導致次解碼器312被啟動（假設理所當然，輸入所需位址信 號RAi至次解碼器3 12)。接著次解碼器3 12將產生適當控制 4吕號’俾使字元線驅動器111啟動次記憶區塊1丨〇之一字元 線WL一 0。此外，由於行區塊位址(：：；8八〇與（：]8入1均處於邏輯 ”低”狀態，故僅有邏輯電路392、391與381將運作，並因而 啟動行解碼器371。行解碼器371接收預解碼器375之行位址 貝讯，並接著於次記憶區塊11〇上之2n·2條行選擇線 中選擇一行選擇線（CSL)。亦即，對應於啟動之次記憶區塊 Π〇之半導體記憶裝置具分頁長度。例如在分頁模式操 作下，維持字元線（列）啟動，同時依序施加卜2個行位址^ 以存取被啟動列之記憶單元。 另一種具圖3示例性架構之 可選擇啟動兩個次記憶區塊， 半導體記憶裝置之操作模式 以獲得211-1分頁長度。特別言 O:\89\89113.DOC -18 - 200425162 之，若啟動控制信號PL0B(例如邏輯”低”狀態）並關閉控制 信號PL 1 B(例如邏輯”高狀態），則根據行區塊位址CB A1B與 CB A1之邏輯狀態，將啟動兩個次記憶區塊，與行區塊位址 CBA0及CBA0B之邏輯狀態無涉，示如圖4B。更特別言之， 若行區塊位址CBA1具邏輯”低”狀態，則啟動次記憶區塊 110與120之字元線WL_0與WL—1，與行區塊位址CBA0之邏 輯狀態無涉。此外，若行區塊位址CBA1具邏輯”高’’狀態， 則啟動次記憶區塊130與140之字元線WL_2與WL—3，與行 區塊位址CBA0之邏輯狀態無涉。再者，在此操作模式下， 根據行區塊位址CBA0之邏輯狀態，可選擇啟動與啟動之次 記憶區塊有關之行解碼器。 藉由示例，假設器動控制信號PL0B(例如邏輯π低”狀 態），並關閉控制信號PL1B(例如邏輯’f高”狀態）。在此情況 下，由於將具f’高”邏輯位準之控制信號PL1B輸入至控制電 路 360之兩NAND閘 363與 364，故各NAND電路之輸出將為 邏輯”高”狀態，與行區塊位址CBA0及CBA0B之邏輯狀態無 涉。進一步假設行區塊位址CBA1具邏輯'’低”狀態，故NAND 電路367之輸出將處於邏輯”高”狀態。在此情況下，由於各 NAND電路 363、3 64與 367之輸出為邏輯Π高Π，故次解碼器 312與322被啟動（假設理所當然，輸入所需位址信號RAi至 次解碼器）。接著次解碼器3 12與322將產生適當控制信號， 俾使對應之字元線驅動器111與121啟動次記憶區塊110與 120之各字元線WL_0與WL_1。 此外，當行區塊位址CBA1處於邏輯”低”狀態並啟動次記 O:\89\89113.DOC -19- 200425162 憶區塊110與12〇時，行解碼器371與372應分別啟動，以獲 得2nl分頁長度。在一較佳具體實施例中，可根據行區塊位 止CBA0之㉔輯狀怨，於次記憶區塊工或之一上啟動一 行選擇線（CSL)。例如在圖3中，若行區塊位址CBA〇處於邏 輯’’低”狀態，則至NAND電路392之輸入將為邏輯，，高'因 此，於久a己憶單元陣列區塊丨丨〇上啟動自行解碼器3 7 1產生 之行選擇線（CSL)，並響應於行選擇線（CSL)選擇次記憶區 塊no之行線。接著，藉由改變行區塊位址CBA〇為邏輯，，高，，， 將因NAND電路394之所有輸入均為邏輯，，高，，而關閉次記憶 區塊11〇之行解碼器371，並將啟動次記憶區塊12〇之行解碼 器 372。 因此，對圖4B所示之示例性操作模式而言，與啟動之字 凡線有關之分頁長度為211-1，其係以圖4A之操作模式所得之 分頁長度的兩倍。亦即，若使用者需要具2η-ι分頁長度之半 導體記憶裝置，則以控制信號產生器35〇產生一啟動控制信 號PL0B，並輸入至控制電路36〇，藉以改變半導體記憶裝 置分頁長度。 另一種具圖3示例性架構之半導體記憶裝置之操作模式 可選擇啟動四個次記憶區塊，以獲得2n分頁長度。特別言 之’若啟動控制信號PL 1B(例如邏輯，，低”狀態），則將器動 所有的次記憶區塊11 〇、120、1 30與140，與行區塊位址 CBAOB、CBAO、CBA1B及CBA1之邏輯狀態無涉，示如圖 4C。更特別言之，若控制信號PL1B為邏輯”低，，，則控制電 路360之各NAND電路363、364、367與368之輸出將為邏輯 O:\89\89113.DOC -20- 200425162 ’’高’’，與行區塊位址CBAOB、CBAO、CBA1B及CBA1之邏 輯狀悲無涉。在此操作模式下，將啟動次記憶區塊1 1 〇、 120、130與 140之字元線 WL—0、WL—1、WL—2與 WL 3，與 行區塊位址CBA0及CBA1之邏輯狀態無涉。 此外，在此操作模式下，可根據行區塊位址CBA0及CBA1 之邏輯狀態，選擇啟動與啟動之次記憶區塊有關之行解碼 器。故是否啟動一次記憶區塊之一給定行選擇線（CSL)，係 取決於行區塊位址CBA0及CBA1之邏輯狀態。故在此情況 下，半導體裝置具2n分頁長度。 圖3之示例性具體實施例之優點在於，由於控制信號產生 器350之施行具模式暫存器組353，故模式暫存器组353可輸 出控制信號，以根據位址與指令控制改變半導體裝置分頁 長度。 現將參閱圖5與6討論圖3中所示次解碼器與字元線驅動 器之示例性具體實施例。圖5係闡釋一本發明之一具體實施 例之次解碼器之電路圖。為闡釋與解析之故，圖5顯示圖3 之-入解瑪器3 12之一具體實施例。圖6係依本發明之一具體 貫施例之一字元線驅動器之部分驅動器電路系統之電路 圖〇 參閱圖5，次解碼器3 1 2包括一 N AND電路510、第一與第 二反相器520與530。NAND電路510接收一第一列位址 RAl(其中i==0、U，並自控制電路360之NAND電路363與367 輸出之控制信號。第一反相器520接收NAND電路510之輸出 信號，並產生一第一閘信號PXIDG。第二反相器53〇接收O: \ 89 \ 89I13.DOC -17- 200425162 or 0 The operation mode of a semiconductor memory device with the exemplary structure of FIG. 3 can be selected to activate one of the secondary memory blocks 110, 20, 130, and 140 to obtain 2n- 2 Page length. In particular, when the control signals PL0B and PL 1B are turned off (such as a logic π high state), only one of the secondary memory blocks 110, 120, 130, and 140 is based on the logic of the row block addresses CBA0 and CBA1. The state is closed, as shown in Figure 4A. In addition, 'In this operation mode, one of the row decoders 371, 372, 373, and 374 is started according to the logical state of the row block addresses CU ^ and CU ^. By way of example, suppose two The control signals PL0B and PL1B are both turned off (for example, in a logic high state), and the row block addresses CBA0 and CBA1 are both in a logic low state. In this case, the outputs of the NAND gates 363 and 367 will be logic, high, and cause the secondary decoder 312 to be activated (assuming, of course, the required address signal RAi is input to the secondary decoder 3 12). Next, the secondary decoder 312 will generate the appropriate control number 4 ', so that the character line driver 111 activates one of the character lines WL-0 of the secondary memory block 110. In addition, since the row block addresses (::; 8800 and (:) 8 into 1 are in a logic "low" state, only logic circuits 392, 391, and 381 will operate, and thus the row decoder 371 will be activated. The row decoder 371 receives the row address of the pre-decoder 375, and then selects a row selection line (CSL) from the 2n · 2 row selection lines on the secondary memory block 110. That is, corresponding to the activation The semiconductor memory device of the secondary memory block Π0 has a page length. For example, in the paging mode operation, the word line (column) is kept activated, and 2 row addresses are sequentially applied to access the memory of the activated column. Unit. Another option with the exemplary structure of Figure 3 is to activate two secondary memory blocks. The operating mode of the semiconductor memory device is to obtain a 211-1 page length. In particular, O: \ 89 \ 89113.DOC -18-200425162 If the control signal PL0B is activated (for example, the logic “low” state) and the control signal PL 1 B is turned off (for example, the logic “high state”), two times will be activated according to the logic state of the row block addresses CB A1B and CB A1. Memory block, and the logical state of row block addresses CBA0 and CBA0B Nothing involved, as shown in Figure 4B. More specifically, if the row block address CBA1 has a logic "low" state, the word lines WL_0 and WL-1 of the secondary memory blocks 110 and 120 are activated, and the row block The logic state of the address CBA0 is not involved. In addition, if the row block address CBA1 has a logic "high" state, the word lines WL_2 and WL-3 of the secondary memory blocks 130 and 140 are activated, and the row block bits The logic state of the address CBA0 is not involved. Furthermore, in this operation mode, according to the logic state of the row block address CBA0, the row decoder related to the memory block activated at the start can be selected. By way of example, the hypothesistor Control signal PL0B (such as logic π low) and turn off control signal PL1B (such as logic 'f high'). In this case, the control signal PL1B with f 'high logic level is input to the control The two NAND gates 363 and 364 of circuit 360, so the output of each NAND circuit will be a logic "high" state, which has nothing to do with the logical states of the row block addresses CBA0 and CBA0B. Further assume that the row block address CBA1 is logical. "Low" state, so the output of NAND circuit 367 will be at logic "High" In this case, since the outputs of each of the NAND circuits 363, 3 64, and 367 are logic Π high Π, the secondary decoders 312 and 322 are activated (assuming, of course, that the required address signal RAi is input to the secondary decoder) Then the secondary decoders 3 12 and 322 will generate appropriate control signals, so that the corresponding word line drivers 111 and 121 activate the respective word lines WL_0 and WL_1 of the secondary memory blocks 110 and 120. In addition, when the row block bit When the address CBA1 is in the logic "low" state and starts the secondary record O: \ 89 \ 89113.DOC -19- 200425162 When the memory blocks 110 and 120 are recalled, the row decoders 371 and 372 should be started respectively to obtain a 2nl page length. In a preferred embodiment, the CBA0 complaints can be stopped according to the row block position, and a row selection line (CSL) can be started on the next memory block or one. For example, in FIG. 3, if the row block address CBA0 is in a logic "low" state, the input to the NAND circuit 392 will be logic, and high '. Therefore, Yujiu has recalled the cell array block. The row selection line (CSL) generated by the self-decoder 3 7 1 is activated, and the row line of the secondary memory block no is selected in response to the row selection line (CSL). Then, by changing the row block address CBA0 to logic ,, High ,,, will turn off the decoder 371 of the secondary memory block 11o, and will activate the decoder 372 of the secondary memory block 120, because all the inputs of the NAND circuit 394 are logic, high. Therefore, for the exemplary operation mode shown in FIG. 4B, the page length related to the activated z-line is 211-1, which is twice the page length obtained in the operation mode of FIG. 4A. That is, If the user needs a semiconductor memory device with a 2η-ι page length, the control signal generator 35o generates an activation control signal PL0B and inputs it to the control circuit 36o, thereby changing the page length of the semiconductor memory device. 3 Exemplary Architectures of Semiconductor Memory Devices The operating mode can be selected to activate four secondary memory blocks to obtain a 2n page length. In particular, 'If the control signal PL 1B is activated (for example, logic, low' state), all secondary memory blocks will be moved 11 〇 , 120, 1 30, and 140 have nothing to do with the logical states of the row block addresses CBAOB, CBAO, CBA1B, and CBA1, as shown in Figure 4C. More specifically, if the control signal PL1B is logic "low", the outputs of the NAND circuits 363, 364, 367, and 368 of the control circuit 360 will be logic O: \ 89 \ 89113.DOC -20- 200425162 '' "High" has nothing to do with the logical state of the row block addresses CBAOB, CBAO, CBA1B, and CBA1. In this operating mode, the character lines WL of the secondary memory blocks 1 10, 120, 130, and 140 will be activated —0, WL-1, WL-2, and WL 3 are not related to the logical states of the row block addresses CBA0 and CBA1. In addition, in this operation mode, the logical states of the row block addresses CBA0 and CBA1 can be determined. , Choose to start the row decoder related to the secondary memory block. So whether to start a given row selection line (CSL) of a memory block depends on the logic state of the row block addresses CBA0 and CBA1. In this case, the semiconductor device has a 2n page length. The advantage of the exemplary embodiment of FIG. 3 is that since the control signal generator 350 implements the mode register group 353, the mode register group 353 can output control Signal to change the page length of a semiconductor device based on address and command control Exemplary embodiments of the secondary decoder and the word line driver shown in FIG. 3 will now be discussed with reference to FIGS. 5 and 6. FIG. 5 is a circuit diagram illustrating a secondary decoder of a specific embodiment of the present invention. For the sake of analysis, FIG. 5 shows a specific embodiment of FIG. 3-the entry-decomposer 312. FIG. 6 is a circuit diagram of a part of a driver circuit system of a word line driver according to a specific embodiment of the present invention. In FIG. 5, the secondary decoder 3 1 2 includes an N AND circuit 510, first and second inverters 520 and 530. The NAND circuit 510 receives a first column address RAl (where i == 0, U, and The control signals output by the NAND circuits 363 and 367 of the control circuit 360. The first inverter 520 receives the output signals of the NAND circuit 510 and generates a first gate signal PXIDG. The second inverter 53 receives

O:\89\89113.DOC -21 - 200425162 NAND電路510之輸出信號，並以一提昇位準產生一字元線 電源信號PXI。次解碼器3 12亦輸出一第二閘信號PXIB(其係 NAND電路510之輸出）。 參閱圖6，一字元線驅動器600包括複數個MOS電晶體 MN1、MN2、MN3、MN4。供應電源電壓VCC至MOS電晶 體MN1之閘極。MOS電晶體MN1之第一端子耦合至正規字 元線致動信號（NWE)線（如上述，NWE係由列解碼器150產 生）。MOS電晶體MN1之第二端子連結至MOS電晶體MN2之 閘極端子。MOS電晶體MN2之第一端子連結至字元線電源 信號PXI(例如自次解碼器312輸出）。MOS電晶體MN2之第 二端子連結至字元線WL。MOS電晶體MN3之閘極連結至第 一閘信號PXIDG(例如自解碼器312輸出）。M〇S電晶體MN4 之閘極連結至第二閘信號PXIB(例如自解碼器3 12輸出）。於 圖3中之一給定字元線驅動器111、121、131、141中施行之 字元線驅動器電路600數等於在對應之次記憶區塊上之字 元線數。 次解碼器312與字元線驅動器600(屬於字元線驅動器111) 響應於第一列位址RAi(其中i = 0與1)與控制電路360之輸出 信號啟動字元線WL_0。更特別言之，次解碼器3 12與字元 線驅動器600操作如後。次解碼器3 12根據輸入控制信號與 列位址產生第一閘信號PXIDG、第二閘信號PXIB，及字元 線電源信號PXI。特別言之，僅當第一列位址RAi(其中i = 0 與1)與圖3之NAND電路363及367之輸出信號處於邏輯”高” 狀態時，第一閘信號PXIDG與字元線電源信號PXI處於邏輯 O:\89\891I3.DOC -22- 200425162 ’’高”狀態。在此情況下，用於預充電字元線WL之第二閘信 號PXIB處於邏輯”低”狀態。O: \ 89 \ 89113.DOC -21-200425162 The output signal of the NAND circuit 510, and a word line power signal PXI is generated at an elevated level. The secondary decoder 3 12 also outputs a second gate signal PXIB (which is the output of the NAND circuit 510). Referring to FIG. 6, a word line driver 600 includes a plurality of MOS transistors MN1, MN2, MN3, and MN4. The power supply voltage VCC is supplied to the gate of the MOS transistor MN1. The first terminal of the MOS transistor MN1 is coupled to a regular word line activation signal (NWE) line (as described above, the NWE is generated by the column decoder 150). The second terminal of the MOS transistor MN1 is connected to the gate terminal of the MOS transistor MN2. The first terminal of the MOS transistor MN2 is connected to the word line power signal PXI (e.g., output from the secondary decoder 312). The second terminal of the MOS transistor MN2 is connected to the word line WL. The gate of the MOS transistor MN3 is connected to the first gate signal PXIDG (e.g. output from the decoder 312). The gate of the MOS transistor MN4 is connected to the second gate signal PXIB (for example, output from the decoder 3 12). The number of word line driver circuits 600 implemented in a given word line driver 111, 121, 131, 141 in one of Fig. 3 is equal to the number of word lines on the corresponding secondary memory block. The secondary decoder 312 and the word line driver 600 (belonging to the word line driver 111) activate the word line WL_0 in response to the first column address RAi (where i = 0 and 1) and the output signal of the control circuit 360. More specifically, the sub-decoder 312 and the word line driver 600 operate as follows. The secondary decoder 312 generates a first gate signal PXIDG, a second gate signal PXIB, and a word line power signal PXI according to the input control signal and the column address. In particular, only when the first column address RAi (where i = 0 and 1) and the output signals of the NAND circuits 363 and 367 of FIG. 3 are in a logic “high” state, the first gate signal PXIDG and the word line power supply The signal PXI is in a logic O: \ 89 \ 891I3.DOC -22- 200425162 "high" state. In this case, the second gate signal PXIB for the precharge word line WL is in a logic "low" state.

在圖6之字元線驅動器600中，供應電源電壓VCC至MOS 電晶體MN1之閘極，故MOS電晶體MNU亙導通。當第一閘 信號PXIDG與字元線電源信號PXI處於邏輯’’高”狀態，且第 二閘信號PXIB處於邏輯”低”狀態時，MOS電晶體MN3導 通，且MOS電晶體MN4關閉。因而在此情況下，字元線電 源信號PXI與字元線WL互相連結，並啟動字元線WL。 換言之，若第一閘信號PXIDG與字元線電源信號PXI處於 邏輯”低’’狀態，且第二閘信號PXIB處於邏輯”高”狀態，則 MOS電晶體MN3關閉，且MOS電晶體MN4導通。因而在此 情況下，字元線WL關閉。In the zigzag line driver 600 of FIG. 6, the power supply voltage VCC is supplied to the gate of the MOS transistor MN1, so the MOS transistor MNU 亘 is turned on. When the first gate signal PXIDG and the word line power signal PXI are in a logic “high” state, and the second gate signal PXIB is in a logic “low” state, the MOS transistor MN3 is turned on and the MOS transistor MN4 is turned off. In this case, the word line power signal PXI and the word line WL are connected to each other and the word line WL is activated. In other words, if the first gate signal PXIDG and the word line power signal PXI are in a logic "low" state, and the first The second gate signal PXIB is in a logic "high" state, the MOS transistor MN3 is turned off, and the MOS transistor MN4 is turned on. Therefore, in this case, the word line WL is turned off.

在上述圖3之示例性具體實施例中，控制信號產生器350 之施行具半導體記憶裝置之MRS 353，俾產生可改變分頁 長度之控制信號.。已知其它用以產生控制信號之方法與裝 置均可依本發明施行之。例如圖7闡釋依本發明之另一具體 實施例，利用線接合施行之控制信號產生器電路700 ;圖8 則闡釋依本發明之另一具體實施例，利用熔絲施行之控制 信號產生器。 更特別言之，圖7所示控制信號產生器700包含複數個接 合塾710a、710b、710c、720a、720b、720c及反相器 711、 721。接合墊710a與720a連結於電源電壓VCC，接合墊710b 與720b則接地。反相器711之一輸入端子連結至接合墊 710c，反相器721之一輸入端子則連結至接合墊720c。反相 O:\89\89113.DOC -23- 200425162 器711與721分別輸出控制信號PL0B與PL 1B。 連結接合墊710c至墊710a或墊71 Ob，以及連結接合墊 720c至墊720a或720b之製程，係於半導體記憶裝置製造期 間施行。第一控制信號PL0B與第二控制信號PL1B之邏輯狀 態將視接合墊之連結而定。例如圖7所示，其中接合墊7 1 0c 連結至接合墊710b，接合墊720c連結至接合墊720a，設定 控制信號PL1B於邏輯”高”狀態，並設定控制信號PL0B於邏 輯”低’’狀態。因此，若圖7之控制信號產生器電路700係於 圖3之示例性具體實施例中施行，則半導體記憶裝置分頁長 度將為2η“（見圖4B)。理所當然地，各接合墊間連結可變， 以產生不同邏輯狀態之控制信號，獲得所要的分頁長度。 已知接合墊與電力接腳（VCC、VSS)間之連結，可由金屬或 線接合為之。 參閱圖8，依本發明之另一具體實施例之控制信號產生器 800具二'極體耦合MOS電晶體MP1與MP2、雷射熔絲812與 822，及反相器8 13與823。MOS電晶體MP1具二極體耦合連 結，其中MOS電晶體MP1之閘極與汲極相互連結，且其源 極連結至電源電壓VCC。雷射熔絲812連結於MOS電晶體 MP1之汲極與接地電壓間。反相器813將MOS電晶體MP1汲 極端子之信號反相，並輸出控制信號PL1B。 類似地，MOS電晶體MP2亦具二極體耦合連結，其中MOS 電晶體MP2之閘極與汲極相互連結，且其源極連結至電源 電壓VCC。雷射熔絲822連結於MOS電晶體MP2之汲極與接 地電壓間。反相器823將MOS電晶體MP2汲極端子之信號反 O:\89\89113.DOC -24- 200425162 相’並輸出控制信號PL0B。 控制信號PL0B與PL1B之邏輯狀態端視雷射熔絲狀態而 定。更特別言之，若切斷雷射熔絲8 1 2或822，則對應之控 制信號將具邏輯”低”狀態，若未切斷雷射熔絲8丨2或822， 則對應之控制信號將具邏輯”高”狀態。例如假設雷射熔絲 8 12連結且雷射炼絲822切斷，則控制信號pl〇b處於邏輯，， 低’’狀態，且控制信號PL1B處於邏輯”高，，狀態。在此情況 下’若控制信號產生器電路8〇〇係於圖3之示例性具體實施 例中施行’則半導體記憶裝置分頁長度將為2n_1(見圖4B)。 理所當然地，控制信號產生器8〇〇適於根據雷射熔絲812與 822邏輯狀態產生具不同邏輯狀態之控制信號。 圖9係依本發明之一具體實施例之用以改變半導體記憶 裝置分頁長度之方法之高階流程圖。概言之，一種用以改 、炎半導體€憶裝置分頁長度之方法包括產生律定複數個分 頁長度#作杈式之一之第一控制信號（步驟91〇);根據第一 控制信號與一區塊位址產生第二控制信號（步驟920);以及 接著依律疋之分頁長度操作模式，利用第二控制信號改變 半導體裝置分頁長度（步驟93 0)。 在本毛明之一具體貫施例中，產生第一控制信號之步驟（步 驟910)包括根據例如由記憶體控制器或㈣接收之外部指令 與位址產生第一控制信號。例如步驟91〇可利用Μ)，由 圖3所不控制^號產生器35〇為之。在本發明之其它具體實 施例中T利用裝置或方法如控制信號產生器電路以及例 如參閱圖7或8所述方法產生第_控制信號。In the exemplary embodiment of FIG. 3 described above, the control signal generator 350 implements the MRS 353 with a semiconductor memory device, and generates a control signal that can change the page length. It is known that other methods and devices for generating control signals can be implemented according to the present invention. For example, FIG. 7 illustrates a control signal generator circuit 700 implemented by wire bonding according to another embodiment of the present invention, and FIG. 8 illustrates a control signal generator implemented by fuses according to another embodiment of the present invention. More specifically, the control signal generator 700 shown in FIG. 7 includes a plurality of couplings 710a, 710b, 710c, 720a, 720b, 720c, and inverters 711, 721. The bonding pads 710a and 720a are connected to the power supply voltage VCC, and the bonding pads 710b and 720b are grounded. One input terminal of the inverter 711 is connected to the bonding pad 710c, and one input terminal of the inverter 721 is connected to the bonding pad 720c. Inverted O: \ 89 \ 89113.DOC -23- 200425162 Devices 711 and 721 output control signals PL0B and PL 1B respectively. The process of connecting the bonding pad 710c to the pad 710a or the pad 71 Ob, and the bonding pad 720c to the pad 720a or 720b is performed during the manufacturing of the semiconductor memory device. The logic state of the first control signal PL0B and the second control signal PL1B will depend on the connection of the bonding pads. For example, as shown in FIG. 7, the bonding pad 7 1 0c is connected to the bonding pad 710b, the bonding pad 720c is connected to the bonding pad 720a, the control signal PL1B is set to a logic “high” state, and the control signal PL0B is set to a logic “low” state Therefore, if the control signal generator circuit 700 of FIG. 7 is implemented in the exemplary embodiment of FIG. 3, the page length of the semiconductor memory device will be 2η "(see Fig. 4B). As a matter of course, the connection between the bonding pads is variable to generate control signals of different logic states to obtain a desired page length. It is known that the connection between the bonding pad and the power pin (VCC, VSS) can be connected by metal or wire. Referring to FIG. 8, a control signal generator 800 according to another embodiment of the present invention has two pole-coupled MOS transistors MP1 and MP2, laser fuses 812 and 822, and inverters 8 13 and 823. The MOS transistor MP1 has a diode coupling connection. The gate and the drain of the MOS transistor MP1 are connected to each other, and the source is connected to the power supply voltage VCC. The laser fuse 812 is connected between the drain of the MOS transistor MP1 and the ground voltage. The inverter 813 inverts the signal from the drain terminal of the MOS transistor MP1 and outputs a control signal PL1B. Similarly, the MOS transistor MP2 also has a diode coupling connection, in which the gate and the drain of the MOS transistor MP2 are connected to each other, and the source thereof is connected to the power supply voltage VCC. The laser fuse 822 is connected between the drain of the MOS transistor MP2 and the ground voltage. The inverter 823 inverts the signal of the MOS transistor MP2 drain terminal O: \ 89 \ 89113.DOC -24- 200425162 phase 'and outputs the control signal PL0B. The logic state of the control signals PL0B and PL1B depends on the laser fuse status. More specifically, if the laser fuse 8 1 2 or 822 is cut off, the corresponding control signal will have a logic “low” state. If the laser fuse 8 2 or 822 is not cut off, the corresponding control signal will be Will have a logic "high" state. For example, assuming that the laser fuse 8 12 is connected and the laser refining wire 822 is cut off, the control signal pl0b is in a logic, low state, and the control signal PL1B is in a logic high, state. In this case, ' If the control signal generator circuit 800 is implemented in the exemplary embodiment of FIG. 3, the page length of the semiconductor memory device will be 2n_1 (see FIG. 4B). It goes without saying that the control signal generator 800 is suitable for The laser fuses 812 and 822 logic states generate control signals with different logic states. Figure 9 is a high-level flowchart of a method for changing the page length of a semiconductor memory device according to a specific embodiment of the present invention. In summary, a The method for changing the paging length of the MEMS memory device includes generating a first control signal (step 91), which is one of a plurality of paging lengths, and is generated according to the first control signal and a block address. The second control signal (step 920); and then according to the page length operation mode, the second control signal is used to change the page length of the semiconductor device (step 930). In the embodiment, the step of generating the first control signal (step 910) includes generating the first control signal according to, for example, an external command and an address received by the memory controller or the processor. For example, step 910 may utilize M). It does not control the ^ number generator 35. In other specific embodiments of the present invention, T uses a device or method such as a control signal generator circuit and, for example, the method described with reference to FIG. 7 or 8 to generate the _th control signal.

O:\89\89113.DOC -25- 200425162 此外，產生第一控制信號之步驟（步驟92〇)可參閱諸如圖 3所述為之，藉此使得控制電路處理來自控制信號產生器之 控制信號及一行區塊位址，產生可選擇控制記憶區塊之各 字元線控制電路之第二控制信號。再者，響應於第二控制 k號凋整分頁長度之步驟（步驟930)較佳包括響應於第二控 制信號，選擇啟動記憶區塊中具相同列位址之一或多條對 應字元線，藉以改變半導體記憶裝置分頁長度。 圖10闡釋得以施行本發明之記憶系統之簡略方塊圖。記 憶系統1000包括一 CPU 1001、記憶體控制器1002及複數個 纪憶模組1003。記憶模組1003包括施行本發明之複數個半 導體纪憶裝置1〇〇4。CPU 1001可為微處理器單元（Mpu)或 網路處理單元（NPU)等。CPU 1001經第一匯流排系統β1(例 如控制匯流排、資料匯流排、位址匯流排）連結至記憶體控 制器1002，記憶體控制器1002經第二匯流排系統B2(控制匯 流排、資料匯流排、位址匯流排）連結至記憶模組丨〇〇3。在 圖1 0之不例性架構中，CPU 1 001控制記憶體控制器丨〇〇2， 冗憶體控制器1002則控制記憶體ι〇〇4(但已知CPU可用於直 接控制記憶體，無需使用個別記憶體控制器）。 在圖10之示例性具體實施例中，各記憶模組1〇〇3均可代 表例如一記憶庫，且一給定記憶模組1〇〇3之各記憶裝置 1004均可代表得以施行本發明之記憶裝置。在此情況下， 各記憶裝置1004均可被邏輯分割為複數個次記憶區塊，並 如上述般受控而改變分頁長度。用以施行記憶存取及/或改 變分頁長度之控制電路系統均可位於記憶裝置丨〇〇4内。 O:\89\89I13.DOC -26- 200425162 在一較佳具體實施例中，一記憶模組之記憶裝置可具以 位兀組織’同時另-記憶模組之記憶裝置可具X16位元組 織。亦即，不同的記憶模組可以不同的位元組織運作。 在本^明之另一具體實施例中，記憶系統可包括一或多 個個別半導體記憶裝置(取代如圖1〇所示具複數個記憶裝 置之記憶模組）’以及—中央處理單元（無記憶體控制器）。 在此具體實施例中，記憶裝置直接與中央處理單元通聯。 此外，一半導體記憶裝置可具以位元組織，同時另一半導 體Z憶裝置可具><16位元組織。亦即，不同的記憶模組可以 不同的位元組織運作。 在另一具體實施例中，依本發明之記憶系統可包括直接 與記憶體控制器（無CPU)通聯之一或多個個別半導體記憶 裝置（取代如圖10所示具複數個記憶裝置之記憶模組）。在此 具體實施例中，一記憶裝置可具以位元組織，同時另一記 憶裝置寸具X16位元組織。 此處雖已參閱隨附圖式描述闡釋性具體實施例，應知本 毛明不以此處所述精確系統與方法具體實施例為限，熟悉 此技藝者’在不悖離本發明之範疇或精神下，可作各種其 它改變與改良。並欲將所有此類改變與改良納入隨附之申 請專利範圍所界定之本發明之範疇。 【圖式簡單說明】 圖1A、1B與1 c係闡釋依先前技藝之半導體記憶裝置之階 層記憶架構之簡圖。 圖2係依本發明之一具體實施例之記憶單元陣列區塊架O: \ 89 \ 89113.DOC -25- 200425162 In addition, the step of generating the first control signal (step 92) can be referred to, for example, as described in FIG. 3, so that the control circuit processes the control signal from the control signal generator. And a row of block addresses to generate a second control signal that can selectively control each word line control circuit of the memory block. Furthermore, the step (step 930) of responding to the second control of the page length of the k number preferably includes, in response to the second control signal, selecting one or more corresponding word lines with the same column address in the memory block to be activated. To change the page length of the semiconductor memory device. FIG. 10 illustrates a simplified block diagram of a memory system in which the present invention can be implemented. The memory system 1000 includes a CPU 1001, a memory controller 1002, and a plurality of memory modules 1003. The memory module 1003 includes a plurality of semiconductor memory devices 1004 for implementing the present invention. The CPU 1001 may be a microprocessor unit (Mpu) or a network processing unit (NPU). The CPU 1001 is connected to the memory controller 1002 through the first bus system β1 (such as the control bus, the data bus, and the address bus), and the memory controller 1002 is connected to the memory controller 1002 through the second bus system B2 (control bus, data Bus, address bus) are connected to the memory module. In the example architecture of FIG. 10, CPU 1 001 controls the memory controller 丨 002, and redundant memory controller 1002 controls the memory ι〇〇4 (but it is known that the CPU can be used to directly control the memory, No separate memory controller is required). In the exemplary embodiment of FIG. 10, each memory module 1003 can represent, for example, a memory bank, and each memory device 1004 of a given memory module 1003 can represent the implementation of the present invention. Memory device. In this case, each memory device 1004 can be logically divided into a plurality of secondary memory blocks, and controlled as described above to change the page length. The control circuit system for performing memory access and / or changing the page length can be located in the memory device. O: \ 89 \ 89I13.DOC -26- 200425162 In a preferred embodiment, the memory device of a memory module can be organized in a bit structure, and the memory device of a memory module can be organized in X16 bits. . That is, different memory modules can operate in different bit organizations. In another specific embodiment of the present invention, the memory system may include one or more individual semiconductor memory devices (instead of a memory module having a plurality of memory devices as shown in FIG. 10) 'and a central processing unit (no memory Controller). In this specific embodiment, the memory device is directly in communication with the central processing unit. In addition, one semiconductor memory device may have a bit organization, while the other semiconductor Z memory device may have a < < 16-bit organization. That is, different memory modules can operate in different bit organizations. In another specific embodiment, the memory system according to the present invention may include one or more individual semiconductor memory devices directly communicating with the memory controller (without CPU) (instead of the memory having a plurality of memory devices as shown in FIG. 10). Module). In this embodiment, one memory device may be organized in bits, while the other memory device is organized in X16 bits. Although reference has been made to the description of the illustrative embodiments herein, it should be understood that the present Maoming is not limited to the specific embodiments of the precise systems and methods described herein, and those skilled in the art will not depart from the scope of the present invention. In the spirit, various other changes and improvements can be made. It is intended to incorporate all such changes and improvements into the scope of the invention as defined by the scope of the accompanying patent application. [Brief description of the drawings] Figures 1A, 1B, and 1c are diagrams illustrating the hierarchical memory architecture of a semiconductor memory device according to the prior art. FIG. 2 is a block diagram of a memory cell array according to a specific embodiment of the present invention

O:\89\89113.DOC -27- 200425162 構簡圖’其可改變半導體記憶裝置分頁長度。 圖3係依本發明之—具體實施例之記憶單元 雷政m +1- 已塊之 2:，其可利用MRS(模式暫存器組）產生之控制信號 +V體記憶裝置分頁長度。 “圖4 A、4B與4C係闡釋圖3之記憶單元陣列區塊之各操作 杈式之表圖，纟中可獲得帛導體記憶裝置之不同分頁長度。 圖5闡釋可於圖3之電路中施行之依本發明之一具體實^施 例之次解碼器之電路圖。 ，係可於圖3之電路中施行之依本發明之一具體實施例 之子元線驅動器之電路圖。 圖7闡釋依本發明之一具體實施例之控制信號產生器。 圖8闡釋依本發明之另一具體實施例之控制信號產生器。 圖9係依本發明之一具體實施例之用以改變半導體記憶 裝置分頁長度之方法之高階流程圖。 圖10蘭釋得以施行本發明之記憶系統之簡略方塊圖。 【圖式代表符號說明】 元件名稱 半導體記憶裝置 記憶庫 記憶單元陣列區塊 次記憶單元陣列區塊 字元線驅動器 次解碼器 元件編號 100 100A，100B，100C，100D 100a ， l〇〇b ， 100c ， 100d 110 ， 120 ， 130 ， 140 in，121，m，141 112 ， 122 ， 132 ， 142 ， 212 ， 222 ， 232 ， 242 ， 312 ， 322 ， 332 ， 342 O:\89\89113.DOC -28 - 200425162 150 列解碼器 200 ， 300 記憶區塊 250 ， 360 控制電路 350 ， 800 控制信號產生器 351 指令緩衝器 352 位址緩衝器 353 模式暫存器組 361 ， 362 ， 365 ， 366 ， 711 ， 721 ， 813 ， 823 363 ， 364 ， 367 ， 368 ， 510 反相器 NAND電路 371〜374 行解碼器 375 預解碼器 381〜384 ， 391〜398 邏輯電路 520 第一反相器 530 第二反相器 600 字元線驅動器 700 控制信號產生器電路 710a，710b，710c，720a，720b，720c 接合墊 812 ， 822 雷射熔絲 1000 記憶系統 1001 中央處理單元（CPU) 1002 記憶體控制器 1003 記憶模組 1004 記憶體 O:\89\89113.DOC -29-O: \ 89 \ 89113.DOC -27- 200425162 Schematic ’which can change the page length of semiconductor memory devices. Fig. 3 is a memory unit according to a specific embodiment of the present invention. Lei Zheng m + 1- Block 2: 2: It can use the control signal generated by MRS (mode register group) + the page length of the V memory device. "Figures 4 A, 4B, and 4C are table diagrams illustrating the various operation patterns of the memory cell array block of Figure 3, and the different page lengths of the conductor memory device can be obtained in Figure 2. Figure 5 illustrates this in the circuit of Figure 3. The circuit diagram of the decoder in accordance with one embodiment of the present invention implemented in accordance with one embodiment of the present invention is a circuit diagram of a sub-element line driver in accordance with one embodiment of the present invention that can be implemented in the circuit of FIG. 3. FIG. A control signal generator according to a specific embodiment of the present invention. FIG. 8 illustrates a control signal generator according to another specific embodiment of the present invention. FIG. 9 is a view for changing a page length of a semiconductor memory device according to a specific embodiment of the present invention. High-level flowchart of the method. Figure 10 A simplified block diagram of a memory system capable of implementing the present invention. [Illustration of Representative Symbols] Component Name Semiconductor Memory Device Memory Cell Array Block Secondary Memory Cell Array Block Character Line driver secondary decoder element numbers 100 100A, 100B, 100C, 100D 100a, 100b, 100c, 100d 110, 120, 130, 140 in, 121, m, 141, 112, 122 132, 142, 212, 222, 232, 242, 312, 322, 332, 342 O: \ 89 \ 89113.DOC -28-200425162 150 column decoder 200, 300 memory block 250, 360 control circuit 350, 800 control Signal generator 351 Instruction buffer 352 Address buffer 353 Mode register group 361, 362, 365, 366, 711, 721, 813, 823 363, 364, 367, 368, 510 Inverter NAND circuit 371 ~ 374 Row decoder 375 Predecoder 381 ~ 384, 391 ~ 398 Logic circuit 520 first inverter 530 second inverter 600 word line driver 700 control signal generator circuit 710a, 710b, 710c, 720a, 720b, 720c Bonding pads 812, 822 Laser fuse 1000 Memory system 1001 Central processing unit (CPU) 1002 Memory controller 1003 Memory module 1004 Memory O: \ 89 \ 89113.DOC -29-

Claims (1)

200425162 拾、申請專利範圍： L 一種半導體裝置，包括·· 一被邏輯分割為複數個記憶區塊之記憶單元陣列，其 中各圮憶區塊均為一對應區塊位址所定址； 複數個子元線控制電路，其中各字元線控制電路均與 忒等。己憶區塊之一有關，以啟動相關記憶區塊之一 線；及 70 用以選擇控制該等字元線控制電路之控制電路，俾 啟動具-同列位址之_或多條對應字元線，以改變一該 半導體記憶裝置之分頁長度。 X 2. 3. 4· 口申 '專利範圍第1項之裝置，#中該控制電路接收—行 區塊位址與一第一控制信號為輸入，接著產生一第二栌 制信號以選擇啟動一或多個字元線控制電路。 一工 如:請專利範圍第2項之裝置，進—步包括—控制信號產 生為’其接收-外部指令與—外部位址’接著根據該外 部指令與該外部位址產生該第一控制信號。 如申請專利範圍第3項之裝置，纟中該控制信號產生器包 括· 内部位址之位置緩衝 一用以接收該外部位址並產生一 器； 用以接收該外部指令並產生一 内部指令之指令緩 衝 一用以根據該内部位 # 5虎之模式暫存器組。 址與該内部指令產生該第一 控制 O:\89\89I13.DOC 200425162 5·如申請專利範圍第2項之裝置，其中各字元線控制電路均 具一個次解碼器電路與一相關字元線驅動器電路。 6·如申請專利範圍第5項之裝置，其中各個次解碼器電路均 接收一列位址以及自該控制電路輸出之該第二控制信 號’以選擇啟動該相關字元線驅動器電路。 7.如申請專利範.圍第1項之裝置，其中該區塊位置包括一列 位址或一行位址。 8·如申請專利範圍第2項之裝置，進一步包括一用以產生該 第一控制#號之控制信號產生器，其中配置該控制信號 產生裔以經由線接合、金屬選用品與熔絲選用品之一產 生該第一控制信號。 9·如申請專利範圍第2項之裝置，其中當關閉該第一控制信 號時’即啟動在該等複數個記憶區塊之—記憶區塊處之 一字το線，以及其中當啟動該第一控制信號時，即啟動 在該等複數個記憶區塊之二記憶區塊處之具相同列位址 之至少兩字元線。 10·—種記憶系統，包括·· -用以產生複數個指令與位置信號之記憶控制器；及 一接收該等指令與位置信號之第-記憶模組，該第- 己隐杈且包括具-第_記憶裝置之複數個記憶裝置，其 中該第一記憶裝置包括： 一被邏輯分割為複數個記憶區塊之記憶單元陣列， 其中各記憶區塊均為一對應區塊位址所定址； # Km $ m ^制電路’其中各字元線控制電路均 O:\89\89113.DOC 200425162 :該等記憶區塊之一有關’以啟動相關記憶區塊之一 字元線；及 -用以選擇控制胃等字元線控制電路之控制電路， 俾啟動具一同列位址之一或多條對應字元線，以改變 一該半導體記憶裝置之分頁長度。 1如申請專利範圍第H)項之記憶系統，進一步包括一接收 該記憶控制器產生之該等指令與位置信號之第二記憶模 組，該第二記憶模組包括具—第二記憶裝置之複數個記 憶裝置，其中該第二記憶裝置包括一被邏輯分割為複數 個記憶區塊之記憶單元陣列； 其中該第-記憶裝置具一第一位元組織，且該第二記 憶裝置具-第二位元組織，其中該第一位元組織與該第 二位元組織相異。 12. 如申請專利範圍第1G項之記憶系統，其中該控制電路接 收一行區塊位址與一第一控制信號為輸入，接著產生一 第二控制信號以選擇啟動一或多個字元線控制電路。 13. 如申請專利範圍第12項之記憶系統，進一步包括一控制 信號產生器，其中該控制信號產生器包括·· 一用以接收一自該記憶控制器產生之位址信號並產生 一内部位址之位置緩衝器； 一用以接收一自該記憶控制器產生之指令並產生一内 部指令之指令緩衝器；及 一用以根據該内部位址與該内部指令產生該第一控制 信號之模式暫存器組。 〇；\89\89 Π 3. D〇c 200425162 申明專利範圍第1 3項之記憶系統，其中當關閉該第〆 控制信號時，即啟動在該等複數個記憶區塊之_記憶區 塊處之一字元線，以及直中去 /、τ田啟動该第一控制信號時， 即啟動在該等複數個記恃F抬 U ‘隱&塊之二記憶區塊處之具相同 列位址之至少兩字元線。 15· —種記憶系統，包括： 一用以產生複數個指令與位置㈣之巾央處理單元；及 一接收該等指令與位置信號之第-記憶模組，該第- 記憶模組包括具一第_ # #壯m & ^弟5己憶裝置之複數個記憶裝置，其 中該第一記憶裝置包括： 八 -被邏輯分割為複數個記憶區塊之記憶單元陣列， 其中各記憶區塊均為-對應區塊位址所定址； 複數個字元線控制電路，苴中 甲各予TL線控制電路均 與该專記憶區塊之_右關，丨v玲今& λ a 百關 乂启文動相關記憶區塊之一 字先線；及 -用以選擇控制該等字元線控制電路之控制電路， 俾啟動具-同列位址之一或多條對應字元線，以 一該半導體記憶裝置之分頁長度。 Κ如申請專利範圍第15項之記憶系統，進—步包括—接 該中央處理單元產生之料指令與位置信號之第二 模組，該第二記憶模組包括具—第二記憶裝置之複數: 記憶裝置，其中該第-#播姑$ — > 弟一 3己憶裝置包括一被邏輯分割為# 數個記憶區塊之記憶單元陣列； 其中該第一記憶裝置具一第一位元組織，且該第二記 O:\89\89U3.DOC -4- 200425162 隐裝置具一第二位元組織，其中該第一位元組織與該第 二位元組織相異。 α ^申請專利範圍第15項之記憶系統，該第—記憶裝置進 ν匕括控制k唬產生器，其中該控制信號產生器包 括： 用以接收一自該中央處理單元產生之位址信號並產 生一内部位址之位置緩衝器； 用以接收—自该中央處理單元產生之指令並產生― 内部指令之指令緩衝器；及 用以根據該内部位址與該内部指令產生該第_控制 信號之模式暫存器組。 18·如申請專利範圍第17項之記憶系統，其中當關閉該第一 &制U時’即啟動在該等複數個記憶區塊之—記憶區 塊處之一字疋線，以及其中當啟動該第一控制信號時， Ρ啟動在5亥等複數個記憶區塊之二記憶區塊處之具相同 列位址之至少兩字元線。 19. 如申請專利範圍第15項之記憶系統，其中該十央處理單 兀係一網路處理單元（NPU)。 20. —種§己憶系統，包括·· 用以產生複數個指令與位置信號之記憶控制器；及 -接收該等指令與位置信號之第一記憶裝置，其中該 第一記憶裝置包括： 一被邏輯分割為複數個記憶區塊之記憶單元陣列， 其中各記憶區塊均為一對應區塊位址所定址； O:\89\89113.DOC 200425162 複數個字元線控制電路，其中各字元線控制電路均 與該等記憶區塊之-有關，以啟動相關記憶區塊之— 字元線；及 -用以選擇控制該等字元線控制電路之控制電路， 俾啟動具-同列位址之一或多條對應字元線，以改變 一該半導體記憶裝置之分頁長度。 21.如申請專利範圍第2〇項之記憶系統，進—步包括一接收 該記憶控制器產生之該等指令與位置信號之第二記憶裝 置’該第二記憶裝置包括—被邏輯分割為複數個記憶區 塊之記憶單元陣列； 其中該第-記憶袭置具一第一位元組織，且該第二記 憶裝置具-第二位元組織’其中該第一位元組織與該第 二位元組織相異。 22· —種記憶系統，包括： 一用以產生複數個指令與位置信號之中央處理單元；及 一接收該等指令與位置信號之第—記憶裝置，該第— 記憶裝置包括： -被邏輯分割為複數個記憶區塊之記憶單元陣列， 其中各記憶區塊均為一對應區塊位址所定址； 複數個字元線控制電路，其中各字元線控制電路均 與該等記憶區塊之-有關，以啟動相關記憶區塊之_ 字元線；及 -用以選擇控制該等字元線控制電路之控制電路， 俾啟動具一同列位址之一或多條對應字元線，以改變 O:\89\89113.DOC -6- 200425162 一該半導體記憶裝置之分頁長度。 23.如申請專利範圍第22項之記憶系統，進一步包括—接 =中央處理單元產生之該等指令與位置信號之第二 衮置’其中該第二記憶裝置包括一被邏輯分割為複數個 記憶區塊之記憶單元陣列； 其中該第-記憶裝置具一第—位元組織，且該第二吃 憶裝置具-第二位元組織，其中該第一位元組織與該第 二位元組織相異。 24·如申請專利範圍第22項之記憶系統，其中該中央處理單 元係一網路處理單元（NPU)。 25. 如申請專利範圍第22項之記憶系統，其中該中央處理單 元係一微處理器單元（MPU)。 26. 種用以改變一具有被邏輯分割為複數個記憶區塊之士己 憶單元陣列之半導體記憶裝置之分頁長度的方法，其°中 各記憶區塊係由—對應區塊位址所定址，該方法包括步 驟： 產生律疋複數個分頁長度操作模式之第一控制信 號； 根據該第—控制信號及一區塊位址產生-第二控制作 號；及 ° 響應於該第二控制信號，選擇啟動具-相同列位址之 該等記憶區塊中之-或多條字元線，以提供-對應於該 律定分頁長度操作模式之該半導體記憶裝置之二 O:\89\89U3.DOC 200425162 27·如申4專利範圍第26項之方法，其中產生該第一控制信 號之步驟包括步驟·· 接收一指令信號及一位址信號；及 位置k號產生該第一控制信號。 之方法，其中該第一控制信號係 28. 根據該指令信號與該 如申請專利範圍第27項 由一模式暫存器組產生 29. 如申請專利範圍第26項之方法， 中之一或多條字元線之步驟包括 其中啟動該等記憶區 步驟： 塊 輸入该苐二控制信號與一列位 巧位置於複數個次解碼器；及 根據該次解碼器產生之字开给兩 予凡線電源信號啟動與該等記 憶區塊有關之一或多個字元線驅動器。 寺 O:\89\89I13.DOC200425162 Scope of patent application: L A semiconductor device including a memory cell array logically divided into a plurality of memory blocks, where each memory block is addressed by a corresponding block address; a plurality of sub-elements Line control circuit, in which each word line control circuit is equal to 忒. One of the self-memory blocks is related to activate a line of the relevant memory block; and 70 is a control circuit for selecting and controlling the control lines of these character lines, and the _ or multiple corresponding character lines of the same address are activated. To change the page length of a semiconductor memory device. X 2. 3. 4 · The device of the first scope of the patent application, the control circuit in # receives the line block address and a first control signal as inputs, and then generates a second control signal to choose to start One or more word line control circuits. One example is as follows: please request the device in the second scope of the patent, further including-the control signal is generated as 'its receiving-external command and-external address', and then the first control signal is generated according to the external command and the external address . If the device in the scope of patent application is No. 3, the control signal generator in the first step includes: a position buffer of an internal address to receive the external address and generate a generator; a device to receive the external instruction and generate an internal instruction The instruction buffer is used to register a register group according to the internal bit # 5 tiger mode. Address and the internal instruction to generate the first control O: \ 89 \ 89I13.DOC 200425162 5. If the device in the scope of the patent application is the second item, wherein each word line control circuit has a secondary decoder circuit and a related character Line driver circuit. 6. The device according to item 5 of the patent application, wherein each secondary decoder circuit receives a column of addresses and the second control signal 'output from the control circuit to selectively activate the relevant word line driver circuit. 7. The device as claimed in claim 1. The block location includes a row of addresses or a row of addresses. 8. The device according to item 2 of the scope of patent application, further comprising a control signal generator for generating the first control # number, wherein the control signal generator is configured to be connected by wire bonding, metal options and fuse options One of them generates the first control signal. 9. The device according to item 2 of the scope of patent application, wherein when the first control signal is turned off, the word το line at the memory blocks of the plurality of memory blocks is activated, and when the When a control signal is generated, at least two word lines with the same column address are activated at two of the plurality of memory blocks. 10 · —A memory system, including a memory controller for generating a plurality of instructions and position signals; and a first memory module receiving the instructions and position signals, the first memory module including A plurality of memory devices of the _th memory device, wherein the first memory device includes: a memory cell array logically divided into a plurality of memory blocks, wherein each memory block is addressed by a corresponding block address; # Km $ m ^ Control circuit 'where each character line control circuit is O: \ 89 \ 89113.DOC 200425162: one of these memory blocks is related' to activate a character line of the relevant memory block; and-use A control circuit for controlling a character line control circuit such as a stomach is selected, and one or more corresponding character lines with an address in a row are activated to change the page length of a semiconductor memory device. 1. The memory system according to item H) of the patent application scope, further comprising a second memory module that receives the instructions and position signals generated by the memory controller. The second memory module includes a second memory device. A plurality of memory devices, wherein the second memory device includes a memory cell array logically divided into a plurality of memory blocks; wherein the first memory device has a first bit organization, and the second memory device has a first A two-dimensional organization, wherein the first-level organization is different from the second-level organization. 12. For example, the memory system of item 1G of the patent application scope, wherein the control circuit receives a row of block addresses and a first control signal as inputs, and then generates a second control signal to selectively activate one or more word line controls. Circuit. 13. The memory system according to item 12 of the patent application, further comprising a control signal generator, wherein the control signal generator includes: a receiver for receiving an address signal generated from the memory controller and generating an internal bit An address buffer; an instruction buffer for receiving an instruction generated from the memory controller and generating an internal instruction; and a mode for generating the first control signal according to the internal address and the internal instruction Register group. 〇 ； \ 89 \ 89 Π 3. D〇c 200425162 declares the memory system of item 13 of the patent scope, wherein when the second control signal is turned off, it starts at the _memory block of the plurality of memory blocks One of the character lines, and the straight control /, τ field when the first control signal is activated, it starts to have the same rank at the two memory blocks of the plurality of memory blocks U &H; Address at least two character lines. 15 · —A memory system including: a central processing unit for generating a plurality of instructions and position signals; and a -memory module that receives the instructions and position signals, the -memory module includes a No. _ # #m 5 &d; a plurality of memory devices of the fifth memory device, wherein the first memory device includes: Eight-a memory cell array logically divided into a plurality of memory blocks, wherein each memory block is Addressed by-the corresponding block address; a plurality of word line control circuits, each of the TL line control circuits in the middle and the _ right off of the dedicated memory block, v Ling Jin & λ a hundred off One of the word lines of the relevant memory block of Qiwendong; and-a control circuit for selecting and controlling the control lines of these word lines, 俾 starting device-one or more corresponding word lines of the same address, Page length of a semiconductor memory device. Κ If the memory system of the 15th scope of the patent application, further includes-a second module connected to the material instruction and position signal generated by the central processing unit, the second memory module includes a plurality of second memory devices : A memory device, wherein the first-# 播 姑 $ — > Diyi 3 Jiyi device includes a memory cell array logically divided into # memory blocks; wherein the first memory device has a first bit Organization, and the second record O: \ 89 \ 89U3.DOC -4- 200425162 has a second-bit organization, wherein the first-bit organization is different from the second-bit organization. The memory system of item 15 in the scope of the patent application, the first memory device further controls the generator, wherein the control signal generator includes: a receiver for receiving an address signal generated from the central processing unit and Generating a location buffer for an internal address; for receiving—an instruction generated from the central processing unit and generating—an internal instruction buffer; and for generating the _th control signal based on the internal address and the internal instruction Mode register group. 18. The memory system of item 17 in the scope of patent application, wherein when the first & system U is turned off, a word line at the memory block of the plurality of memory blocks is activated, and when the When the first control signal is activated, P activates at least two word lines with the same column address at two memory blocks of a plurality of memory blocks such as 5H. 19. For example, the memory system of claim 15 in which the ten central processing unit is a network processing unit (NPU). 20. —A self-memory system including a memory controller for generating a plurality of instructions and position signals; and a first memory device receiving the instructions and position signals, wherein the first memory device includes: a A memory cell array that is logically divided into a plurality of memory blocks, where each memory block is addressed by a corresponding block address; O: \ 89 \ 89113.DOC 200425162 a plurality of word line control circuits, where each word The element line control circuits are all-related to these memory blocks to activate the-character lines of the relevant memory blocks; and-the control circuits used to select and control these word line control circuits, Address one or more corresponding word lines to change the page length of a semiconductor memory device. 21. The memory system of claim 20 in the scope of patent application, further comprising a second memory device that receives the instructions and position signals generated by the memory controller. The second memory device includes-is logically divided into a plurality Memory cell array of two memory blocks; wherein the first memory device has a first bit tissue, and the second memory device has a second bit tissue, wherein the first bit tissue and the second bit Meta organizations differ. 22 · A memory system comprising: a central processing unit for generating a plurality of instructions and position signals; and a first-memory device for receiving the instructions and position signals, the first-memory device comprising:-logically divided Is a memory cell array of a plurality of memory blocks, where each memory block is addressed by a corresponding block address; a plurality of word line control circuits, wherein each word line control circuit is connected to the memory block. -Relevant to activate the _ character lines of the relevant memory blocks; and-control circuits for selecting and controlling these character line control circuits, 俾 activate one or more corresponding character lines with the addresses listed together to Change O: \ 89 \ 89113.DOC -6- 200425162-the page length of the semiconductor memory device. 23. The memory system according to item 22 of the scope of patent application, further comprising-connecting = the second setting of the instructions and position signals generated by the central processing unit, wherein the second memory device includes a logical division into a plurality of memories An array of memory cells in the block; wherein the first memory device has a first bit organization, and the second memory device has a second bit organization, wherein the first bit organization and the second bit organization Different. 24. The memory system of claim 22, wherein the central processing unit is a network processing unit (NPU). 25. The memory system of claim 22, wherein the central processing unit is a microprocessor unit (MPU). 26. A method for changing the page length of a semiconductor memory device having a self-memory cell array logically divided into a plurality of memory blocks, wherein each memory block is addressed by a corresponding block address The method includes the steps of: generating a first control signal of a plurality of page length operation modes; generating a second control number according to the first control signal and a block address; and responding to the second control signal , Choose to activate-or multiple character lines in the memory blocks with the same column address to provide-corresponding to the two of the semiconductor memory device of the regular page length operation mode O: \ 89 \ 89U3 .DOC 200425162 27. The method of item 26 in the scope of patent application 4, wherein the step of generating the first control signal includes the steps of: receiving a command signal and a bit address signal; and generating the first control signal by the position k number. Method, wherein the first control signal is 28. According to the instruction signal and the patent application scope item 27 is generated by a mode register group 29. Such as the patent application scope item 26 method, one or more of The step of a word line includes the steps of activating the memory areas: inputting the second control signal and a row of bit positions in a plurality of sub-decoders; and turning on the power of the two Yufan lines according to the word generated by the decoder The signal activates one or more word line drivers associated with the memory blocks. Temple O: \ 89 \ 89I13.DOC
TW92131236A 2002-11-19 2003-11-07 Circuits and methods for changing page length in a semiconductor memory device TWI233619B (en)

Applications Claiming Priority (2)

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KR10-2002-0072093A KR100510496B1 (en) 2002-11-19 2002-11-19 Semiconductor memory device having the structure of being capable of converting page length according to specific mode, and method of converting page length of the semiconductor memory device
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US7793037B2 (en) * 2005-05-31 2010-09-07 Intel Corporation Partial page scheme for memory technologies
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US8811110B2 (en) 2012-06-28 2014-08-19 Intel Corporation Configuration for power reduction in DRAM
US10394456B2 (en) 2017-08-23 2019-08-27 Micron Technology, Inc. On demand memory page size
CN110910923A (en) * 2018-09-14 2020-03-24 北京兆易创新科技股份有限公司 Word line decoding method and nonvolatile memory system
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