TWI417894B - Structure and method of implementing power savings during addressing of dram architectures - Google Patents

Description

Structure and method for implementing power saving during addressing of a dynamic random access memory architecture

The present invention generally relates to a memory storage device, and more particularly to a design structure that implements power saving during addressing of a Dynamic Random Access Memory (DRAM) device.

DRAM integrated circuit arrays have been used for many years, and their storage capacity has also increased significantly through advanced semiconductor process and circuit design techniques. The rapid development of semiconductor process and circuit design technology has also led to an increase in integration, resulting in a significant reduction in memory array size and cost, and improved process yield.

A DRAM memory cell generally includes a basic element such as an access transistor (switch) and a capacitor that stores a binary data bit in the form of a charge. Basically, a first voltage stored in the capacitor represents a logic HIGH or a binary "1" (eg, V _DD ), and a second voltage on the storage capacitor represents a logical LOW or binary "0" value (eg, ground). . A fundamental disadvantage of DRAM devices is that the charge in the capacitor will eventually leak out, so the capacitor charge must be "updated" or the data bits stored in the memory cell will be lost.

As the power requirements of computer systems increase, there is a constant need for new ways to save power. Recent research has shown that in a memory cache, up to 95% of all memory accesses occur in only 25% of caches. Therefore, a considerable number of memory devices are often in a standby state, so power is consumed. In current DRAM architectures, long (large) page access is typically required to account for the performance of certain types of applications. However, addressing large pages can cause many devices within the DRAM array to receive column address commands, which can consume considerable power for the memory system. The first figure shows an exemplary DRAM architecture 100 in which the startup column arrangement results in considerable power consumption.

In the simplified example shown, the DRAM architecture 100 of the first diagram is an array of 4 x 4 memory cells 102, each cell including a storage capacitor 104 and an access transistor 106 (however, modern DRAM) There may be thousands of memories in terms of length and width). In a read operation, the selected column of memory cells is enabled, and each of the transistors connected to the word line 108 of the column is turned on and the capacitors of the column are connected to An associated sense line 110, and the sense line 110 is (optionally) coupled to the sense amplifier 112, and the sense amplifier 112 recognizes and latches the stored signal representing 0 or 1. The value from the appropriate row is selected and connected to the output. At the end of the read cycle, the column values are restored to the capacitor 104 that was discharged during the read process. A write operation charges the memory cell capacitor 104 to the desired value by the sense line 110 by activating the column and connecting the data value to be written to the sense line 110. In the process of writing to a particular memory cell, the entire column is read, a value is changed, and the entire column is rewritten.

In some applications, it is possible to "step" the action of accessing the column. To effectively optimize the power to start the entire column. However, in many applications, the randomness of the access itself offsets the page depth, because some systems never use large page access, or there is no way to "step" enough. The number of rows to compensate for the number of devices that were previously energized. Therefore, in general, there is a need to provide a method of reducing the power used to actively address data in a memory system.

One way to reduce power consumption is to place the DRAM in a "degrade" mode where the DRAM enters a closed stand-by state. Further information on this method can be found in the U.S. Patent Application Serial No. 2006/0047493 filed by. In particular, in the case of US 2006/0047493, a deep power down mode using real memory portions for a plurality of volatile real memory portions is mentioned without causing data loss.

From the above, it is preferable to be able to continuously access the DRAM while saving power, and to some extent, it does not take extra time because the DRAM is to be woken up from the late standby mode.

The problems discussed above or the absence of the foregoing may be overcome or solved in the exemplary embodiments, wherein a random access memory device including an array of individual memory cells arranged in rows and columns is proposed. (random access memory device), each memory cell has one of its associated access devices Each column of the array further includes a plurality of N-type lines associated therewith, where N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given column is only coupled to One of the N-character lines of the column, and the address decoder logic in communication with the array signal, configured to receive a plurality of column address bits, and to be addressed by the column address bits The identified requirement column determines which of the N partitions in the request column are to be accessed so as not to activate the access devices within a select column but not within a partition to be accessed.

In another embodiment, a method of reducing power consumption of a random access memory device includes receiving a required address for a memory array, the memory array comprising individual memory cells arranged in rows and columns, each A memory cell has an access device associated therewith; each column of the array further includes a plurality of N-character lines associated therewith, wherein N corresponds to a number of independently accessible partitions of the array, wherein in a given column Each access device is only coupled to one of the N-character lines of the column, and is determined by a required column identified by a plurality of column address bits included in the required address, in the request column Which of the N partitions are to be accessed; and one or more of the N character lines of the request column are activated to initiate only one or more of the N partitions to be accessed. The access devices are activated, wherein no access device corresponding to one or more of the N partitions that are not to be accessed is activated.

In still another embodiment, an arithmetic system includes a processor; a memory controller is executable by the processor, and has a Arranging individual memory cells into a row and column array of random access memory devices, each memory cell having an access device associated therewith; each column of the array further includes a plurality of N-character lines associated therewith, where N Corresponding to a number of independently accessible partitions of the array, wherein each access device in a given column is only coupled to one of the N-character lines of the column; and the bit in communication with the array signal Address decoder logic configured to receive a plurality of column address bits and to determine a required column identified by the column address bits, and which of the N partitions in the required column are to be stored So that the access devices are not activated in a selected column but not within a partition to be accessed.

The problems discussed above or the absence of the foregoing may be overcome or overcome in the exemplary embodiments, wherein a design structure embodied in a machine readable medium embodied in a design flow includes a random access memory device. Included in that it includes an array of individual memory cells arranged in rows and columns, each memory cell having one access device associated therewith; each column of the array further includes a plurality of N-character lines associated therewith, wherein N corresponds to the array independent a number of addressable partitions, wherein each access device in a given column is only coupled to one of the N-character lines of the column; and address decoder logic for communicating with the array signal, configured The method is configured to receive a plurality of column address bits, and determine, according to a required column identified by the column address bits, which of the N partitions in the required column are to be accessed, so that the A plurality of access devices are selected within the column but not within a partition to be accessed.

The above and other objects, features and advantages of the present invention will be More particularly preferred embodiments are to be understood and described in conjunction with the accompanying drawings.

What is disclosed herein is a design structure that implements power savings during addressing of a DRAM device. In short, the DRAM array is divided into multiple partitions by each complex digital meta-line, without the need to use all the address (or page depth) space associated with the traditional server architecture. For applications, power can be saved. In addition, reducing power consumption does not mean that there is a need to reduce the available memory space. Conversely, all addresses are still valid and can maintain data in self-updating operations, while in power saving mode, access is available at the same time. The number of partitions will be reduced. In order to individually address a particular column partition, support control logic is used to individually decode, select, and address each partition. As will be explained in more detail below, the support control logic can be integrated into a separate memory controller as separate logic or embedded in the DRAM.

Referring to the second figure, there is shown another schematic diagram of an existing DRAM architecture 100 illustrating a conventional row-select operation. When the row address strobe (RAS) signal is active, the address represented by a set of column address bits A[0:n] is translated into a column position within the array. When the array demultiplexer ""Row Demux"" (row demultiplexer circuitry) 114 is decoded, each access transistor of the selected column is turned "on" (becoming the most power-consuming part of the operation). Next, select the desired row. When the row address strobe (CAS) signal is active, the address represented by a set of row address bits A[n:m] passes through the row selector circuit 116. The translation is done in a row within the array, and the data is read out to the data line D[0:x].

As indicated above, even though the full width of the array is not required to be accessed, in a conventional column architecture, the entire array of access devices will still be in an operational state. Therefore, in accordance with an embodiment of the present invention, a DRAM architecture has an array having the ability to access only a portion of the DRAM wafer's address as long as the architecture does not require the use of a larger data set. For example, by splitting the column access command (which uses most of the operating power when addressing the DRAM), the device allows access to only 1/2 of the column partitions that are accessed under the current architecture (for example). This saves 1/2 of the column access power during operation. However, the present invention may also implement further partial partitioning (e.g., 1/3, 1/4, 1/5, etc.).

The third figure shows a schematic diagram of a DRAM architecture 300 for implementing column partitioning in accordance with an embodiment of the present invention. As will be explained below, each column of the array includes a pair of word lines (column select lines) 302A, 302B that effectively divide the array into a pair of column partitions A, B, on either side of dashed line 304. Here, as described in the simple example, there are two partitions, so each column has two word lines, and the leftmost row of memory cells of the array is coupled to the associated one word line 302A, and the rightmost row of the array The memory cell is coupled to an associated word line 302B. For N partitions, N can be a different number, and each column will have n word lines. It should be further appreciated that the number of memory cells in a given column is not necessarily the same in all N partitions. For example, in a 256-line device, partition A may include a coupling to word line 302A. 192 memory cells, and partition B may include 64 memory cells remaining coupled to word line 302B.

In order to be able to independently select one (or both) of a particular column of word lines 302A, 302B, address decoder logic 306 is configured to receive column address bits A[0:n] and decide Which column to start. The address decoder logic 306 uses the map 310 of the array to further determine which one of the column partitions to initiate (e.g., A, B, or both). Based on the number of partitions housed within the array, address decoder logic 306 provides at least one additional signal 308 to column demultiplexer circuit 114, further specifying which partition(s) to boot. In this embodiment, address decoder logic 306 may be included in column demultiplexer circuit 114 on the DRAM, or alternatively, in a separate memory controller (not shown in the third figure). Since the partitioning is implemented, less than the total number of access devices in a column will be activated, while reducing the number of devices in the sense/latch circuitry 112 and the row selector circuit 116, thus achieving the goal of power saving. .

Finally, the fourth figure shows a block diagram of an exemplary computing system for the reduced power DRAM architecture of the third figure. The exemplary computing system 400 includes a processor 402 that can further include a plurality of CPUs (Central Processing Units) 404A, 404B. The processor 402 is coupled to the memory controller 406 by the first bus 408. The memory controller 406 performs, for example, fetch and store operations, maintains cache coherency, and stores the location of the recorded memory page in real memory. In addition, the memory 410 is coupled to the memory controller 406 through the second bus bar 412.

As described in the fourth figure, the memory 410 further includes an operating system 414, memory portion data 416, and User program and data 418. In the exemplary embodiment shown, the memory 410 is comprised of a real memory portion, such as a card containing a memory chip (eg, a DRAM die), or a dual inline memory module (DIMM), or Any other suitable memory unit. For example, an computing system can have a memory 410 of four 128 MB DIMMs. The memory portion data 416 contains information about the real memory portion of the memory 410.

In the exemplary computing system 400, the processor 402 is coupled by a third bus 420 to various I/O devices, such as I/O controller 422, tape controller 424, and network controller 426, but not Limited. The I/O controller 422 is coupled to a hard disk 428 (which may be the entire hard disk subsystem), as well as a CD ROM 430. Other I/O devices, such as DVDs (not shown), can also be used. In the illustrated embodiment, the tape controller 424 is further coupled to the tape unit 432, and in the alternative embodiment may include the entire tape subsystem, with any number of physical tape drives. In addition, the network controller 426 is coupled to a local area network (LAN) 434 and an internet connection 436. It should be appreciated that there are many ways in which the computing system can be configured, and computing system 400 is used by way of example only.

As indicated above, the support control logic 306 in the third figure can be integrated into the memory controller 406 as separate logic or embedded in the memory device 410. For example, the memory controller 406 can be designed to use the work of the address partition by constructing the total possible number of addresses of the partition memory. can. Next, the memory controller 406 can adjust the partitioning function according to individual applications. For applications that require a long page length, the partition will be closed (all word lines in the selected column will be started) and full column access may occur. For applications that do not require large page lengths (more random access), the partitioning function can be turned on to save power during the access process. In the partition state, all data can be accessed normally, and the remaining partitions can be used when needed, but may require a long access time.

The fifth diagram shows a flow chart of a design flow 500. The design flow 500 may vary depending on the type of IC being designed. For example, the design flow 500 for constructing an application specific IC (ASIC) is not the same as the design flow 500 for designing a standard component, and the design structure 510 is preferably The input to a design flow 520 may be provided by an IP provider, a core developer, or other design company, or may be generated by an operator of the design process, or from other sources. Design structure 510 includes a schematic diagram or HDL, a circuit embodiment 300 in the form of a hardware description language (e.g., Verilog, VHDL, C, etc.). Design structure 510 can be included in one or more machine readable mediums. For example, design structure 510 can be a text file or graphical representation of circuit embodiment 500 shown in the third figure. Design flow 520 synthesizes (or translates) circuit embodiment 300 into a netlist 530, such as wiring, transistors, logic gates, control circuitry, I/O, and models, etc. A list, and description of the connections to other components and circuits in the integrated circuit design, recorded on at least one machine readable medium. The design flow may be repeated, where the network connection table 530 is resynthesized one or more times, depending on the design specifications and parameters used in the circuit.

Design flow 520 includes the use of various inputs, such as input from a library element 535 including a set of commonly used components, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing Techniques (eg, different technology nodes, 32 nm, 45 nm, 90 nn, etc.), design specifications 540, characterization data 550, verification data 560, design rules 570, And a test data file 580 including test patterns and other test information. The design flow 520 further includes, for example, a standard circuit design flow such as timing analysis, a verification tool, a design rule checker, and a place and route tool. Those skilled in the art of circuit design should be aware of the scope associated with electronic design automation tools and applications for design process 520 without departing from the spirit and scope of the present invention. The design structure of the inventive embodiments is not limited to any particular design flow.

Design flow 520 preferably translates the embodiment of the invention illustrated in the third figure, as well as any additional integrated circuit design or materials, if applicable, into a second design structure 590. The second design structure 590 is located in the storage medium as a data format for exchanging layout data of the integrated circuit (eg, GDSII (GDS2), GH, OASIS, or any other suitable format for storing such a design structure) Stored information). The second design structure 590 can include information such as test data files, design content files, manufacturing materials, layout parameters, wiring, metal layers, vias, shapes, winding materials, etc., and semiconductor manufacturing. Other information required by the business for the semiconductor manufacturer to produce An embodiment of the invention as shown in the third figure. The second design structure 590 can then proceed to stage 595. For example, the second design structure 590 proceeds to tape-out, delivers production, delivers a photomask factory, sends it to another design company, and returns it to the customer, and the like.

While the invention has been described in terms of the preferred embodiments, it will be understood by those skilled in the art Various modifications may be made without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiment, and the scope of the appended claims is intended to cover all modifications and variations.

DRAM architecture ‧ ‧ 100

Memory ‧‧‧102

Storage capacitor ‧‧‧104

Access transistor ‧‧‧106

Character line ‧‧108

Sensing line ‧‧110

Sense amplifier ‧‧112

Defining multiplexer circuits ‧‧‧114

Row selector circuit ‧‧‧116

DRAM architecture ‧‧300

Word line ‧‧‧302A, 302B

Dotted line ‧‧‧304

Address decoder logic ‧ ‧ 306

Additional signal ‧ ‧ 308

Map ‧ ‧ 310

Demonstration computing system ‧‧400

Processor ‧ ‧ 402

CPU‧‧‧404A, 404B

Memory controller ‧ ‧ 406

First bus ‧ ‧ 408

Memory ‧‧410

Second bus ‧ ‧ 412

Operating system ‧ ‧ 414

Memory part information ‧‧‧416

User program and information ‧ ‧ 418

Third bus ‧ ‧ 420

I/O controller ‧‧ 422

Tape controller ‧‧‧424

Network controller ‧‧‧426

Hard disk ‧ ‧ 428

CD ROM‧‧‧430

Tape unit ‧‧‧432

Regional network ‧ ‧ 434

Internet connection ‧ ‧ 436

Design process ‧‧500

Design structure ‧ ‧ 510

Design process ‧‧‧520

Internet connection table ‧ ‧ 530

Component library component ‧‧ 535

Design specification ‧ ‧ 540

Characteristic information ‧ ‧ 550

Verification information ‧ ‧ 560

Design rules ‧ ‧ 570

Test data file ‧‧‧580

Second design structure ‧‧‧590

In the following exemplary figures, like numerals represent like elements.

The first figure shows a schematic diagram of an exemplary DRAM architecture; the second figure shows another schematic diagram of the DRAM architecture of the first figure, in which the conventional column selection operation is specifically illustrated; An embodiment of the invention, a schematic diagram of a DRAM architecture for implementing column partitioning; a fourth diagram showing a block diagram of an exemplary computing system for a reduced power DRAM architecture of the third diagram; and a fifth diagram showing A flow chart of a demonstration design flow for one of semiconductor design, fabrication, and/or testing.

Claims (28)

A random access memory device comprising: arranging individual memory cells into an array of rows and columns, each memory cell having an access device associated therewith; each column of the array further comprising a plurality of N-shaped lines associated therewith Where N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given column is only coupled to one of the N-character lines of the column; The address decoder logic of the array signal communication, the address decoder logic is configured to receive a plurality of column address bits, and is determined by a request column identified by the column address bits, Which of the N partitions in the request column are to be accessed so as not to activate the access devices in a selected column but not within a partition to be accessed. The memory device of claim 1, wherein the array of the individual memory cells comprises a dynamic random access memory cell. A memory device as claimed in claim 1, wherein the address decoder logic utilizes an array map to determine which of the N partitions in the request column are to be accessed. The memory device of claim 1, wherein the address decoder logic is configured to transmit the plurality of column address bits to a column demultiplexer circuit associated with the word lines (row Demultiplexer), and the address solution The code logic is further configured to communicate at least one additional signal to the column demultiplexer circuit, the at least one additional signal indicating which of the N partitions in the request column are to be accessed. A memory device as in claim 4, wherein the address decoder logic is embedded in circuitry of the array. A memory device as in claim 4, wherein the address decoder logic is located in a discrete memory controller associated with the array. A method of reducing power consumption of a random access memory device, the method comprising: receiving a required address for a memory array, the memory array comprising individual memory cells arranged in rows and columns, each memory cell Having one access device associated therewith; each column of the array further includes a plurality of N-character lines associated therewith, wherein N corresponds to a number of independently accessible partitions of the array, wherein each of the given columns An access device is coupled to only one of the N-character lines of the column; and determining a request column to be identified by a plurality of column address bits included in the required address, Which of the N partitions in the column are to be accessed; and one or more of the N-character lines of the required column are activated to initiate only the N partitions corresponding to the N partitions to be accessed. One or more of the access devices, wherein none of the N corresponding to the N that are not accessed are activated One or more of the access devices of the partition. The method of claim 7, wherein determining which of the N partitions in the request column are to be accessed by an address decoder logic that communicates with the array signal, and the address decoder logic The configuration is configured to receive a plurality of column address bits. The method of claim 7, wherein the array of the individual memory cells comprises a dynamic random access memory cell. The method of claim 8, wherein the address decoder logic utilizes an array map to determine which of the N partitions in the required column are to be accessed. The method of claim 8, wherein the address decoder logic is configured to transmit the plurality of column address bits to a column demultiplexer circuit associated with the word lines, and wherein The address decoder logic is further configured to communicate at least one additional signal to the column demultiplexer circuit, the at least one additional signal indicating which of the N partitions in the request column are to be accessed. The method of claim 8, wherein the address decoder logic is embedded in the circuitry of the array. For example, the method of claim 8 of the patent scope, wherein the address decoder logic Located within one of the discrete memory controllers associated with the array. An arithmetic system comprising: a processor; a memory controller executable by the processor, the memory controller and a random access memory device having an array of individual memory cells arranged in rows and columns Communication, each memory cell having an access device associated therewith; each column of the array further includes a plurality of N-character lines associated therewith, wherein N corresponds to a number of independently accessible partitions of the array, wherein Each access device of a given column is coupled to only one of the N-character lines of the column; and the address decoder logic is in communication with the array signal, the address decoder logic configured to receive a plurality of column address bits, and for determining a required column identified by the column address bits, which of the N partitions in the request column are to be accessed, so that a selection is not initiated The access devices within the column but not within a partition to be accessed. The system of claim 14, wherein the array of the individual memory cells comprises a dynamic random access memory cell. A system as claimed in claim 14, wherein the address decoder logic utilizes an array map to determine which of the N partitions in the request column are to be accessed. The system of claim 14, wherein the address decoder logic is configured to transmit the plurality of column address bits to a column demultiplexer circuit associated with the word lines, and wherein The address decoder logic is further configured to communicate at least one additional signal to the column demultiplexer circuit, the at least one additional signal indicating which of the N partitions in the request column are to be accessed. The system of claim 17, wherein the address decoder logic is embedded in a circuit of the random access memory device. The system of claim 17, wherein the address decoder logic is located in the memory controller associated with the array. A design structure for use in a machine readable medium of a design flow, the design structure comprising: a random access memory device comprising an array of individual memory cells arranged in rows and columns, each memory cell having an associated One access device; each column of the array further includes a plurality of N-type lines associated therewith, wherein N corresponds to a number of independently accessible partitions of the array, wherein each access in a given column The device is coupled to only one of the N-character lines of the column; and address decoder logic for communicating with the array signal, the address decoder logic configured to receive a plurality of column address bits, And determining, by the request columns identified by the column address bits, which of the N partitions in the request column are to be accessed, so that they are not activated in a selected column but are not to be saved. Score The access devices in the zone. The design structure of claim 20, wherein the array of the individual memory cells comprises a dynamic random access memory cell. The design structure of claim 20, wherein the address decoder logic utilizes an array map to determine which of the N partitions in the required column are to be accessed. The design structure of claim 20, wherein the address decoder logic is configured to transmit the plurality of column address bits to a column demultiplexer circuit associated with the word lines, and wherein The address decoder logic is further configured to communicate at least one additional signal to the column demultiplexer circuit, the at least one additional signal indicating which of the N partitions in the request column are to be accessed. The design structure of claim 23, wherein the address decoder logic is embedded in the circuitry of the array. The design structure of claim 23, wherein the address decoder logic is located in a discrete memory controller associated with the array. The design structure of claim 20, wherein the design structure includes a network connection table describing the random access memory device. For example, the design structure of claim 20, wherein the design structure is located in a storage medium as a data format used for exchanging layout data of the integrated circuit. For example, the design structure of claim 20, wherein the design structure includes at least one of a test data file, a characterization data, a verification data, a programming material, or a design specification.