JPH1173763A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a memory system capable of effectively utilizing cache while having a shared sense amplifier configuration. SOLUTION: A latch type sense amplifier 11 which is shared by neighboring memory banks n, n+1 is installed. Bit lines BLn, BBLn, BL n+1, BBL n+1, are respectively installed with transfer gates 121-124 to control the electric connections with this sense amplifier 11 and the cell array blocks on both sides. To hold the potentials of the connection lines (latch node) of the sense amplifier between the transfer gates 121-124, the sense amplifier section 11 is provided with charge storage memory elements 131-134. The configuration having this shared sense amplifiers is installed between neighboring banks and connected to a arbitrary memory cell column.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a dynamic memory.
In particular, it is applied to a configuration in which the sense amplifier unit is used as a cache.

[0002]

2. Description of the Related Art Generally, when a dynamic memory is used on a certain system, there is locality of data reference. Therefore, using a sense amplifier in a memory as a cache (called a sense amplifier cache) is an average latency (time from data request to transfer).
This is an effective means to reduce.

[0003] That is, a row (row) and a column (column) in a memory cell array are designated according to a certain address input, data access to a memory cell (here, read operation) is performed, and then a row corresponding to the address is assigned. Leave activated. In other words, by keeping the data of the memory cells belonging to the accessed row latched in the respective sense amplifiers, in the subsequent access, when a column access in the row comes, that is, in the case of a cache hit, Data can be immediately transferred to the outside.

[0004] The average latency depends on the architecture of the system in which the memory is implemented and on the percentage of cache hits by applications running on the system. However, since the cache hit rate is generally high due to the locality of data reference, it can be said that the average latency is small.

Separating the inside of the memory into a plurality of memory cell arrays, each of which is independent and equivalent, is divided into equivalent cell array blocks, that is, banks, so that the number of caches that can hold independent row data and can be accessed independently. Will increase. This improves the cache hit ratio and is effective in reducing the average latency.

The multi-bank operation is performed by interleaving between banks, that is, by performing row access in another bank while data transfer is being performed in one bank, thereby continuing to output data even during row access. Therefore, data transfer efficiency can be improved.

[0007]

When the number of bits is increased to increase the data transfer speed and the number of banks is increased to reduce the average latency, the sense amplifier is shared between the banks. There is a need. Otherwise, the chip area will increase significantly, and the resulting increase in cost will be a serious problem.

On the other hand, in the case where the sense amplifier is shared between the banks as described above, the independence between the banks is limited. That is, when one of the adjacent banks is activated (selected state), the other cannot be activated.
This is because the sense amplifier can latch only one data of an adjacent bank.

For example, with respect to alternate access between adjacent banks sharing a sense amplifier, the same situation occurs when the sense amplifier accesses a row different from the row data stored as a cache. Cannot be used as a cache. In such a case, the sense operation must be performed again after precharging the sense amplifier and the bit line.

Therefore, in the memory system constituting the shared sense amplifier, the efficiency of using the sense amplifier as a cache is reduced, and it is difficult to reduce the average latency.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor integrated circuit device having a memory system which can effectively use a cache while having a shared sense amplifier configuration, and reduce an average latency. The object of the present invention is to provide a semiconductor integrated circuit device having a memory system.

[0012]

A semiconductor integrated circuit device according to the present invention is shared by a plurality of cell array blocks in each of which a plurality of memory cells are arranged in a matrix, and adjacent ones of the cell array blocks. A latch type sense amplifier, a transfer control element for controlling an electrical connection between the sense amplifier and the cell array blocks on both sides thereof, and a storage unit for holding a potential of a connection line of the sense amplifier between the transfer control elements And characterized in that:

In the storage section, information of a memory cell is copied and used as a cache. Then, when the transfer control element is inactive, data is read from the storage unit via the operation of the sense amplifier.

According to the present invention, an independent cache is provided for each cell array block even in a shared sense amplifier configuration. Further, such a storage unit can be effectively used as a cache even in a sense amplifier having no shared sense amplifier configuration. By providing such a storage unit in the sense amplifier, the use efficiency of the cache is improved and the average latency is reduced.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the periphery of a sense amplifier in a memory core in a semiconductor integrated circuit device showing a typical basic configuration of the present invention. The latch type sense amplifier 11 is arranged between adjacent cell array blocks, that is, between banks n and n + 1. Also,
The sense amplifier 11 is configured to latch the potential relationship of any complementary column line (bit line) of the bank n or n + 1. That is, the bit line B for the bank n
Sense and latch of complementary potentials of Ln and BBLn, bit lines BLn + 1 and BBLn + 1 for bank n + 1
Is a shared sense amplifier that senses and latches a complementary potential of

Each of the bit lines has the sense amplifier 1
1 and an isolation control signal ISO (ISOn, I
Transfer gates 121 to 124 that are gate-controlled by (SOn + 1) are provided. Furthermore, in order to hold the potential of the connection line of the sense amplifier between the transfer gates 121 to 124, that is, the potential of the latch node, the charge storage type storage elements 131 to 1 are stored in the sense amplifier unit.
34. A configuration having such a shared sense amplifier is provided between adjacent banks, and is connected to an arbitrary column of memory cells. The charge storage type storage element has a relatively small occupation area and is suitable for being provided in the sense amplifier portion.

According to the structure of the present invention, for example, data of a plurality of memory cells connected to a certain word line (row) is transferred from one of the banks n in which the transfer gates 121 and 122 are activated to each sense amplifier 11. When the data is sense-amplified, the data is temporarily stored in the storage elements 131 and 132. Next, instead, the other bank n + 1 is activated, and thereafter, when an arbitrary memory cell of one bank n connected to the same word line as described above is read again (cache hit), the transfer gate By deactivating 121 to 124, the bank n and the sense amplifier 11 are separated from each other, and data is read from the storage elements 131 and 132 to the sense amplifier 11 at high speed. The same applies when the other bank n + 1 is accessed. For example, data of a plurality of memory cells connected to a certain word line of the bank n + 1 are sense-amplified by each sense amplifier 11 and the data at this time is stored in the storage element 13.
3, 134 as a cache temporarily.
If a cache hit occurs in the next access, the bank and the sense amplifier are separated in the same manner as described above, and the storage element (13
3, 134), data can be read from each sense amplifier 11 at high speed.

The storage element 131 is provided in the sense amplifier 11 part.
134 are formed, the data sensing operation from these storage elements to the sense amplifier 11 is not affected by the capacitance equivalently connected to the bit line. Therefore, it is much faster than a normal sense amplifier operation. That is, with this configuration, a cache hit can be used between banks while having a shared sense amplifier configuration between banks.

FIG. 2 is a circuit diagram showing the periphery of the sense amplifier of the memory core in the semiconductor integrated circuit device according to the first embodiment of the present invention. This shows a specific configuration example of a main part of the configuration shown in FIG.
1 shows one configuration of a latch type sense amplifier 11 shared with respect to 1. The same parts as those in FIG. 1 are denoted by the same reference numerals.

The sense amplifier 11 is connected to a bank n or n +
1 arbitrary column line (bit line) BLn or BLn + 1
And the complementary potential relationship of BBLn or BBLn + 1 is latched. For convenience, a line connected to bit line BLn or BLn + 1 is connected to sense line S
An and a wiring connected to the bit line BBLn or BBLn + 1 are referred to as a sense line BSAn.

The sense amplifier 11 includes a P-channel MOS transistor 11 to which a control signal SAP is supplied to a source.
Drains of the sense lines BSAn and S
An. The gate of the transistor 111 is connected to the sense line SAn, and the gate of the transistor 112 is connected to the sense line BSAn. Also, the control signal / SA
The drains of the N-channel MOS transistors 113 and 114 to which N (the leading / is indicated by an upper bar in the drawing) are connected to the sense lines BSAn and SAn, respectively. The gate of the transistor 113 is connected to the sense line SA.
n, the gate of the transistor 114 is connected to the sense line BSAn
It is connected to the. The control signal SAP is, when enabled, a high-potential power supply of the sense amplifier and a control signal / SAN.
Are set to the low potential power supply (ground potential) of the sense amplifier when enabled. Also, control signals SAP, / SAN
Is set to an intermediate potential so as not to exceed the threshold voltage of each of the transistors 111 to 114 when inactive.

Sense line BSAn is electrically connected to global data line BDQ (a signal line complementary to DQ) via a current path of N-channel MOS transistor 117. The sense line SAn is connected to the global data line D
It is electrically connected to Q via the current path of N-channel MOS transistor 118. These transistors 11
The column selection signal CSL is supplied to the gates 7 and 118.

The charge storage type storage elements 131 to 134
Like the memory cells MC in the bank, the memory cell MC includes a capacitor C for charge storage, a gate transistor (N-channel MOS transistor) Tr, and a capacitor C. That is, the storage elements 131 to 134 are formed in the same manufacturing process as the memory cell MC.

Temporary storage element (cache) on bank n
The drain of the transistor Tr of the storage element 131 is connected to the sense line BSAn, and the drain of the transistor Tr of the storage element 132 is connected to the sense line SAn. The drain of the transistor Tr of the storage element 133 which functions as a cache on the bank n + 1 side is a sense line B
The drain of the transistor Tr of the storage element 134 is connected to the sense line SAn.

That is, the storage elements 131 and 132 serving as caches on the bank n side store sense data complementary to each other. That is, a cache cell CCLn that stores one bit is configured by using a pair of the storage elements 131 and 132 as one unit. Therefore, the storage element 1
The gates of both transistors 31 and 132 are controlled by a cache word line CWLn. Similarly, storage elements 133 and 134 serving as caches on the bank n + 1 side
Store sense data complementary to each other. That is,
A cache cell CCLn + 1 that stores one bit is configured by using a pair of the storage elements 133 and 134 as one unit. For this reason, the gates of both the storage elements 133 and 134 are connected to the cache word line CWLn +
1 is controlled.

The transfer gate 121 is connected to the sense line B
A current path is formed between SAn and bit line BBL, and transfer gate 122 forms a current path between sense line SAn and bit line BL. Gates of both transfer gates 121 and 122 are controlled by an isolation control signal ISOn, so that cache cell CCLn and memory cell MC
Is electrically connected / disconnected to and from the bank n in which these are arranged.

Transfer gate 123 forms a current path between sense line BSAn and bit line BBL + 1, and transfer gate 124 forms sense line SAn.
And a bit line BLn + 1 to form a current path. Both transfer gates 123 and 124 output the separation control signal I
The gate is controlled by SOn + 1 and the cache cell CC
Electrical connection / separation control is performed between Ln + 1 and the bank n + 1 in which the memory cells MC are arranged.

The memory cell (MC) is conveniently stored in bank n
And any l-th row of the word lines WLn
The cells connected to the illustrated column belonging to the third row are representatively shown. Also, the word line W in the bank n + 1
A cell connected to an illustrated column belonging to an arbitrary l-th row of Ln + 1 and an m-th row is representatively shown.

FIG. 3 is a waveform diagram showing an example of the circuit operation of FIG. The precharge prech in the figure is the precharge potential of the bit line, and is an intermediate potential lower than the high potential level for bit line sensing and higher than the low potential level. Although not shown, it is not essential to the present invention. For example, in FIG.
A supply source is provided at the end of +1 and BBL + 1.

First, an access (here, a read operation) to the row 1 of the bank n occurs (31 in FIG. 3). Here, it is assumed that this access is the first access to the row 1 of the bank n, or that data from a previous access is not stored as a cache. When the word line WLn, l of the bank n rises and the isolation control signal ISOn rises, the bit line of the bank n and the sense amplifier 11 are connected. At this time, the signal ISOn + 1
Maintain the GND level, and the bit line (B
Ln + 1, BBLn + 1) and the sense amplifier 11 are separated.

When the electric charge of the memory cell connected to the word line WLn, 1 appears as a potential difference between the bit line pair BL, BBL, the sense amplifier 11 is activated, and the potential difference is sufficiently amplified. It can be carried out.
That is, the transistors 117 and 118 are turned on by the selection signal CSL of the designated column, and the sense amplifier 11
Is transmitted to global data lines DQ and BDQ (operation of data transfer system).

Thereafter, when accessing the next bank n + 1, the operation must be shifted to the bank n + 1 after the data is stored in the cell by lowering WLn, l. This procedure is the same as that of the prior art. However, in the present invention, before the precharge of the bit line pair and the sense amplifier in the next access is started, the cache word line CWLn provided in the sense amplifier unit is connected. And the latch data is stored in the cache cell CCLn (3
2).

Normally, in the dynamic memory cell (MC), in order to prevent the restoration of sufficient charge due to the threshold voltage drop of the gate transistor (Tr), the word line is raised to a high level higher than the power supply potential. Use potential. However, the cache cell CCLn according to the present invention uses the two storage elements 131 and 132 in a complementary manner so that the high level of the word line for caching can be sufficiently cached even when a power supply potential lower than the boosted potential is used. It can be stored in cells. That is, the cache cell C is generated by the signal CWLn.
When CLn is operated, a complementary potential difference based on the latch data of the sense amplifier is applied to the two storage elements 131 and 13.
2 is stored. Cache cell CCLn +
The same is true of the first embodiment. By using the two storage elements 133 and 134 in a complementary manner, a sufficient charge can be stored in the cache cell even when the high level (CWLn + 1) of the cache word line is used at a power supply potential lower than the boosted potential. And sense amplification can be easily performed by storing data having a complementary potential difference.

In the subsequent access (33) to bank n + 1, row m, it is assumed that the data of the first access to row m of bank n + 1 or the previous access has not been stored as a cache. This is performed in exactly the same manner as the access to the previous bank n, and before the precharge, the word line CWLn + 1 for the cache is activated,
Data is stored in cache cell CCLn + 1 (3
4). This cache cell CCLn + 1 also has
By using the two storage elements 133 and 134 complementarily, the high level (CWL) of the word line for the cache is used.
Even if a power supply potential equal to or lower than (n + 1) is used, a sufficient charge can be stored in the cache cell.

If it is assumed that bank n and row 1 are accessed again, ISOn and ISOn + 1 are changed to GN
D and the bit lines (BLn, BBLn, BLn + 1,
(BBLn + 1) and the sense lines (SAn, BSAn) are electrically separated, and the signal CWLn is raised (3
5) The data stored in the cache cell CCLn is amplified by the sense amplifier 11. As described above, since this sensing operation is not affected by the capacitance equivalently connected to the bit line, it is much faster than a normal sense amplifier operation.
Further, since it is not necessary to use the boosted potential for the high level of the cache word line CWLn, a short rise time is also one factor that can shorten the access time.

Thereafter, while the data transfer system is operating, the signals ISOn and WLn, l are raised to restore data. The reason why the potential of CCLn is changed before CWLn falls is that a column write occurs at that time,
This indicates that the bit line has been inverted (36).

Further, the bank n + 1 is accessed, and when a cache hit occurs, ISOn, ISOn + 1
While the bit line and the sense line are electrically separated while maintaining the potential at GND, the signal CWLn + 1 rises (37), and the data stored in the cache cell CCLn + 1 is sensed by the sense amplifier 1.
Amplify by 1. If it is not a cache hit, reading from a normal memory cell, that is, ISOn + 1 rises, and the bit line precharge potential
When a potential difference between the data stored in the memory cell (MC) connected to one of the bit lines Ln + 1 and BBLn + 1 appears, the sense amplifier 11 is operated to latch the data. If the subsequent access is not the bank n + 1, the data may be kept latched in the sense amplifier, or may be precharged every time regardless of the access.

As described above, the cache cell (CCLn or CCLn + 1) has a configuration in which one bit is stored using two storage elements in a complementary manner, so that the high level (CWLn or CWLn) of the word line for the cache is used. Even if a power supply potential equal to or lower than the boosted potential is used for CWLn + 1), sufficient charge can be stored in the cache cell. The sense operation of the cache cell is much faster than a normal sense amplifier operation because there is no influence of the capacitance equivalently connected to the bit line. Further, since it is not necessary to use the boosted potential for the high level of the word line for the cache, the rise time is shortened, which contributes to shortening the access time.

FIG. 4 is a circuit diagram showing the periphery of a sense amplifier in a memory core in a semiconductor integrated circuit device according to a second embodiment of the present invention. Has become. Thereby, the efficiency of the cache hit is improved. The other configuration is the same as that of FIG. 2, and the same parts are denoted by the same reference numerals and description thereof will be omitted.

That is, in the configuration example of FIG. 2, the data of the cell for one row is stored as a cache for each bank, but in the configuration example of FIG.
For one bank, cell data for two rows can be stored as a cache. Therefore, in FIG. 4, the cache cells CCLn, 0 and CCLn, 1 on the bank n side and the cache cells CCLn + 1,0, CCLn on the bank n + 1 side are provided per one sense amplifier 11.
+1 and 1 are provided. Each cache cell has the same configuration as that of the cache cell CCLn or CCLn + 1 in FIG.

FIG. 5 is a waveform chart showing an example of the circuit operation of FIG. The precharge prech in the figure is the precharge potential of the bit line, and is an intermediate potential lower than the high potential level for bit line sensing and higher than the low potential level. Although not shown, it is not the essence of the present invention, but in FIG. 4, for example, the ends of bit lines BL and BBL, BL
A supply source is provided at the end of +1 and BBL + 1.

First, row 1 of bank n is accessed (here, read operation) (51 in FIG. 5). Here, it is assumed that this access is the first access to the row 1 of the bank n, or that data from a previous access is not stored as a cache. When the word line WLn, l of the bank n rises and the isolation control signal ISOn rises, the bit line of the bank n and the sense amplifier 11 are connected. At this time, the signal ISOn + 1 is G
While maintaining the ND level, the bit line (BLn +
1, BBLn + 1) and the sense amplifier 11 are separated. Then, in the same procedure as in the first embodiment, banks n,
The data of the row 1 is read out to the sense amplifier 11, and the data is stored in the cache cell CCLn, 0 before the next precharge (52).

Next, the same bank n is accessed but a different row m is accessed (53). In this access, it is assumed that the data of the first access to the row m of the bank n or the previous access is not stored as a cache. Data in bank n and row m is read out to sense amplifier 11 in the same procedure as in the first embodiment, and cache cell CCL is read before the next precharge.
The data is stored in n, 1 (54).

If it is assumed that bank n and row 1 are accessed again, ISOn and ISOn + 1 are transferred to GN
D and the bit lines (BLn, BBLn, BLn + 1,
BBLn + 1) and the sense lines (SAn, BSAn) are electrically separated, and the signal CWLn, 0 rises (5
5) The data stored in the cache cell CCLn, 0 is read by the sense amplifier 11 at high speed.

After the column write to the bank n and the row 1 is performed (56), if the bank n and the row m are accessed again, the bit lines and the sense lines are kept while keeping ISOn and ISOn + 1 at GND. Are electrically separated, the signal CWLn, 1 rises (57), and the data stored in the cache cell CCLn, 1 is read out at high speed by the sense amplifier 11.

As described above, by storing data of a plurality of rows in the same bank in each cache cell as a cache in the sense amplifier, the cache hit rate can be improved. At the time of a cache hit, the sense amplification operation is performed faster from the cache cell corresponding to the cache hit than the sense amplification operation of the normal memory cell, as in the first embodiment. This reduces the average latency. Not limited to the configuration of FIG. 4, the number of cache cells may be further increased so that data of a plurality of rows per bank can be further stored as a cache.

FIGS. 6A to 6C are conceptual diagrams of a memory system configuration to which the present invention is applied, showing a third embodiment of the present invention. FIG. 6A shows a printed circuit board (PCB)
d circuit board) 61 with a memory controller 62 and memory devices 631, 632 arranged, FIG. 6 (b)
Is formed by forming a memory macro (memory circuit) 64 and a memory control logic circuit 65 on one chip (66).

In a system using a sense amplifier cache, high-speed access is possible when a cache hit occurs. However, when a cache hit does not occur, a sense amplifier and a bit line pair must be precharged first, and new row data must be sensed. It is very time-consuming because it must be done. Therefore, it can be said that the average latency depends on the hit rate to the cache. By applying the cache cell configuration of the present application to the memory devices 631 and 632 and the memory macro 64, it is expected that the hit rate to the cache is improved and the average latency is reduced.

The hit ratio to the cache varies depending on the system configuration and the application executed on the system. In an actual computer system, as shown in FIG. 6C, there are many functional units 691 to 695 for executing arbitrary processing and the like, and requests memory resources. Therefore, since many functional units independently access the memory 67 via the memory controller 68, random access is increased and the hit rate is reduced as compared with the case where a single unit accesses the memory.

Assuming that the hit ratio is A, the minimum delay time from row access to column access is tRCD, the latency of the column is tCL, and the time required to precharge the sense amplifier is tPR. The average latency is: A × tCL + (1−A) × (tPR + tRCD + tCL) = tCL + (1−A) × (tPR + tRCD) (1)

Compared with the latency tRCD + tCL of the memory system not using the sense amplifier cache, to obtain a smaller latency, (1-A) × (tPR + tRCD) <tRCD, that is, A> tPR / ( tPR + tRCD) (2)

Using general values, tPR = 30 ns, tRC
Assuming that D = 20 ns, the cache hit rate must be about 60% or more for the sense amplifier cache to function effectively.

On the other hand, if the memory system according to the present invention is used and the accessed row data is stored in the cache cell and the sense amplifier and bit line are precharged, the average latency per access can be reduced by the cache. If the time required to access the cell data is tCH, then A (tCH + tCL) + (1-A) .times. (TRCD + tCL) = tCL + A.times.tCH + (1-A) .times.tRCD (3)

In addition, compared with a system that does not use the cache of the sense amplifier, it is sufficient that A (tCH−tCL) <0. Since tCH is always smaller than tRCD, this inequality always holds, and the latency can be reduced even if it is difficult to reduce the latency in the conventional system. Also, by increasing the number of cache cells,
Independent row data can be held, the number of independently accessible caches can be increased, and the hit rate can be further increased.

In the embodiments of the present invention, the effective use of the cache has been described particularly for a semiconductor integrated circuit device having a memory having a shared sense amplifier configuration, but the sense amplifier is not shared between adjacent memory cell arrays. Providing the cache cells (storage elements 131 to 134) of the present invention is effective also in the sense amplifier. This configuration is shown in FIG. 7 as a fourth embodiment. The sense amplifier 111 is, for example, a signal CWL in FIG.
The circuit configuration excludes the configuration of the cache cell CCLn + 1 controlled by n + 1, the configuration of both transfer gates 123 and 124 controlled by the signal ISOn + 1, and the memory cell configuration of the bank n + 1. Also, the sense amplifier 1
Reference numeral 12 denotes a circuit configuration excluding, for example, the configuration of the cache cell CCLn controlled by the signal CWLn, the configuration of both the transfer gates 121 and 122 controlled by the signal ISOn, and the memory cell configuration of the bank n in FIG. Become. Of course, as shown in FIG. 4, each cache cell may be further increased.

As described above, according to the configuration of FIG. 7, as in the other embodiments, the number of caches that can hold independent row data and can be accessed independently increases, so that the cache hit rate is improved. Thus, the average latency can be reduced.

The layout of the sense amplifier in each of the above embodiments is, for example, a layout in which all the sense amplifiers connected to each bit line are arranged between two cell array blocks, or between two cell array blocks. Is a layout in which only a sense amplifier connected to an arbitrary one of the bit lines is arranged. In the latter case, the sense amplifiers connected to the remaining bit lines are laid out from the area between the two cell array blocks to the area opposite to any one of the cell array blocks. As an example, there is a configuration in which sense amplifiers sequentially connected to bit lines are alternately arranged in regions on both sides of a cell array block.

The storage elements 131 to 134 constituting the cache cell of the present invention are formed in the same manufacturing process as that of the memory cell. However, the present invention is not limited to this. Alternatively, a charge storage type storage element (131-134) may be formed by forming a transistor and a parallel plate capacitor connected to the transistor.

[0059]

As described above, according to the present invention,
Information in a memory cell is copied by a storage element provided in the sense amplifier unit and used as a cache. Thus, even with a shared sense amplifier configuration, an independent cache is provided for each cell array block. In addition, the cache can be effectively used without using the shared sense amplifier configuration. As a result, a semiconductor integrated circuit device having a memory system for reducing the average latency can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the periphery of a sense amplifier in a memory core unit in a semiconductor integrated circuit device showing a basic configuration of the present invention.

FIG. 2 is a circuit diagram showing the periphery of a sense amplifier in a memory core unit in the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a waveform chart showing an example of the circuit operation of FIG. 2;

FIG. 4 is a circuit diagram showing the periphery of a sense amplifier of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a waveform chart showing an example of the circuit operation of FIG.

FIGS. 6A to 6C are conceptual diagrams of a memory system configuration according to a third embodiment of the present invention, to which the present invention is applied;

FIG. 7 is a block diagram showing the periphery of a sense amplifier in a memory core unit in a semiconductor integrated circuit device according to a fourth embodiment of the present invention;

[Explanation of symbols]

 n, n + 1... memory banks (cell array blocks) 11. sense amplifiers 121 to 124 transfer gates 131 to 134... charge storage type storage elements

Claims (10)

[Claims] 1. A plurality of cell array blocks in each of which a plurality of memory cells are arranged in a matrix, a latch-type sense amplifier shared by adjacent blocks among the cell array blocks, the sense amplifier and both sides thereof A semiconductor integrated circuit device, comprising: a transfer control element for controlling an electrical connection with each of the cell array blocks; and a storage unit for holding a potential of a connection line of the sense amplifier between the transfer control elements. . 2. A latch type sense amplifier having a plurality of cell array blocks in each of which a plurality of memory cells are arranged in a matrix, a latch type sense amplifier having a connection line to an adjacent one of the cell array blocks, and A transfer control element for controlling electrical connection to the cell array block by the connection line; and a storage unit for holding a potential of the connection line on the sense amplifier side of the transfer control element. Semiconductor integrated circuit device. 3. The latch section stores the latched data when data of a predetermined memory cell is latched in the sense amplifier, and deactivates the transfer control element when reading the data of the predetermined memory cell again. 3. The semiconductor integrated circuit device according to claim 1, wherein data is read out from said storage unit through the operation of said sense amplifier. 4. The semiconductor integrated circuit device according to claim 1, wherein the storage section includes a charge storage type storage element formed in the same manufacturing process as the memory cell. 5. The charge storage type memory device according to claim 1, wherein the storage unit includes a transistor for controlling transmission of a signal of the connection line formed in a different manufacturing process from the memory cell, and a parallel plate capacitor connected to the transistor. 3. The semiconductor integrated circuit device according to claim 1, further comprising a storage element. 6. The storage element, wherein one unit is configured as a pair to store complementary sense information of the sense amplifier, and stores one bit of information. The semiconductor integrated circuit device according to claim 4. 7. The semiconductor device according to claim 6, wherein a plurality of units of said storage elements are provided for the same column of one cell array block, respectively, and store information of memory cells belonging to different rows. Integrated circuit device. 8. An LSI board on which at least one memory device and a memory controller are mounted, wherein the memory device includes the configuration of the cell array block, the sense amplifier, the transfer control element, and the storage unit. The semiconductor integrated circuit device according to claim 1. 9. An LSI chip comprising a memory circuit and a memory control logic circuit mounted on one chip,
8. The semiconductor integrated circuit device according to claim 1, wherein the memory circuit includes a configuration of the cell array block, a sense amplifier, a transfer control element, and a storage unit. 10. A system comprising one or more memory units, a memory controller, and a plurality of functional units for executing arbitrary processing, wherein the memory unit includes the cell array block, a sense amplifier, a transfer control element, The semiconductor integrated circuit device according to claim 1, further comprising a configuration of a storage unit.