KR100222574B1 - Address buffer circuit - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to an address buffer circuit of a semiconductor memory device having a storage means capable of storing a predetermined address. The present invention relates to receiving a page address and a first control signal from an external device. An input unit configured to output the page address in response to the first control signal; An output unit which stores and outputs the page address output from the input unit; And a storage unit configured to receive and store the page address stored in the output unit in response to a second control signal applied from the outside, and output the stored page address to the output unit in response to a third control signal applied from the outside. .

Description

Address buffer circuit of semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to an address buffer circuit of a semiconductor memory device having a page address storage means capable of storing a predetermined page address.

In the case of erasing data on a page-by-page basis in relation to a flash memory device among semiconductor memory devices, the time required for the erasing operation usually requires several msec. The cell array for storing data in the flash memory device is composed of a plurality of strings composed of a plurality of cell transistors. Each cell transistor of the strings is commonly connected to a corresponding word line and a cell transistor of each string is commonly connected to each word line. The erase operation for the predetermined page is stopped when the data stored in the cell transistors of a page other than the predetermined page, that is, another page other than the erased page, is read out according to a user's need during the erase operation for the predetermined page. And a page address for reading data of a page desired by the user. After the data read is performed, in order to perform the erase operation on the predetermined page again, the page address applied during the erase operation on the predetermined page must be re-applied. To this end, a means for storing the page address is required when the erase operation is stopped.

In a conventional semiconductor memory device, particularly a flash memory device, when a plurality of pages are bundled and erased in block units, a method of storing predetermined block address information in a row decoder is used. That is, during the data erase operation for the predetermined block, the address for the predetermined block is stored in the row decoder at the initial block erasure. During the block erase operation, when a data for another block that does not belong to the predetermined block is to be read, a suspend command is applied from the outside to stop the erase operation for the predetermined block. Subsequently, after performing data reading by applying the address for reading the data, a resume command is applied from outside to resume the erase operation for the predetermined block. When the resume command is applied, the predetermined block address stored in the row decoder is reapplied internally to the semiconductor device, thereby performing an erase operation on the predetermined block.

However, according to the above-described conventional semiconductor memory device, an apparatus capable of storing more addresses in a row decoder than a block erase is required for a page erase having a relatively small amount of data to be erased compared to a block erase. That is, assuming that there are n page addresses (where n is a positive integer), 2 ⁿ address storage devices are required for the row decoder in a conventional semiconductor memory device, and the layout area increases accordingly, resulting in high integration. There is a problem that is difficult to realize.

Accordingly, it is an object of the present invention to provide an address buffer circuit for a semiconductor memory device having a page address storage means capable of storing a predetermined page address.

1 is a block diagram showing a configuration of an address buffer circuit of a semiconductor memory device according to the present invention;

2 is an operation timing diagram according to the present invention;

* Explanation of symbols on the main parts of the drawings

10: input means 20: blocking means

40: first storage means 50: output means

70: first control means 80: second storage means

90: second control means

According to an aspect of the present invention for achieving the above object, the input means for receiving a page address applied from the outside; Blocking means for receiving the page address output from the input means, outputting the page address in response to a first control signal applied from the outside, and blocking the application of another address from the outside; First storage means for storing the page address output from the blocking means; First control means for receiving the page address output from the first storage means, outputting the page address in response to a second control signal applied from the outside, and blocking output of another address; Second storage means for storing the page address output from the first control means; Second control means for receiving the page address output from the second storage means and outputting the page address to the first storage means in response to a third control signal applied from the outside; Output means for outputting the page address stored in the first storage means.

According to another aspect of the invention, the input unit for receiving the page address and the first control signal applied from the outside, and outputs the page address in response to the first control signal; An output unit which stores and outputs the page address output from the input unit; And a storage unit configured to receive and store the page address stored in the output unit in response to a second control signal applied from the outside, and output the stored page address to the output unit in response to a third control signal applied from the outside. .

In a preferred embodiment of this circuit, the input unit comprises: input means for receiving the page address; And a blocking means for receiving the page address output from the input means, outputting the page address in response to the first control signal, and blocking the application of another address from the outside.

In a preferred embodiment of this circuit, the input means comprises one of a NAND gate and a NOR gate.

In a preferred embodiment of this circuit, the blocking means consists of PMOS transistors, NMOS transistors, and an inverter.

In a preferred embodiment of this circuit, the output unit comprises: first storage means for storing the page address output from the blocking means; And output means for outputting the page address stored in the first storage means.

In a preferred embodiment of this circuit, the first storage means consists of inverters.

In a preferred embodiment of this circuit, the output means consists of inverters.

In a preferred embodiment of this circuit, the storage section receives the page address output from the first storage means, outputs the page address in response to the second control signal, and blocks the output of another address. First control means; Second storage means for storing the page address output from the first control means; And second control means for receiving the page address stored in the second storage means and outputting the page address to the first storage means in response to the third control signal.

In a preferred embodiment of this circuit, the first control means consists of a transfer gate consisting of MOS transistors and an inverter.

In a preferred embodiment of this circuit, the second storage means consists of inverters.

In a preferred embodiment of this circuit, the second control means consists of inverters, NAND gates, PMOS transistors, and NMOS transistors.

By such a circuit, by providing storage means for storing page addresses in the address buffer circuit, it is possible to realize high integration of the semiconductor memory device by drastically reducing the layout area occupied by the storage means as compared with the prior art.

Hereinafter, a reference drawing according to an embodiment of the present invention will be described in detail with reference to FIGS.

When performing a predetermined command, for example, an erase command, applied to the semiconductor memory device, the operation for the erase command is stopped for another purpose before the operation for the erase command is completed, and another command, For example, there is a case of operating by receiving a read command. In this case, since the operation on the erase command must be performed after the operation on the read command is completed, an address related to the read command is needed again. To this end, the address for the erase command is stored in the page address storage means 80 of the address buffer circuit, and re-applied in the semiconductor memory device after the operation of the read command is completed.

In particular, if a flash memory device stops an erase operation by applying a suspend command when a page is erased, reads data of a desired page, and then resumes the erase operation, a page address storage means for storing the page address may be provided. need. In the novel semiconductor memory device of the present invention, as shown in FIG. 2, the page address storage means 80 is implemented in an address buffer circuit and controlled by external control signals (blocking_pls, erase_pls, resume_pls). As a result, the layout area can be reduced and the degree of integration of the semiconductor memory device can be improved as compared with the case where the page address storage means is provided in the conventional row decoder. In addition, in the case of all the semiconductor memory devices performing the erase operation in units of pages, the degree of integration may be improved by using the address buffer circuit of the semiconductor memory device according to the present invention.

1 is a block diagram showing a configuration of an address buffer circuit of a semiconductor memory device according to a preferred embodiment of the present invention.

The address buffer circuit of the semiconductor memory device shown in FIG. 1 includes an input unit 30, an output unit 60, and a storage unit 100. The input unit 30 transmits a page address (Address A) for a predetermined page applied from the outside to the output unit 60, and then controls the control signal (blocking_pls) applied from the outside to block another address applied from the outside. In response to). In addition, the input unit 30 is composed of an input means 10 and a blocking means 20, the input means 10 may be provided with any one of the NAND gate (G1) and the NOR gate and the preferred embodiment of the present invention In the example, the NAND gate G1 is configured. The blocking means 20 includes PMOS transistors M1 and M2, NMOS transistors M3 and M4, and an inverter I1. The control signal blocking_pls is transitioned from a low level to a high level for a predetermined period when the page address Address A is applied from the outside, thereby the NMOS transistor M4 and the PMOS transistor M1. Activate each to transmit the page address (Address A) to the output unit (60).

In addition, the control signal blocking_pls applied to the blocking means 20 is maintained at a low level in a section in which the page address Address A is not applied, so that another address from the outside is output to the output unit 60. Will be blocked). In addition, the output unit 60 outputs the page address Address A transmitted from the input unit 30 so that the semiconductor memory device performs an erase operation on the page address Address A. FIG. The output unit 60 is composed of first storage means 40 and output means 50 composed of inverters I2, I3, I4, I5, respectively. The storage unit 100 receives and stores the page address (Address A) stored in the first storage unit 40 of the output unit 60 in response to a control signal (erase_pls) applied from the outside. The stored page address Address A is transmitted to the first storage means 40 of the output unit 60 in response to another control signal (resume_pls) applied from the outside.

The storage unit 100 includes a transmission gate T1 composed of NMOS and PMOS transistors, first control means 70 composed of an inverter I6, and second storage means composed of inverters I7, I8. 80, and second control means 90 composed of inverters I9 and I10, NAND gates G2 and G3, and MOS transistors M5 and M6. That is, a page address (Address A) for a predetermined page is stored in the first storage means 40 in response to the control signal erase_pls, and data is read for another page while an erase operation is performed on the predetermined page. If desired, the erase operation is stopped and data read is performed. After the read operation is completed, the first storage means 40 of the output unit 60 returns the page address Address A stored in the second storage means 90 in response to the control signal resume_pls. The transfer operation is resumed for the predetermined page.

2 is an operation timing diagram according to the present invention. 1 to 2, the operation of the address buffer circuit of the semiconductor memory device according to the preferred embodiment of the present invention will be described.

In order to erase data stored in the cell transistors of a predetermined page of the semiconductor memory device, as shown in FIG. 2, the page address Address A for the page from the outside is input through the NAND gate G1 of FIG. 1. 30 is applied. At this time, the first control signal blocking_pls transitions from a low level to a high level for a predetermined period, and accordingly, the blocking means 20 is enabled and output from the NAND gate G1. The page address (Address A) is transmitted to the first storage means (40). When the first control signal blocking_pls applied to the blocking means 20 transitions back to a low level, the first storage means 40 floats an output terminal of the blocking means 20 so that a standby current is generated. In addition to preventing (stand-by current) from occurring, it serves to store the page address (Address A).

When the page erase signal page_erase applied together with the page address Address A transitions from a low level to a high level, the control signal erase_pls synchronized with the page address transitions to a high level for a predetermined period of time. Accordingly, the current path of the transmission gate T1 of the first control means 70 is turned on so that the page address Address A stored in the first storage means 40 is transferred to the second storage means 80. The page address (Address A) for a predetermined page is stored in the second storage means (80). The output means 50 outputs the page address Address A stored in the first storage means 40 so that a page erase operation corresponding to the page address Address A is performed.

Next, when it is necessary to read data of a page different from the page while the erase operation is performed on the predetermined page, although not shown in FIG. 2, the erase of the predetermined page is performed by applying a suspend command from the outside. The operation is stopped. The page address Address B for the data to be read is again applied through the NAND gate G1. As described above, the first control signal blocking_pls transitions from a low level to a high level for a predetermined time, so that the page address Address B is transmitted to the first storage means 40, and the output means 50 is transmitted. Is output via Thus, after the page read operation is performed on the data to be read, a control signal (resume_pls) for resuming the erase operation is applied from the outside to perform the erase operation on the predetermined page again.

For this purpose, as shown in FIG. 2, as the control signal (resume_pls) transitions from the low level to the high level for a predetermined period, the second control means 90 is enabled to enable the second storage means 80. The page address (Address A) for the predetermined page stored in the) is transferred to the first storage means (40). The output means 50 continues to perform an erase operation by outputting a page address (Address A) for the predetermined page transferred to the first storage means (40). In addition, assuming that there are n page addresses (Address A), in the related art, 2 ⁿ address storage means are required for the row decoder, thereby increasing the layout area. On the other hand, according to the address buffer circuit according to the present invention, since the same function can be performed only by the storage means 40 and 80 for storing n page addresses in the address buffer circuit, the layout area is significantly reduced. High integration can be realized.

As described above, when data of a page different from the predetermined page is to be read during the erasing operation for the predetermined page, the page address for the predetermined page is stored in the storage means of the address buffer circuit. Thereafter, after the data reading for the other page is completed, the erase operation for the predetermined page can be resumed by internally applying the page address. As a result, the layout area occupied by the address buffer circuit according to the present invention can be drastically reduced as compared with the case of implementing the page address storage means in the row decoder in the related art, and high integration of the semiconductor memory device can be realized.

Claims (12)

Input means (10) for receiving a page address (Address A) applied from the outside; The page address Address A output from the input means 10 is input, and in response to the first control signal blocking_pls applied from the outside, the page address Address A is output and then another address is received from the outside. Blocking means 20 for blocking the application; First storage means (40) for storing the page address (Address A) output from the blocking means (20); After receiving the page address Address A output from the first storage means 40, the page address Address A is output in response to a second control signal erase_pls applied from the outside, and then another address is set. First control means (70) for blocking output; Second storage means (80) for storing the page address (Address A) output from the first control means (70); The page address Address A output from the second storage means 80 is input, and the page address Address A is received in response to a third control signal resistor_pls applied from the outside. Second control means (90) for outputting to 40; And an output means (50) for outputting said page address (Address A) stored in said first storage means (40). An input unit 30 receiving a page address Address A and a first control signal blocking_pls applied from the outside and outputting the page address Address A in response to the first control signal blocking_pls; An output unit (60) for storing and outputting the page address (Address A) output from the input unit (30); The page address Address A stored in the output unit 60 is received and stored in response to the second control signal erase_pls applied from the outside, and in response to the third control signal resume_pls applied from the outside. And a storage section (100) for outputting the stored page address (Address A) to the output section (60). The method of claim 2, The input unit 30 includes: input means (10) for receiving the page address (Address A); Receiving the page address (Address A) output from the input means 10, outputs the page address (Address A) in response to the first control signal (blocking_pls) after the other address is applied from the outside An address buffer circuit of a semiconductor memory device comprising blocking means 20 for blocking. The method of claim 3, wherein The input means (10) is an address buffer circuit of a semiconductor memory device consisting of any one of the NAND gate (G1) and the NOR gate. The method of claim 3, wherein The blocking means (20) is an address buffer circuit of a semiconductor memory device composed of PMOS transistors (M1, M2), NMOS transistors (M3, M4), and an inverter (I1). The method of claim 2, The output unit (60) includes first storage means (40) for storing the page address (Address A) output from the blocking means (20); And an output means (50) for outputting the page address (Address A) stored in said first storage means (40). The method of claim 6, The first storage means (40) is an address buffer circuit of a semiconductor memory device consisting of inverters (I2, I3). The method of claim 6, The output means (50) is an address buffer circuit of a semiconductor memory device consisting of inverters (I4, I5). The method of claim 2, The storage unit 100 receives the page address Address A output from the first storage means 40 and outputs the page address Address A in response to the second control signal erase_pls. First control means (70) for blocking the output of another address afterwards; Second storage means (80) for storing the page address (Address A) output from the first control means (70); The page address Address A stored in the second storage means 80 is received, and the page address Address A is output to the first storage means 40 in response to the third control signal resume_pls. An address buffer circuit of a semiconductor memory device comprising: second control means (90). The method of claim 9, The first control means (70) is an address buffer circuit of a semiconductor memory device composed of a transfer gate (T1) consisting of MOS transistors and an inverter (I6). The method of claim 9, The second storage means (80) is composed of inverters (I7, I8) address buffer circuit of the semiconductor memory device. The method of claim 9, The second control means (90) comprises inverters (I9, I10), NAND gates (G2, G3), a PMOS transistor (M5), and an NMOS transistor (M6).