KR100221024B1 - Nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device for increasing the degree of integration in a semiconductor memory device, comprising a cell array for storing data and a plurality of page buffers. And a page buffer unit for sensing the data from the cell array and temporarily storing the data in the corresponding page buffers, an inverting unit for inverting the voltage levels of the data stored in each page buffer, and column selection signals. A nonvolatile semiconductor memory device comprising: a column pass gate unit configured to transfer the inverted data to a next stage in response to a second pass; and an input / output buffer unit configured to output the data transferred from the column pass gate unit to the outside; To the first control signal and the second control signal. Power supply means for answering outputs the first and second voltage levels, and; A plurality of outputting one of the first voltage level and the second voltage level to the column pass gate unit in response to the data output from the page buffers, and inverting and outputting the voltage levels of the respective data; Reversal means.

Description

Non volatile semiconductor memory device

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device for increasing the degree of integration in a semiconductor memory device.

Recently, flash memory has been in the spotlight as a solid state file system application in small devices, and dual NAND flash memory devices have become important due to their small cell size and high reliability. In the case of the NAND flash memory device, a data read access method of a memory cell, which is mainly used, adopts a serial access method. In general, a continuous access method is classified into a sensing operation and a reading operation. The sensing operation simultaneously senses data stored in all memory cells in a string unit connected to a selected word line (or page) of a memory cell, thereby integrating the inside of the chip. This means storing the data temporarily in a data buffer (hereinafter referred to as a page buffer). In addition, the read operation means that data stored in the page buffer is sequentially read from a selected column address by toggling a control pin (RE pin) outside the chip. Since the data reading method of the NAND flash memory is described in detail in "Application No .: P95-32483, Method and Apparatus for Reading Semiconductor Memory", a detailed description thereof will be omitted.

1 is a block diagram illustrating a schematic configuration of a nonvolatile semiconductor memory device according to the prior art.

The conventional nonvolatile semiconductor memory device illustrated in FIG. 1 includes a cell array 10, a page buffer unit 20, a tristate inverter 30, a column passgate unit 40, and an input / output buffer unit 50. Consists of. The cell array 10 is for storing data, and although not shown in the drawing, the cell array 10 is composed of a plurality of strings. Each string includes a plurality of memory cells having a channel connected in series between the first select transistor and the second select transistor. Each gate of each of the memory cells is commonly connected to a word line, and when the word line is selected, all of the corresponding memory cells are activated. Corresponding bit lines BLn and n = 0 to 511 are electrically connected to the respective drain terminals of the first select transistors of the strings.

In addition, the page buffer unit 20 includes a plurality of page buffers 22 connected to the bit lines BLn, respectively, and selected words of the cell array 10 through the bit lines BLn. It is a means for sensing data stored in memory cells connected to a line and temporarily storing the data. The tree state inverting unit 30 is provided with a plurality of tree state inverting means 31 corresponding to the page buffers 22, respectively, and includes a first control signal Osac and a second control signal applied from the outside. In response to nOsac), the voltage levels of the data sensed by the page buffers 22 are inverted and output. In addition, the column pass gate unit 40 sequentially transfers data output from the inversion unit 31 to the input / output buffer unit 50 in response to column selection signals Yn applied from the outside.

Each of the tristate inverting means 31 is composed of a plurality of PMOS transistors M1 and M2 and a plurality of NMOS transistors M3 and M4. The PMOS transistors M1 and M2 have a channel connected in series between the first power supply terminal 1 and the node 1 to which the power supply voltage VCC is applied, and the output terminal and the second control of the corresponding page buffer 22, respectively. Gates are respectively connected to the second input terminal 4 to which the signal nOsac is applied. The NMOS transistors M3 and M4 are connected in series between the node 1 and the second power terminal 2 to which the ground voltage VSS is applied, and the first control signal Osac is applied. Gates are respectively connected to the first input terminal 3 and the output terminal of the page buffer 22. In addition, the column pass gate portion 40 includes a plurality of transfer transistors Tn, each of which has a gate connected to column selection signals Yn applied from the outside, and the node of the tristate inverting means 31. Each channel is connected between 1 and the input / output buffer unit 50.

The page buffers 22 that sense data from the cell array 10 and temporarily store the data have a small data driving capability. For this reason, the tree state inverting means 31 must drive the high level or low level sufficiently according to the level of data stored in the page buffers 22. That is, in response to the first control signal Osac and the second control signal nOsac applied from the outside, the data stored in the page buffers 22 are sufficiently received through the column pass gate part 40. The level of the data should be determined so that it can be delivered to the input / output buffer unit 50. In other words, suppose that the page buffer 22 senses low-level data when the memory cell connected to any page buffer 22 is an "on" cell. Further, suppose that the page buffer 22 senses high level data when the memory cell is an "off" cell. After the continuous sensing operation is completed, the page buffer 22 connected to the bit line BL0 has a low level, that is, an "on" cell, and the page buffer 22 connected to the bit line BL1 has a high level, that is, an "off" cell, respectively. Let's say it's connected.

At this time, the first control signal Osac and the second control signal nOsac applied from the outside are applied at a high level and a low level, respectively, and accordingly, the PMOS transistors M2 and the NMOS of the tristate inverting unit 30 are applied. Transistors M3 are all activated. Accordingly, the NMOS transistor M4 of the inverting means 31 whose gate is connected to the page buffer 22 corresponding to the bit line BL0 is inactivated and the PMOS transistor M1 is activated. The power supply voltage VCC, that is, the high level, is transferred to the input / output buffer unit 50 through the transfer transistor T0 of the PMOS transistors M1 and M2 and the column pass gate unit 40. On the other hand, the NMOS transistor M4 having a gate connected to the page buffer 22 corresponding to the bit line BL1 is activated and the PMOS transistor M1 is inactivated, so that the NMOS transistors M3 and M4 and the column passgate portion are inactivated. The ground voltage VSS, that is, the low level is transferred to the input / output buffer unit 50 through the transfer transistor T1 of 40 to complete the read operation.

However, according to the conventional nonvolatile semiconductor memory device as described above, the tree state inverting means corresponding to the respective page buffers 22 in order to sufficiently transfer the data stored in the page buffers 22 to the input / output buffer unit 50. Field 31 was used. Here, since the layout area occupied by the components of the tristate inverting means 31, that is, the NMOS transistors M3 and M4 and the PMOS transistors M1 and M2 is large, it is difficult to realize high integration. .

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a nonvolatile semiconductor memory device capable of realizing high integration by simplifying components in a page buffer and reducing its layout area.

1 is a block diagram schematically showing a configuration of a conventional nonvolatile semiconductor memory device;

2 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to the present invention;

* Explanation of symbols for main parts of the drawings

10: cell array 20: page buffer unit

30: inverting portion 40: column pass gate portion

50: I / O buffer section

According to an aspect of the present invention for achieving the above object, a cell array for storing data, and a plurality of page buffers are provided, and each of the page buffers corresponding to the data by sensing the data from the cell array A page buffer section for temporarily storing the data buffer, an inverting section for inverting the voltage level of the data stored in each page buffer, and a column pass gate section for transferring the inverted data to the next stage in response to column selection signals. And an input / output buffer unit configured to output the data transferred from the column passgate to an external device, wherein the inversion unit is configured to have a first voltage level in response to a first control signal and a second control signal; Power supply means for outputting a second voltage level; A plurality of outputting one of the first voltage level and the second voltage level to the column pass gate unit in response to the data output from the page buffers, and inverting and outputting the voltage levels of the respective data; And reversal means.

In a preferred embodiment of the apparatus, the power supply means includes first supply means for outputting the first voltage level in response to the first control signal; And second supply means for outputting the second voltage level in response to the second control signal.

In a preferred embodiment of this apparatus, the first supply means is provided with an n-channel conductive MOS transistor.

In a preferred embodiment of the device, the second supply means is provided with a p-channel conductive MOS transistor.

In a preferred embodiment of the device, each inverting means is provided with a p-channel conductive MOS transistor and an n-channel conductive MOS transistor.

In a preferred embodiment of the device, the first voltage level and the second voltage level are ground voltages and power supply voltages, respectively.

By such an apparatus, high integration of a semiconductor memory device can be realized by minimizing the layout area occupied by each inverting means by replacing the inverting means composed of a plurality of transistors with an inverter using only two transistors.

Hereinafter, the present invention will be described in detail with reference to FIG. 2.

In FIG. 2, the same reference numerals are given to the components having the same functions as the components shown in FIG.

In order to reduce the layout area occupied by the conventional tristate inverting means 31, the nonvolatile semiconductor memory device according to the present invention may reduce the two transistors of each inverting means 31 and perform the same function as the conventional one. The reversal means 32 were implemented. As a result, high integration of the semiconductor memory device can be realized by drastically reducing the layout area occupied by the inverting means 32 according to the present invention. 2 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.

The nonvolatile semiconductor memory device shown in FIG. 2 includes a cell array 10, a page buffer unit 20, an inversion unit 30, a column passgate unit 40, and an input / output buffer unit 50. Consists of. The cell array 10 is for storing data, and although not shown in the drawing, the cell array 10 is composed of a plurality of strings. Each string includes a plurality of memory cells having a channel connected in series between the first select transistor and the second select transistor. Each gate of each of the memory cells is commonly connected to a word line, and when the word line is selected, all of the corresponding memory cells are activated. Corresponding bit lines BLn and n = 0 to 511 are electrically connected to the respective drain terminals of the first select transistors of the strings.

In addition, the page buffer unit 20 includes a plurality of page buffers 22 connected to the bit lines BLn, respectively, and selected words of the cell array 10 through the bit lines BLn. It is a means for sensing data stored in memory cells connected to a line and temporarily storing the data. The inverting unit 30 includes a plurality of inverting means 32 corresponding to the page buffers 22 and first supply means 34 and second supply means commonly connected to the inverting means 32, respectively. It is composed of a power supply means 38 consisting of 36). That is, the first supply means 34 discharges the first conductive path L1 to the ground voltage level VSS in response to the first control signal Osac applied from the outside and the NMOS transistor M5. Consists of The second supply means 36 comprises a PMOS transistor M6 as a means for charging the second conductive path L2 to the power supply voltage level VCC in response to a second control signal Osac applied from the outside. It is. The inverting means 32 inverts and outputs each voltage level of data output from the corresponding page buffers 22, respectively.

Each of the inverting means 32 is composed of a PMOS transistor M7 and an NMOS transistor M8. The PMOS transistor M7 has a gate connected to an output terminal of a corresponding page buffer 22, and the second conductive The channel is connected between the path L2 and the node 2. The NMOS transistor M8 has a gate connected to an output terminal of the page buffer 22 and a channel connected between the node 2 and the first conductive path L1. In addition, the column pass gate unit 40 transmits data output through the inverting means 32 to the input / output buffer unit 50 in response to column selection signals Yn applied from the outside. The column passgate part 40 is composed of a plurality of transfer transistors Tn. Each of the transfer transistors Tn has a gate connected to each of the column selection signals Yn applied from the outside, and is connected between each node 2 of the inverting means 32 and the input / output buffer unit 50. The channel is connected. The configuration method of the inverting means 32 described above enables a memory device to occupy a significantly reduced layout area compared to the layout area of a conventional semiconductor memory device.

Assume that the page buffer 22 senses low level data when a memory cell connected to any page buffer 22 shown in FIG. 2 is an "on" cell. On the other hand, suppose that the page buffer 22 senses high level data when the memory cell is an "off" cell. After the continuous sensing operation is completed, the page buffer 22 connected to the bit line BL0 has a low level, that is, an "on" cell, and the page buffer 22 connected to the bit line BL1 has a high level, an "off" cell, respectively. Let's say At this time, the first control signal Osac and the second control signal nOsac applied from the outside are applied at a high level and a low level, respectively, and the first supply means 34 and the second supply signal. The NMOS transistor M5 and the PMOS transistor M6 of the supply means 36 are activated at the same time. Accordingly, the first conductive path L1 corresponding to each of the transistors M5 and M6 is discharged to the ground voltage VSS and the second conductive path L2 is charged to the power supply voltage VCC.

Therefore, the NMOS transistor M8 of the inverting means 32 whose gate is connected to the page buffer 22 corresponding to the bit line BL0 is inactivated and the PMOS transistor M7 is activated. The power supply voltage VCC, that is, the high level is transmitted to the input / output buffer unit 50 through the transfer transistor T0 and the PMOS transistor M7 activated by the column selection signal Y0 applied from the outside. . On the other hand, the NMOS transistor M8 of the inverting means 32 whose gate is connected to the page buffer 22 corresponding to the bit line BL1 is activated and the PMOS transistor M7 is deactivated. The ground voltage VSS, that is, the low level, is transferred to the input / output buffer unit 50 through the transfer transistor T1 activated by the column select signal Y1 applied from the outside and the NMOS transistor M8. The read operation is completed.

As described above, by inverting means for transferring the data sensed in the page buffer portion to the input / output buffer portion, respectively, by inverting the area occupied by the inverting means in the chip, a high integration of the semiconductor memory device is achieved. It can be realized.

Claims (6)

A cell array 10 for storing data and a plurality of page buffers 22 are provided, and the data is sensed from the cell array 10 and temporarily stored in the corresponding page buffers 22. A page buffer section 20, an inverting section 30 for inverting the voltage level of the data stored in each page buffer 22, and column selection signals Yn (where n is a positive integer). Non-volatile having a column pass gate 40 for transmitting the inverted data to the next stage in response, and an input / output buffer unit 50 for outputting the data transferred from the column pass gate 40 to the outside. In a semiconductor memory device, The inverting unit 30 includes: power supply means 38 for outputting a first voltage level and a second voltage level in response to a first control signal Osac and a second control signal nOsac; In response to the data output from the page buffers 22, one of the first voltage level and the second voltage level may be output to the column pass gate unit 40, respectively, and the voltage level of each data. And a plurality of inverting means (32) for inverting and outputting the volatile semiconductor memory device. The method of claim 1, The power supply means 38 includes first supply means 34 for outputting the first voltage level in response to the first control signal Osac; And second supply means (36) for outputting the second voltage level in response to the second control signal (nOsac). The method of claim 2, The first supply means (34) is a nonvolatile semiconductor memory device, characterized in that provided by the n-channel conductive MOS transistor (M5). The method of claim 2, The second supply means (36) is a non-volatile semiconductor memory device, characterized in that provided with a p-channel conductive MOS transistor (M6). The method of claim 1, And each inverting means (32) comprises a p-channel conductive MOS transistor (M7) and an n-channel conductive MOS transistor (M8). The method of claim 1, And the first voltage level and the second voltage level are a ground voltage VSS and a power supply voltage VCC, respectively.