JPS54123838A - Memory address control unit for data processor - Google Patents

Memory address control unit for data processor

Info

Publication number
JPS54123838A
JPS54123838A JP3132978A JP3132978A JPS54123838A JP S54123838 A JPS54123838 A JP S54123838A JP 3132978 A JP3132978 A JP 3132978A JP 3132978 A JP3132978 A JP 3132978A JP S54123838 A JPS54123838 A JP S54123838A
Authority
JP
Japan
Prior art keywords
address
byte
unit
word
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3132978A
Other languages
Japanese (ja)
Inventor
Makoto Tazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3132978A priority Critical patent/JPS54123838A/en
Publication of JPS54123838A publication Critical patent/JPS54123838A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To make easy the transition for the mode between the byte mode and word mode on CPU at ON-line state, by providing the shift unit etc. which convert the byte address into word address. CONSTITUTION:When the CPU 2 is of byte mode, the status FF3 is set to ''1'', and when the byte address 12(1100) address A in the main memory unit 1 constituted in word unit is called out, since FF3 is ''1'', the shift unit 4 has right 1 bit shift function, and the byte address 12(1100) address is converted into the word address 6(110) address and set to the memory address register 5. On the other hand, ''0'' shifted out from the unit 4 is stored in FF6 and gives 1 byte shift function to the byte shift unit 7. Thus, the content of the word address 6 read out from the unit 1 at the word address 6(110) of the register 5 is shifted right by one byte at the unit 7, and it is set to the memory read register 8.
JP3132978A 1978-03-17 1978-03-17 Memory address control unit for data processor Pending JPS54123838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3132978A JPS54123838A (en) 1978-03-17 1978-03-17 Memory address control unit for data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3132978A JPS54123838A (en) 1978-03-17 1978-03-17 Memory address control unit for data processor

Publications (1)

Publication Number Publication Date
JPS54123838A true JPS54123838A (en) 1979-09-26

Family

ID=12328214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3132978A Pending JPS54123838A (en) 1978-03-17 1978-03-17 Memory address control unit for data processor

Country Status (1)

Country Link
JP (1) JPS54123838A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949639A (en) * 1982-09-16 1984-03-22 Hitachi Ltd Word length varying circuit of storage circuit
JPS60258799A (en) * 1985-04-23 1985-12-20 Toshiba Corp Semiconductor memory
JPS61205984A (en) * 1985-03-11 1986-09-12 日本電気オフイスシステム株式会社 Memory reading system
JPS6366645A (en) * 1986-09-08 1988-03-25 Nec Corp Calculation circuit for effective address

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949639A (en) * 1982-09-16 1984-03-22 Hitachi Ltd Word length varying circuit of storage circuit
JPS61205984A (en) * 1985-03-11 1986-09-12 日本電気オフイスシステム株式会社 Memory reading system
JPS60258799A (en) * 1985-04-23 1985-12-20 Toshiba Corp Semiconductor memory
JPH0226315B2 (en) * 1985-04-23 1990-06-08 Tokyo Shibaura Electric Co
JPS6366645A (en) * 1986-09-08 1988-03-25 Nec Corp Calculation circuit for effective address
JPH0544692B2 (en) * 1986-09-08 1993-07-07 Nippon Electric Co

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