JPS554668A - Computer - Google Patents

Computer

Info

Publication number
JPS554668A
JPS554668A JP7789078A JP7789078A JPS554668A JP S554668 A JPS554668 A JP S554668A JP 7789078 A JP7789078 A JP 7789078A JP 7789078 A JP7789078 A JP 7789078A JP S554668 A JPS554668 A JP S554668A
Authority
JP
Japan
Prior art keywords
bit
program
computer
contents
execution sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7789078A
Other languages
Japanese (ja)
Inventor
Yoshiki Nansei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7789078A priority Critical patent/JPS554668A/en
Publication of JPS554668A publication Critical patent/JPS554668A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To grasp the program execution sequence and to simplify the inquiry for the factor of the fault occurrence in the computer which performs the arithmetic control based on the program by providing the trace bit at the control program area.
CONSTITUTION: The computer contains arithmetic process part 1, program counter part 2 to indicate the operation execution sequence, memory part 4 possessing address part 3 which is indicated by part 2, and decoder part 5 to give the arithmetic process information to part 1 respectively. In such computer, trace bit 21 is provided at the program area of part 4, and output part 22 is connected to bit 21. Furthermore, one bit correspondint to part 3 is given to bit 21. And when the fixed memory of part 4 is supplied to decoder part 9 via the designated address of part 3 corresponding to the contents of part 2, bit 21 also transfers the data to part 22. And this output is used as the trigger signal in order to memorize the contents of counter 2.
COPYRIGHT: (C)1980,JPO&Japio
JP7789078A 1978-06-26 1978-06-26 Computer Pending JPS554668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7789078A JPS554668A (en) 1978-06-26 1978-06-26 Computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7789078A JPS554668A (en) 1978-06-26 1978-06-26 Computer

Publications (1)

Publication Number Publication Date
JPS554668A true JPS554668A (en) 1980-01-14

Family

ID=13646661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7789078A Pending JPS554668A (en) 1978-06-26 1978-06-26 Computer

Country Status (1)

Country Link
JP (1) JPS554668A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155650A (en) * 1981-03-23 1982-09-25 Hitachi Ltd Detecting circuit of break point
JPS5880751A (en) * 1981-11-06 1983-05-14 Mitsubishi Electric Corp Data processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155650A (en) * 1981-03-23 1982-09-25 Hitachi Ltd Detecting circuit of break point
JPS5880751A (en) * 1981-11-06 1983-05-14 Mitsubishi Electric Corp Data processor

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