JPS54152827A - Serial data transmission system for data transmission system - Google Patents

Serial data transmission system for data transmission system

Info

Publication number
JPS54152827A
JPS54152827A JP6097478A JP6097478A JPS54152827A JP S54152827 A JPS54152827 A JP S54152827A JP 6097478 A JP6097478 A JP 6097478A JP 6097478 A JP6097478 A JP 6097478A JP S54152827 A JPS54152827 A JP S54152827A
Authority
JP
Japan
Prior art keywords
data
signal line
circuit
line
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6097478A
Other languages
Japanese (ja)
Inventor
Masahiro Takahashi
Kinshiro Onishi
Shoichi Furutoku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6097478A priority Critical patent/JPS54152827A/en
Publication of JPS54152827A publication Critical patent/JPS54152827A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the constitution as well as to ensure a high-speed information exchange by securing the data transmission in such form as the access of the memory via the control signal line and the data signal line.
CONSTITUTION: Data processor 1 of the microcomputer and the like is connected to analog or digital input/output circuits 2-1W2-n via downward control signal line A, downward data line B, upward control signal line C and upward data D each. In case processor 1 writes the data into circuit 2, the sending of the WRITE address proper to the input/output circuit to dats line B is started and at the same time signal line A is turned to "1" with the data sending start continued to circuit 2. After this, processor 1 sends out the data, and circuit 2 takes in the subsequent data in case the WRITE address belongs to its own. When processor 1 reads the data out of circuit 2, the READ address proper to the input/output circuit is sent to data line B and at the same time signal line A is turned to "1". And circuit 2 starts to send the data to data line D and also turns signal line C to "1" if the READ address belongs to its own.
COPYRIGHT: (C)1979,JPO&Japio
JP6097478A 1978-05-24 1978-05-24 Serial data transmission system for data transmission system Pending JPS54152827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6097478A JPS54152827A (en) 1978-05-24 1978-05-24 Serial data transmission system for data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6097478A JPS54152827A (en) 1978-05-24 1978-05-24 Serial data transmission system for data transmission system

Publications (1)

Publication Number Publication Date
JPS54152827A true JPS54152827A (en) 1979-12-01

Family

ID=13157896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6097478A Pending JPS54152827A (en) 1978-05-24 1978-05-24 Serial data transmission system for data transmission system

Country Status (1)

Country Link
JP (1) JPS54152827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577653A (en) * 1980-06-17 1982-01-14 Matsushita Electric Ind Co Ltd Transmission control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577653A (en) * 1980-06-17 1982-01-14 Matsushita Electric Ind Co Ltd Transmission control system

Similar Documents

Publication Publication Date Title
EP0217479A3 (en) Information processing unit
JPS54152827A (en) Serial data transmission system for data transmission system
JPS5644919A (en) Control board
JPS5326632A (en) Common memory control unit
JPS5525176A (en) Memory unit control system
JPS5553743A (en) Address control system
JPS5563453A (en) Memory system
JPS52149038A (en) Interface system
JPS55143637A (en) Data transfer unit
JPS54131831A (en) Memory unit
JPS5533282A (en) Buffer control system
JPS5733472A (en) Memory access control system
JPS5586237A (en) Bit rate conversion system
JPS5488749A (en) Information processor
JPS5541511A (en) Micro program control system
JPS55112688A (en) Detection circuit for optional character
JPS5478637A (en) Information transfer control unit
JPS5532109A (en) Data transfer system
JPS55147745A (en) Data transfer unit between memory units
JPS5587241A (en) Information transfer system
JPS5532263A (en) Check system for write data
JPS54122060A (en) Inter-processor information transfer system
JPS56161775A (en) Subscanning control system for facsimile
JPS5311548A (en) Error information transfer control system
JPS54150935A (en) Memory switching device