JPS5487439A - Error detection system of memory unit - Google Patents

Error detection system of memory unit

Info

Publication number
JPS5487439A
JPS5487439A JP15623277A JP15623277A JPS5487439A JP S5487439 A JPS5487439 A JP S5487439A JP 15623277 A JP15623277 A JP 15623277A JP 15623277 A JP15623277 A JP 15623277A JP S5487439 A JPS5487439 A JP S5487439A
Authority
JP
Japan
Prior art keywords
parity
data
elements
bits
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15623277A
Other languages
Japanese (ja)
Inventor
Taiho Higuchi
Fumio Hosono
Akio Munakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15623277A priority Critical patent/JPS5487439A/en
Publication of JPS5487439A publication Critical patent/JPS5487439A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve an error detection rate by dividing the output of each semiconductor memory element into several groups and by leading respective groups to different parity check circuits.
CONSTITUTION: This system is provided with semiconductor memory elements 1-1 and 1-2 with several bit outputs and parity ckeck circuits 3-1 and 3-2, and the outputs of elements 1-1 and 1-2 are divided into bits A0 to A7 of data A and bits B0 to B7 of data B; parity generator 2-1 generates check bit PA for data A, and parity generator 2-2 parity bit PB for data B. Then, elements 1-1 and 1-2 are applied at the same time with the same address information AD0 to the information AD5, chip select signal CS, and read/write signal R/W. Next, outputs of elements 1-1 and 1-2 classified by groups are supplied to different circuits 3-1 and 3-2, where comparison of parity bits is done, and an error signal is outputted.
COPYRIGHT: (C)1979,JPO&Japio
JP15623277A 1977-12-23 1977-12-23 Error detection system of memory unit Pending JPS5487439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15623277A JPS5487439A (en) 1977-12-23 1977-12-23 Error detection system of memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15623277A JPS5487439A (en) 1977-12-23 1977-12-23 Error detection system of memory unit

Publications (1)

Publication Number Publication Date
JPS5487439A true JPS5487439A (en) 1979-07-11

Family

ID=15623247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15623277A Pending JPS5487439A (en) 1977-12-23 1977-12-23 Error detection system of memory unit

Country Status (1)

Country Link
JP (1) JPS5487439A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50118633A (en) * 1973-12-27 1975-09-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50118633A (en) * 1973-12-27 1975-09-17

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