SU1251187A1 - Device for checking memory blocks - Google Patents

Abstract

The invention relates to computing technology and allows real-time monitoring of memory blocks, in particular, made in the form of chips with a large amount of memory. The aim of the invention is to simplify the device. The device contains a signal generator 1, a signal conditioner 2, a trigger 4, an adder 5 modulo two, counters 7 and 8, which perform respectively the functions of the address counter and the control frame counter, unit 9 of comparison, and signal conditioner 10. Shaper 2 generates write enable and read signals at input 14 of the monitored memory block 6. The trigger 4 controls the writing and reading of information in block 6. The device provides full control of block 6 of the memory chip using the running unit method by repeatedly writing, counting and comparing the recorded and read information in each memory element of block 6. The comparison in block 9 is controlled by a signal gating at the output of the shaper 10. The sequence of control is provided by the adder 5. 2 Il, 2 tab. SS CO WITH

Description

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1251187

The invention relates to computing technology and can be used for the operational monitoring of memory circuits, in particular, made in the form of microcircuits with a large memory size.

The purpose of the invention is to simplify the structure.

FIG. shows a functional diagram of the proposed device; in fig. 2 - time diagrams that show his work.

The device contains (Fig. 1) a signal generator 1, a first signal generator 2, an AND 3 element, a trigger 4 and an adder 5 modulo two. FIG. a monitored memory block 6 is shown. The device also contains the first 7 and second 8 counters, a comparison unit 9, a second driver 10 of signals and an indication unit 11 consisting of an indicator 12 and a trigger 13.

FIG. 1, control outputs 1A and 15 are designated to provide the enable signals and read or write signals, respectively.

20

25

since he is a boy

BUT, and information output device 16, as well as the input 17 and the output 18 of the transfer of the adder 5, the input 19 start and the output 20 of the generator 1.

FIG. 2 shows a pulse Start at input 19, pulses 20 at the output of generator 1, pulses 21 of the record and reading at output 15, pulses 22

addresses, as well as pulses 23 and 24 at the outputs of the formers 2 and 10, respectively.

The device works as follows.

In the initial state (after the Reset signal), the counters 7 and 8 are reset to zero, the trigger 4 is in the Record state, the trigger 13 is in the state corresponding to the indication of the Indicator 12f. The Start-up signal generates the first pulse and writes 1 at zero address to the monitored block 6. The information recorded in block 6 comes from the adder 5 and is determined by the state of counters 7 and 8, which act as the address counter and frame counter, respectively . The device provides full control unit 6 in accordance with the algorithm table. one.

Table 1

2

00000

ABOUT

ABOUT

On the falling edge of the first pulse of the generator 1, trigger 4 is tilted, and the recorded information is read. When writing and reading, the signal at input 14 of block 6 is fed through shaper 2, which eliminates the influence of transients. Then the recorded and read information is compared. At the output 18 of the adder 5 - the same information when writing and reading at the same address. The information at the output of block 9 in read mode is identical to that read from block 6 if it is operational. Since the information on the output of block 6 is shifted relative to the information on its input 16, a comparison is made on a gate pulse from the output of the imaging unit 10, which appears only in read mode, which eliminates the appearance of a spurious signal at the output of block 9.

Thus, in each frame of the counter 8, the read information is read, read, and retrieved at all 2 addresses, where n is the number of bits of the address and counter 7.

The information recorded in the checked block 6 comes from the adder 5 from the output of 18 transfer units. Information in accordance with the algorithm given in Table. 1 is formed by the serial connection of counters 7 and 8 and the connection of all the outputs of the counter 7 and the corresponding inverse outputs 8 on, the corresponding inputs of the adder 5.

Upon arrival at the input 17 of the adder 5 (transfer from the previous bit) of pulses from the generator, at output 18, information appears in accordance with the algorithm given in Table. 2

Note

The information supplied by the adder 5 according to this algorithm is equivalent to the described record sequence.

Example. Let the number of frames in the counter 8 be

Hk

Hk

1 o

stump a number in

01

1O,

7 (address) is 1 OC

01 1

100 counter

Xa 1 O 1 (the highest digit of the numbers on the right).

Obviously, Ha i Xk. The random summation of Xa, Xk, and Ro, where Ro is the transfer unit from the previous discharge, gives the following: 1100 0010

Ha hk

to me

About 1

11110

.one

ABOUT

Ro 1 Result About

Intermediate transfer unit

The number in the adder

Exit 18

Thus, in the case of the output 18 of the adder 5 in accordance with the Institute of Algorithms with the algorithm table. 2 O appears, which is recorded in block 6. The zero frame ends at the moment when the output of the overflow pulse counter 7 appears.

From the beginning of the filling of the counter 8, the first and the next 2 frames of the check of block 6 are passed in accordance with the algorithm of tab. 1, i.e. all year

000001

about

elementary acts

2 write reads are made.

In case the read information does not coincide with the recorded information, the block

Table 2

Xa is some number currently available in counter 7 (i.e., address); XK - the number of frames in the counter 8. 9 gives a pulse, overturning

trigger 13, which leads to the ignition of the indication signal Scrap. If block 6 is healthy, trigger 13 remains in the Goden position.

 At the end of the monitoring, the overflow pulse of the counter 8 stops the generator 1.

Claims (1)

Invention Formula A device for monitoring memory blocks, a signal generator, a trigger, a first signal conditioner, a comparison unit, an indication unit, an AND element, first and second counters, one of the outputs of the first counter being address outputs of a device whose trigger input is input start-up of the signal generator, which differs from the fact that, in order to simplify the device, a modulo two adder and a second signal conditioner, whose input is connected to the output of the AND element, and the output to the input gate of the comparison unit, are entered into it The modulo adder's two inputs are connected respectively to one of the first counter outputs and to the inverse bit outputs of the second counter, the input of which is connected to another output of the first counter, the output of the last discharge of the second counter is connected to the stop input of the signal generator whose output is connected to the input of the first signal conditioner, the first input of the element I, the counting input of the trigger and the transfer input modulo two, the transfer output of which is connected to one of the input of the comparison unit, the output cat orogo is connected to the input of the display unit, trigger output is connected to the counting input of the first counter and the second input of the element AND, the transfer output of the modulo two adder and the other input of the comparison unit are respectively informational Compiled by T. Zaitseva Editor A. Ogar Tehred J. Gaidosh Proofreader E. Roshko Order 4419/51 Circulation 543. Subscription VNIIPI USSR State Committee for inventions and discoveries P3035, Moscow, Zh-35, Raushsk nab., 4/5 Production and Printing Enterprise, Uzhgorod, st. Project, 4 the output and input of the device, which controls the outputs of which are the outputs of the first generator. 5 of the singal and the trigger. fi9-2