SU1325565A1 - Buffer memory - Google Patents

Abstract

The invention relates to computing and can be used in the construction of buffer storage devices of channels and exchange devices. The aim of the invention is to improve the speed of the device. The device contains a drive 1, a counter 2 addresses, block 3 comparisons, a counter 6 addresses, an element AND-OR 7, an element AND 8 and a one-oscillator 9. The goal is achieved by the fact that there are no elements in the device between the address counter and the accumulator additional delays. 1 il.

Description

one

The invention relates to computing and can be used in the construction of buffer transmitters of channels and exchange devices.

The aim of the invention is to increase the speed of the device.

The drawing shows a block diagram of the proposed device.

The device contains drive 1, Counter 2 addresses, block 3 comparisons, Input 4 records, input 5 readings, counter 6 addresses, AND-OR 7 element, AND 8 element, one-shot 9, clock input 10, information outputs 11 and informational inputs 12,

The device works as follows.

Before starting to write information counters 2 and 6 addresses set. c to the initial state (the reset circuit before the recording mode is not shown).

When performing the recording mode (presence of a signal at the input 4 of the recording), the recording pulses from the clock input .10 of the device through the elements AND 8 and AND- OR 7 arrive at the clock inputs of the counters 2 and 6 addresses. The information supplied to the Information Outputs 11 of the device is recorded in the drive 1 at addresses 5 formed by the counter 6 to the address. Counters 2 and 6 addresses both during recording and. at the end have the same value. On the decline of the recording signal at the input 4 of the recording, the one-shot 9 produces a pulse of setting the counter 6 to its initial state.

Thus, before the reading mode, the 6 address counter is reset, and the 2 address counter shows the number of addresses used when writing.

In reading mode (presence of signal at input 5 of reading) reading pulses from the clock input 0 of the device editor N. Lazarenko Order 3116/49

Composer S. Shustenko

Tehred A. Kravchuk Proofreader L. Pilipenko

Circulation 589 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

, Proizvodstvenno-polygraphic enterprise, Uzhgorod, st. Design, 4.

3255652

the cut element AND-OR 7 arrives at the clock input of the counter 6. Information at the corresponding addresses formed by the counter 6 from the accumulator 1 is fed to the input 12 of the device.

The outputs of the counters 2 and 6 addresses are compared by unit 3 comparison. The outputs of the comparison unit 3 (less, equal, more) can be analyzed by special monitoring and processing devices to make decisions in case of failure or malfunction.

Claims (1)

Invention Formula 0 0 The buffer memory device containing the drive, information inputs and outputs of which are the corresponding inputs and outputs of the device, the first and second address counters, the AND-OR element, the comparison unit 5, the first input of which is connected to the output of the first address counter, the output of the second The address counter is connected to the address input of the accumulator, the output of the comparison unit is the output of the device stop signal, characterized in that, in order to increase the speed of the device, it contains a one-shot and the element And, first The input of which is the clock input of the device and is connected to the first input of the AND-OR element, the second input of which is the recording input of the device and is connected to the second input of the AND element and the input of the installation of the second address counter, the counting input of which is connected to the output of the AND-OR element The third input of which is the read input of the device, the second input of the comparison unit is connected to the output of the second address counter, the output of the AND element is connected to the counting input of the first address counter. five 0 five