SU1297119A1 - Storage with self-checking - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices. The aim of the invention is to increase the reliability and speed of a self-monitoring storage device. The device contains a drive 1, the number of addresses in which exceeds the required for the operation of the computing device, the register 2 addresses, information input blocks 3, information registers 7, 12, comparison blocks 8, triggers 13, 14, elements OR 15-19, delay elements 20- 23, elements And 24-27, the inputs and outputs of the device. The device provides information recovery in a certain volume, has high speed, since only two write and read operations are performed instead of three, and high reliability is due to a decrease in storage capacity. 1 dw., 2 tab. (L with

Description

The invention relates to computing, in particular, to storage devices.

The aim of the invention is to increase the reliability and speed of a self-monitoring storage device.

The drawing shows a block diagram of a self-monitoring memory device.

The device contains a drive 1, the number of addresses in which is twice as necessary for the operation of the computing device, the register 2 addresses, information input blocks 3, each of which consists of the first and second elements AND 4 and AND 5 and the element OR 6, the first information register 7, blocks 8 comparisons, each of which consists of elements AND-NOT 9, OR 10 and 11, the second information register 12, the first trigger 13, the second trigger 14, the first 15, the second 16, the third 17, the fourth 18 and Fifth 19 elements OR, first 20, second 21, third 22 and fourth 23 elements Delay s, first 24, second 25, third 26, and fourth 27 elements I. The device has address inputs 28, inputs 29 of the recordable number (information inputs), inputs “Start” 30, “Record 31 and read 32 (control) devices, informational outlets 33 and the “Readout 34” output.

Drive 1 has the inputs “Write,“ Start, “Read and information outputs.

The device works as follows.

The first, second, and third control inputs 30, 31, 32 of the device receive, respectively, Start, Write, and Read. At control output 34, the device generates a "Read allowed" signal.

The first, second, third, and fourth delay elements 20, 21, 22, and 23 form, respectively, Start Drive and Read, End Read, Write, End Record, and End, which are fed to Drive 1 through its second and third signals. control inputs.

When writing information to the drive 1, the address code is sent to the device inputs 28, the code of the recorded number is input through inputs 29, the Start signal and the Record input 31 signal. The first trigger 13 is set with the trigger signal OR 16 corresponding to the connection of the first half of accumulator I. Second trigger 14 through the fifth element OR 19 is set to the position "Read. Information is recorded in the address register on the leading edge of the “Start.

Recorded information through the elements And 5 and OR 6 blocks 3 input input

Firmatsii enters the first information register 7.

At the second control input of accumulator 1, a start signal appears at a time interval determined by the third delay element 22 and the third OR 17 element. At the same time, the signal arrives at the input of the fourth delay element 23 through the fifth element OR 19. Information from accumulator 1 is modulo two bitwise with information from the first information register 7 by means of AND-NOT elements 9, OR 10, and 11 of comparison units 8 and arrives to the inputs of the second information register 12, which is received on the leading edge of the "End" signal coming from the output of the fourth delay element 23. The "End of read signal from the output of the first delay element 20" signal translates the first trigger 13 into position e, corresponding to the second half of the accumulator 1. The second flip-flop 14 is set to the "recording. A start drive signal is generated through the third element OR 17 and the third delay element 22.

Information from the second information register 12 is recorded in the second half of the accumulator.

The second trigger 14 is set to "Read on signal" End of recording, coming in through the fourth and fifth elements OR 18, OR 19, and the "Start storage signal is generated through the first and third elements OR 15 and OR 17 and the third delay element 22. Read information from the second block of accumulator 1 is performed in the same way as reading from the first half of accumulator 1.

The "End of Read" signal is generated by the first delay element 20 and is fed to the counting input of the first trigger 13 and switches its B state, corresponding to the first half of drive I. The second trigger 14 is set to the Write position by the signal received through the first And 24 element.

The recording of information in the first half of accumulator 1 is performed similarly to the recording in the second half of accumulator 1.

The signal "The end of the recording at the output of the second delay element 21 through the fourth element OR 18 and the fourth element And 27 at the output 34 produces a signal" The connection is denied, which ends the recording of information into the drive 1.

The table lists the possible variants of the result of recording information arriving at input 29 depending on the state — accumulator 1. Table 1 is obtained under the assumption that there is only one defect in two bits of the same name address.

When reading information to the device inputs, an address code is received at input 28, the signal "Start at input 30, signal" Read at input 32. The first trigger 13 through the second element OR 16 is set to the state corresponding to the first half of drive 1. The second trigger 14 through Fifth element OR 19 is set to the position "Read. Information is recorded in the address register on the leading edge of the “Start. At the second control input of accumulator 1, a start accumulator signal appears at a time interval determined by the third delay element 22 and the third element OR 17.

Information from accumulator 1 enters the first information register 7 through the elements AND 4 and OR b of the information input unit 3 on the leading edge of the signal "End coming from the output of the fourth delay element 23 through the third element AND 26 to the second inputs of the first elements AND 4 blocks input information.

The signal "End of reading from the output of the first delay element 20 transfers the first trigger 13 to the position corresponding to the connection from the second half of accumulator 1. The signal to the input of the third delay element 22, at the output of which the signal" Start the accumulator, passes through the second element And 25, the fourth element OR 18, the first element OR 15 and the third element OR 17.

On the leading edge of the signal "End coming from the output of the fourth delay element 28 to the second information register 12, the result of comparing the information read from the second half of accumulator 1 with the information stored in the first information register 7 via AND-HE 9, OR 10 and And 11 blocks 8 comparisons. The signal "Allowed to be read at the control output 34 of the device is generated through the second element AND 25, the fourth element OR 18, and the fourth element AND 27 n allows the next system device to receive true information for further processing.

In tab. Table 2 shows the result of reading the recorded information in the presence of defects listed in Table. one.

Comparison of the information recorded at the inputs 29 and read at the outputs 33 shows their complete identity.

The proposed device provides information recovery in the amount corresponding to the device prototype. However, the proposed device has a higher speed, since it requires only two write or read operations instead of three in the prototype device and a higher reliability due to a decrease in the storage capacity and the exception of the majorization unit.

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Claims (1)

Invention Formula A self-monitoring memory device containing an accumulator, an address register whose information inputs are the device's address input, and outputs are connected to the accumulator's address inputs, delay elements, first AND element, first OR element, whose first input and the address register control input are combined and are the start-up input of the device, characterized in that, in order to increase the reliability and speed of the device, information registers, information input blocks, comparison blocks, the first and second tr the second, third, fourth, and fifth elements OR, the second, third, and fourth elements AND, the first information inputs of the information input blocks, are the information input of the device, and their outputs are connected to the inputs of the first information register, the outputs of which are connected to the first information inputs of comparison units, the outputs of which are connected to the information inputs of the second information register, the outputs of which are connected to the information inputs of the storage device, the information outputs of which are connected to The second information inputs of the information input units and the second information inputs of the comparison units, the outputs of the second information register are information outputs of the device, the first inputs of the second and fifth OR elements are connected to the device start input, the first input of the first AND element and the first control inputs of the information input blocks The first inputs of the second and third elements are combined and are the read input of the device, the output of the third element is To the second control inputs of the information input blocks, the output of the first element OR is connected to the first input of the third element OR and the input of the first delay element, the output of which is connected to the second input of the first element AND, the second input of the second element AND, the second input of the third element OR, the first input of the first trigger, the output of which is connected to the record input of the accumulator, to the first inputs of the third and fourth elements AND, the output of the third element OR via the third delay element connected to the input of the accumulator, output n The first element And connected to the first input of the second trigger and through the second delay element connected to the first input of the fourth element OR, the second input of which is connected to the output of the second element And, the output of the second trigger connected to the input of the drive, the fourth the OR element is connected to the second inputs of the first and fifth OR elements and the fourth AND element, the output of which is the output of the read resolution of the device, the output of the fifth OR element is connected to the second input of the second trigger and - - defect of the second half of the accumulator, in other cases the defect of the first half of the accumulator is assumed. Compiled by O. Kulakov Tehred I. VeresKorrektor M. Samborska Circulation 590 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 through the fourth delay element is connected to the control input of the second information register, to the second input of the third AND element, the second input of the second OR element, the output of which is connected to the second input of the first trigger. Table 1 T a B l and c a 2