SU763973A1 - Individual check buffer memory - Google Patents

Description

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The invention relates to memory devices and can be used in information transmission equipment.

Known buffer storage devices with autonomous control ij and 2.

One of the known devices is used to store information represented as groups of decimal numbers separated from each other by the boundary code Щ.

This device contains shift registers and a control circuit for them. The disadvantages of this device are the complexity of the control scheme and the impossibility of rejecting erroneous information in the process of compiling it.

Of the known devices, the closest technical solution to this invention is a buffer storage device with autonomous control, containing shift registers, a reversible counter, and outputs

which is connected to the inputs of the switchboard 2.

A disadvantage of this device is that it ensures that only the correct information (according to the results of the control) is combined, since the operation of the device is controlled without regard to the control signals. However, practice shows that the information supplied to the data transfer equipment (FDA) may contain errors due to both the technological reasons for the process of its collection and preparation, and failures when entering monitored information into the FDA.

Thus, erroneous information enters the channel along with the correct one, which reduces the reliability of the transmitted information. In addition, the known device can be used.

20 as a buffer device only pl of sequentially incoming information. In cases when the information is received in a parallel form, that with

Data transmission most often has a source, it is necessary to increase the volume of equipment. These consoles reduce the reliability of the device.

The purpose of the invention is to increase the reliability of the device.

This del is achieved by the fact that the device contains an additional decoder and switches, the information inputs of the first switch, the inputs of the additional extender are connected to the outputs of the respective shift registers, the output of the additional decoder is connected to one of the inputs of the reversible counter and the first control input of the first switch, the second control input of which is connected to the output of the decoder of the state of the reversible counter and one to the inputs of the second switch, the other inputs of which are connected us with one of: the device input and output - with the control inputs of the shift registers.

The drawing shows a block diagram of the proposed device.

The device contains the shift registers 1, the information inputs of the others are the inputs of the device, and the outputs are connected to the inputs of the additional decoder 2, which serves to determine. laziness of the combination of the boundary code, and the first commutator 3.

. The output of the decoder 2 is connected to the read input of the reversible counter 4 and to the first control input of the switch 3. The write input of the reversible counter 4 is the control input of the device, and the outputs are connected to the inputs of the decoder 5, which serves to decrypt the zero state of the reversible counter. The output of the decoder is connected to the second input of the switch 3 and the control input of the second switch 6. The output of the switch 6 is connected to the control inputs of the shift registers -1, and the other two inputs are connected to the inputs of the device.

The device works as follows. In the initial state, the reversible counter 4 and the shift registers 1 are set to the zero position, and the switch 6 provides the synchronization of the register control clock 1 from the information reading device signals (not shown). From the outputs of the shift registers I, through the switch 3, the code Empty is read.

Information from the device, starting with the boundary code, bitwise is written into shift registers I, the first bit into the first register, the second

bit d - in the second register, etc. At the time of the appearance of the second boundary code, which indicates the end of the first message, provided that the registers are correctly recorded in registers

this time information, the input of the reversible counter 4 from the control device (not shown) receives a signal recording in one unit. With the arrival of the boundary code after

for each subsequent correct message, the content of the up / down counter 4 is incremented by one. If an error is detected, the appearance of the boundary code is not accompanied by a fiofys signal from the control device, i.e. the contents of the reversible counter 4 remain unchanged:.

After filling the shift registers 1, a boundary appears at their outflows

the code that is fixed by the decoder 2, the signal from which is fed to the read input of the reversible counter 4, reducing its content by one, and confirms the permission to read the

information from the registers through the switch 3 in the ADF. Thus, the contents of the reversing counter 4 corresponds to the number of valid messages in shift registers 1, not yet

read in ADF.

In the case of writing to the shift registers 1 a message containing an error, after reading the last correct message from them in the ADF, the reversible counter 4 will be in the zero state.

In this case, the signal from the decoder 5 will go to the input of the switch 3, which from this moment will issue the Waiting service code in the ADF, allowing not to interrupt the transmission, i.e. eliminates the repetition of the entry procedure after the elimination of the detected alert (call, phasing, etc.). In addition, since the moment of error detection is stopped by the reader, the same signal through switch b ensures the synchronization of register control cycles from the ADF signals.

After eliminating the error, the information is again entered into shift registers 1, starting with the rejected message, and not from the beginning of the array, which would be necessary if the transmission was interrupted. D) and when the output of the registers I of the boundary code of the first correct message, the signal from the decoder 5 through the switch 6 onsTTb ensures synchronization of the control cycles of the registers from the clock signals; switch 3. Thus, the described device provides an increase in the reliability of the transmitted information by eliminating the reading of erroneous messages without interrupting the transmission. It should be noted that the use of only one reversible counter for controlling registers with a significantly simplified decoder of its state made it possible to obtain the indicated effect even with a certain decrease in the equipment volume. The buffer storage device with autonomous control, containing 736 shift registers, a reversible counter, in its IXOD, are connected to the inputs of the decoder, characterized in that, (With the increase of reliability of the device, it contains an additional decoder and switches, and the information inputs of the first commentator and the inputs of the additional decoder are connected to the outputs of the respective shift registers, the output of the additional decoder is connected to one of the inputs of the reversible counter and the first control The first control input, the second control input of which is connected to the output of the decoder and one of the inputs of the second switch, the other inputs of which are connected to one of the device's inputs, and the output to the control inputs of the shift registers. during examination 1. US patent N9 3469О85 l. (and C of C 7/00, 1969. 2. Patent of Great Britain N9147: 21O, class Q C of C. 7/00,. 1977 (prototype) ...

Claims (1)

Formula of the invention Buffer storage device with autonomous control, containing 763973 6 shift registers, a reversible counter, the outputs of which are connected to the inputs of the decoder, characterized in that (in order to increase the reliability of the device, it contains an additional decoder and switches, and the information inputs of the first switch and the inputs of the additional decoder are connected to the outputs of the corresponding 10 shift registers, the output of the additional decoder is connected to one of the inputs of the reverse counter and the first · control input of the first switch, the second control input 15 of which is connected to ode decoder and one of the inputs of the second switch, the other inputs of which soediyeny with one of input devices, and output - to the control inputs re20 giste shift. . Sources of information taken into account during the examination 1. US patent No. 3469085, cl. 11 C 7/00, 1969. 25 2. British Patent No. 147 £ 210, cl. Q 11 C 7/00, .1977 (prototype) .. ’ VNIIIPI Order 6292/45, Circulation 662 Subscription Branch of PPP 'Patent', Uzhhorod, Project 4,