SU428383A1 - CONTROL DEVICE OF DIGITAL COMPUTER MACHINE - Google Patents

Description

I

The invention relates to computational engineering, and the design of digital computing devices and systems can be used.

A control unit is known; a digital computing machine, a compiler, its counting commands, an instruction register, an address register, X and Y address decoders, address keys, drivers, a memory block, an iRem register, a recording unit, blo. to memory. and register serial commands.

To increase the speed and save the equipment, the proposed device contains a unit for building subsequent commands, the inputs of which are connected respectively to the output of the register of a series of commands and the second l to the third inputs of the device, and its outputs are connected respectively to the first and second inputs of the register reg.

The scheme of the proposed device shown in the drawing.

The device includes a command counter}, a register of 2 addresses, a decoder of 3 addresses X, a decoder of 4 addresses K, address keys 5, address forwarders, and 6, a zaguiuiyu unit 7, readout amplifiers 9, receiving register 10, register 11 series of commands, block 12 of the first-generation form of the third order, consisting of the circuit 13

porass d; gogo comparison, ddv | I1gayuyogo register / - #, schemas / 5 soviadeni, schema 16 "NOT, schema / 7th supervised, register 18 kamand. The first 1 input of the device 19 is connected to the input of the counter / command for supplying the signal Id to the code recorded by the s counter. The first output of the Device is connected to the output of the command register 18, the output of the reception register 21 is the second output of the device, and the inputs 22 and 23 of the matching circuit 15 and / 7 are the second 1 and the third inputs of the device, which receive signals from the control micro-command generation unit.

For each regular cycle, the code of the previous command is recorded in register 18. The code of the series of commands from the count / command output is input to the register of the 2 address, and the contents of the / 5 input is added to the input of the device / 5. unit. The outputs of the low and high bits of the address code are decoded, respectively, by the L and 4 address decoders, which determine the location of the cell and the type (in x and y coordinates) in block 8 pa.m.p. corresponding to this code. The output sigals of the decoders 3 and 4 are fed to the INPUTS of the address form 6 of the switches 6 and the keys 5, the output current of their reading in the selection cell of the block 8, which stores the code of the command series. The output signals of block 8 are amplified by read amplifiers 9 and are fed to the input of register 10. Next, the received code is regenerated into a cell of block 8, from which it is fed to the input of register 11. Preliminary to the lower bit of register 14 via a special input ( not shown in the drawing) the unit is recorded. Pr.i set, ke code in .register /./ scheme ./5 one-by-one comparison proiz1BO | Dit compare codes written in {registers 11 and .14. In the absence of "one unit in the lower order of de reg. 11, circuit 13 1, the output of the non-sync signal is output, which through the circuit NOT 16. Is fed to the input of circuit 15 co-Bin and the children. the signal is a single-shift microcommand of a bitwise shift (incident 22). OpiJi this "unit shifts to the next bit of register 14. Sdeigi occur before the moment, since the output of circuit 13 did not show a joint signal, indicating that shifting unit 14 of the 14 sovial with" unit in closest to the lower order of the register code / V. The number of this bit, determined by the position of "one in register code 14," is the bit number of the address code of the previous command, the value of which must be inverted to obtain the code of the address of the subsequent command. For this, when the signal from the input 23 to the input of the circuit 17 is received, a control signal (input 22) is received, through which the value of the bit received from the output of the relaStra 14 is inverted in command register 18. This ends the cycle forming the first team. The iPa6oTa device takes the form of the following commands of the series in the same way until the unit in periicTpe 14 does not move to the most senior category. In this way, it is cyclically transmitted again to the lower register register 14, simultaneously being a call signal for the following code forming a series of commands, etc. Subject of the invention A control unit of a digital computer containing a command counter, the first input of which is connected to the output of the command register and the first (device output, the second input is with the first input of the device, and the output is connected with the input of the address register connected via address and X decryptors, address keys and drivers to the address inputs of the block and whose output through the read amplifiers is connected to the input of the receiving register, the first input of which is connected via the recording generation unit to the information input of the memory block, and the second and third inputs are connected to the second output of the device by the register input of the command series, different By the fact that, in order to increase speed and reduce equipment, the OIO contains a subsequent command generation unit, the inputs of which are connected respectively to the register output of the command series and the second and third inputs of the device, its outputs are connected to first and second inputs coma register "d.