SU1596463A1 - Device for converting equilibrium binary code to full binary code - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital information transmission systems and computing systems. The purpose of the invention is to increase the speed of the device. The device contains a software-time unit, the first output of which is connected to the control input of the register, the information input of the register is the input of the device, the outputs of the register are connected to the first inputs of the corresponding AND elements of the first group, the outputs of which are connected to the corresponding inputs of the OR element and the AND elements of the second group . Pulse distributors, code converters, delay elements, memory block and adder are additionally introduced into the device. 1 il.

Description

The invention relates to telecommunications and can be used in digital information transmission systems and computing systems.

The aim of the invention is to improve the speed of the device.

The drawing shows a block diagram of the device. The device contains a shift register 1, an encoder 2, made on the first, second distributor 3, 4 pulses, AND 5.1-5.p., 6.16 .k elements of the first, second groups, first, second converter 7, 8 code, OR element 9 and the first edem. 10 delay, the second delay element 11 is the software-time block 12, memory block 13 and cyfiMaTOp 14. For example, the value of the source code, weight (i.e., in each code combination of the original equilibrium code of five characters are single and two are zero). Then (the combination of source code code combinations will be 00111, 01011 01101, 01110, 10011, 10011, 10101 ,, 10110, 11001, 11010, 11100. Consider the combination 00111. We assume that in this combination, the units are renumbered from right to left and all units are located on its combination of, for example, 10101 first unit is at the zero position, the second one is at the first position, the last third is one at the second position. Thus, each of the original combinations can be uniquely represent single symbols with their positions.This forms an aggregate of not only H-valued, but 1C-valued (H-K + O-ary combinations (a, a., a)): 000, 100, 110, 111,200 210, 211, 222. Analysis of this aggregate shows that its structure corresponds to the structure of the positional number system, for which the number of each number (in this case it is advisable to speak not of a combination, but of numbers) is defined as jT, -Uj- / where. Cji is the number of combinations of a to b; j is the number of the unit in the initial binary code combination of the new code; . {the digit of the corresponding number of the resulting number system. However, due to the fact that a - j i, where i. - the position number in the combination of the original equilibrium code (numbering from right to left and starting from position 1, ending with position H), in which the j-unit is located. Expression (1) can be represented as: The last expression defines the algorithm for the operation of a new device. And depending on the degree in which the number system will be presented the values of j, i ,. K, as well as the number of combinations and the sum, respectively, will be made the transition from the binary combination of the equilibrium code to the combination (number) of this number system. The encoder works as follows. The software-time unit 12 generates and outputs the signal of the initial installation in the distributors 3, 4 pulses. On the first inputs of distributors 3, 4 single signals are constantly present. The output signals of the distributors 3, 4 are fed to the second inputs of the And 5, 6 elements. The first inputs of the And 5 elements receive the output signals of the register 1. For example, a register 10101 of the equilibrium code, i.e. On the first, third and fifth outputs of register 1 there are single signals. Then, at the output of the first element And 5.1, a single signal is formed, which is fed to the input of the element OR 9 and the converter 7 of the code that converts the input binary positional code into the output binary full code. as a result, a combination 00001 of the position binary code is present at the inputs of the converter 7, which is converted into the combination 001 of the full binary code. This combination matches. The input unit signal of the element OR 9 passes to its output and participates in the following transformations. First, it is applied to the first, the inputs of the And 6 elements. At the same time, both the inputs of the And 6.1 element have single signals, and a single signal is formed at its output. ; A combination of the 001 positional code is formed at the inputs of the converter 8, and a combination of the binary full code 0 is formed at its outputs. This combination defines a binary code. Secondly, it brings the memory unit 13 back to its original state. In the adder 1 And this signal allows the addition of the corresponding codes. Thirdly, it is delayed for a certain time in the delay element 10, and, when placed at the input of the distributor 4 pulses, changes the output state of the latter. As a result, a single signal | is no longer received from the first, but from the second output of the distributor 4. After that, at the appropriate time, a control signal is supplied from the software-time block 12 to the distributor 3, which, by changing the output state of the distributor 3, leads to forming a single signal at its second output. . There is no single character in the second memory cell of the register 1, so the output of the And 5 elements is a zero combination, and the output of the And 6 elements also contains a zero combination. The output combinations of the transducers 7, 8 are also zero. At the same time, the control signal from the output of the element OR 9 to the output of the encoder 2 is not available. After that, at the appropriate time, a third control signal is supplied to the control input of the distributor of 3 pulses from the output of block 12, which causes a single signal to be generated only at the 3rd output of distributor 3. Since in the 3rd cell The memory of the register t has a single signal, in the code of the third element And 5.3 a single signal is formed. At the inputs of the converter 7, a combination 00100 will be formed, which will be converted into the output combination 011, corresponding to the binary code of the position number of the second single character of the original combination. At the same time, the output unit signal of the And 5.3 element passes the MEHT OR 9 and enters the output of the encoder 2, connected to the memory block 13 and the adder 14, to the first inputs of the And elements 6 and to the input of the delay element 10, which leads to the appearance of a single signal on the output of the second element And 6.2. At the output of the second element 6.2, a single signal appears, so that at the input of the converter 8 a binary position code 010 is formed, which is converted into the binary output code of the converter 8 corresponding to the binary code of the number of the second unit in the original combination. After that, a single signal appears at the output of the delay element 10, which, acting on the distributor 4 pulses, leads to the appearance of a single signal at its third output. Further, in accordance with the time point, the output control signal of the program-time block 12 acts on the distributor 3 and a single signal is output from its fourth output. In the fourth memory cell of register 1, there is no single signal, therefore the output signal of the converter 7 is zero, the zero signal is also the output signal of the converter 8. There is no control signal at the output of the OR 9 element. At the appropriate time, a single signal appears at the last, fifth output of the distributor of 3 pulses (the number of outputs of the distributor 3 is determined by the value of the input combination of the equilibrium code). Due to the fact that a single signal is stored in the five memory cell of register 1, a single signal is generated at the output of the fifth slider AND 5.5, which determines the input combination 10,000 for the converter 7 and passes to the output of the element OR 9. In the converter 7, input binary combination in the combination 101 corresponding to the binary position number of the third unit symbol of the original combination. The output signal of the element OR 9 is fed to the output of the encoder 2, to the input of the delay element 10, to the corresponding inputs of the elements AND 6. In this way, the output of the last, third element AND 6.3 is a single control signal that goes to the output of the encoder 2,

nen with the input element 11 delay. In addition, this single signal determines the input binary combination 100 of the converter, which converts it into a combination 011, corresponding to the binary code number of the third unit symbol of the original combination, which is output to the corresponding output of the encoder 2.

 Next, a control signal appears at the output of the delay element 10, which is not perceived by the valve 4.

At the appropriate point in time, the control signal from the program-time unit 12 causes the distributors 3, 4 of the pulses to be reset, and the device is ready for processing the next initial combination of the input register.

Upon receipt of the binary codes ii and j at the corresponding inputs of block 13 there, a binary code is read from the corresponding memory cell, which determines the value of the number of combinations from (i - 1) to j. If the weight of the original combination is equal, then the first at the output of block 13 is the Ct code. , the second - С, ,, the third f Э f

"3- For example, for the original combination

10101 this sequence is 0000, since

g g

C. O, -1 1- "

the second is 0001, since

R

5- C 1,

The last one is 0010, because

g g C

4. fj-r y-i 4

The adder 14 is gated by the output signal of the IL element 9 and performs the summation of binary codes from the output of the block 13 of the memory.

For example, if the output codes of the unit are 13 0000, 0001, 0100, then the control signal from the output of the delay element at the output of the adder 14 generates the code 0101 of the sum of the input codes and is output to the device.

A device for converting binary equilibrium code works as follows.

: The initial, to be converted binary constant code weight combination is fed to the input of the device, starts the program-time block 12 and is stored in register 1.

At a certain point in time, as a result of the action of control signals, in the block, in block 12, encoder 2 / sequentially generates at the outputs of binary codes the sequence numbers of the single characters and their positions in the original combination. Here, each pair of codes (code i) of the unit position and code j of the unit number sequence is gated. the control signal of the encoder 2 and is fed to the corresponding inputs of block 13, which you gives the binary code of the number of combinations of (ij-1) through j to the input of the adder 14, In the adder 14 at the times determined by the gates of the encoder 2 pulses, the binary codes fed to the adder 14 from block 13. The result code is gated by the encoder 2 signal after its I delay in element 11. The sum code 0101 (for the considered example) is output by the gate signal to the device.

Then, all the units of the device are reset, and the next combination of the equilibrium code is converted.

Claims (1)

DEVICE FOR CONVERGENCE-. NIA BINARY BALANCED CODE INTO FULL BINARY CODE containing pro-. the time-gram block, the first output of which is connected to the control input of the register, the information input of the register is the input of the device, the outputs of the register are connected to the first inputs of the corresponding AND elements of the first group, the outputs of which are connected to the corresponding inputs of the OR element, and the AND elements of the second group differing in that in order to improve the performance of the device, pulse distributors, code converters, delay elements, a memory block are entered into it and the adder, the output of the element OR is connected to the first control inputs of the memory block, the adder, the first inputs of the AND elements of the second group and the input of the first delay element, the outputs of the first and second distributions2 pulses are connected respectively to the second inputs of the corresponding elements of the first and second groups, the output of the first delay element is connected to the first control input of the second pulse distributor, the inputs of the first code converter are connected to the outputs of the corresponding elements of the first group, outputs of the elements of the second group are connected to the corresponding inputs the second code converter, the outputs of the first and second code converters are connected respectively with the first and second address inputs of the memory block The output of which is connected to the information input of the adder, the input of the second delay element is connected: To the output of the last element AND elements of the second group, the output of the second delay element is connected to the second control input of the adder, the input of the software-time block is connected to the input of the device, the second-fifth outputs are programmed -time block connected respectively to the control input of the first pulse distributor, the second control inputs of the second pulse distributor, the memory unit and the third control input adder, the adder output is the output of the device. 81), „, 1596463