RU102407U1 - CPU COMPUTER - Google Patents

Abstract

 A computer processor containing a control node, an operational node, the first inputs of the control node are the inputs of the processor, the second group of inputs of the control node is connected to the first outputs of the operational node, the outputs of the control node are connected to the first inputs of the operational node, the second inputs of which are data inputs, and the second outputs are data outputs, characterized in that it further comprises an operation code decoder, a clock, a control unit, a first switch, a second switch, a third mutator, instruction counter, shift counter, address register, number register, adder register, additional register, additional code register, adder, control unit, control memory, logical operations and control unit, including mod2 logical addition unit, invert unit, logical unit addition, a logical multiplication block, a functional correction circuit for performing arithmetic operations, a functional correction circuit for performing an OR operation, a functional circuit for generating mandrels during the operation AND, the functional diagram of the formation of the corrections during the shift operation, the delay element, the first block of disambiguity elements, the second block of discontinuity elements, the third block of discontinuity elements, the first block of OR elements, the second block of OR elements, the coding block, the first block of And elements , the second block of elements And, the element And, the outputs of the exchange device are connected to the first input of the control unit and to the first input of the second switch, the second inputs of which are connected to the outputs of the memory

Description

A memory device with double error detection [1] is known, comprising a memory node, characterized in that it further comprises an input coding unit, an output coding unit, a comparison unit, a block of AND elements, an AND element, an OR element, an input to set the device to zero, write input, read input, address inputs, information inputs, synchronization input, information outputs, “error” signal output, and the input to the zero state, write input, read input, address inputs, are connected respectively to the first, second, third and fourth inputs of the memory node, the information inputs are connected to the fifth inputs of the memory node and to the inputs of the input coding block, the outputs of which are connected to the sixth inputs of the memory node, the synchronization input is connected to the seventh input of the memory node and to the first inputs of the block of elements and AND element, the first outputs of the memory unit are connected to the inputs of the output coding unit and to the second inputs of the block of elements AND, the outputs of the output coding unit are connected to the first inputs of the comparison unit, to the second inputs of which these are the second outputs of the memory node, and the outputs are connected to the inputs of the OR element, the output of the OR element is connected to the second input of the AND element, the outputs of the block of AND elements are information outputs of the device, the output of the AND element is the output of the “error” signal.

The disadvantage of this device is the limited scope of its application, since it allows to ensure the reliability of the operation of only computer storage devices.

The closest in technical solution is the processor [2], containing the control unit, the operating unit, the first group of inputs of the control unit is the inputs of the processor, the second group of inputs of the control unit is connected to the first outputs of the operation unit, the outputs of the control unit are connected to the first inputs of the operation unit, the second whose inputs are data inputs, and the second outputs are data outputs.

The disadvantage of this device is the low reliability of the processor, as it does not detect errors when performing arithmetic and logical operations (information converters: adder, shift registers, devices for performing logical operations).

The purpose of the utility model is to increase the reliability of the processor by detecting and correcting errors that occur.

This goal is achieved in that the processor containing the control unit, the operation unit, the first inputs of the control unit are the inputs of the processor, the second group of inputs of the control unit is connected to the first outputs of the operation unit, the outputs of the control unit are connected to the first inputs of the operation unit, the second inputs of which are inputs data, and the second outputs are data outputs, characterized in that it further comprises an operation code decoder, a clock, a control unit, a first comm tator, second switch, third switch, instruction counter, shift counter, address register, number register, adder register, additional register, additional code register, adder, control unit, control memory, logical operations and control unit, including mod2 logical addition unit , invert block, logical addition block, logical multiplication block, correction correction functional diagram for performing arithmetic operations, correction correction functional diagram for performing the OR operation, f the functional correction scheme for the operation And, the functional scheme for the correction for the shift operation, the delay element, the first block of discontinuity elements, the second block of discontinuity elements, the third block of discontinuity elements, the first block of OR elements, the second block of OR elements, the coding block, the first block of elements AND, the second block of elements AND, element AND, the outputs of the exchange device are connected to the first input of the control unit and to the first input of the second switch, the second inputs of which They are connected to the outputs of the storage device, the first outputs of the second switch go to the input of the exchange device, the second outputs go to the input of the storage device, and the third outputs are connected respectively to the first inputs of the command counter, shift counter, number register, adder register, additional register, additional register code, to the inputs of the descrambler of the operation code, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register, the third input of the control unit is connected to the outputs of the decoder of the operation code and the fourth input is connected to the outputs of the clock generator, and the fifth input is connected to the first output of the control memory, the first output of the control unit is connected to the input of the control memory, the first outputs of which are connected to the first inputs of the control unit, the second output of the control unit is connected to the second input of the first switch, the third and fourth inputs of which are connected respectively to the outputs of the address register and command counter, and from the second output from below the address of the memory cell of the storage device, the third output of the control unit is connected respectively to the second inputs of the control unit, to the second inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch , to the third group of inputs of the second switch, to the first group of inputs of the block of logical operations and control and is the output of the clock pulses, the second, third, fourth fifth outputs of the control pa they are connected to the third and fourth fifth and sixth inputs of the control unit, while the second output is connected to the fourth input of the second switch, and the third, fourth and fifth outputs of the control memory unit are connected respectively to the third, fourth fifth and sixth inputs of the command counter, shift counter, register address, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the first group of inputs of the block operations and control and are the outputs of control signals, read signals, write signals, signals to set the devices to zero, the sixth output of the control memory unit is connected to the fifth input of the control unit, the outputs of the number register, adder register, additional register, additional code register are connected to to the second inputs of the third switch and to the fifth inputs of the second switch, the shift counter output is connected to the sixth inputs of the second switch, the first outputs of the third switch are connected respectively to the inputs of the adder and to the second inputs of the logical operations and control unit, the outputs of the adder are connected to the third inputs of the logical operations and control unit, the second, third, fourth, fifth, sixth, seventh and eighth outputs of the third switch are connected to the fourth, fifth, sixth , seventh, eighth, ninth and tenth inputs of the logical operation and control unit, the outputs of which are connected to the seventh, eighth and ninth inputs of the second switch.

Figure 1 presents a block diagram of a utility model; figure 2 is a functional diagram of a block of logical operations and control; figure 3 is a functional diagram of a control unit; in Fig.4 is a functional diagram of the formation of the amendment when performing arithmetic operations in Fig. 5 is a functional diagram of forming an amendment when performing a shift operation.

The computer processor (Fig. 1) comprises a control unit 1, an operation unit 2, an operation code decoder 3, a clock pulse generator 4, a control unit 5, a first switch 6, a second switch 7, a third switch 8, a command counter 9, a shift counter 10, register 11 addresses, register 12 numbers, register 13 adder, register 14 additional, register 15 additional code, adder 16, block 17 of logical operations and control, block 18 control, control memory 19, from the first 20 to tenth 29 inputs of block 18 of logical operations and control, from the first 30 to the third 32 outputs bl 17 logical operations and control, inputs 33 of the exchange device, inputs 34 data from the storage device, output 35 to the exchange device, output 36 address of the storage device, outputs 37 data to the storage device, outputs 38 clock pulses, outputs 39 for control signals, outputs 40 for a read command, outputs 41 for write signals, outputs 42 for zero signals.

Block 17 of logical operations and control (figure 2) contains block 43 of logical addition by mod2, block 44 of inversion, block 45 of logical addition, block 46 of logical multiplication, functional circuit 47 of the correction when performing arithmetic operations, functional circuit 48 of forming the correction when performing the OR operation, the correction generating circuit 49 when performing the AND operation, the correction generating circuit 50 when performing the shift operation, the delay element 51, the first block 52 of the ambiguity elements, the second block 53 of the elements of disambiguation, the third block 54 of the elements of discontinuity, the first block 55 of the elements OR, the second block 56 of the elements OR, the first block 57 of the coding, the second block 58 of the coding, the first block 59 of the elements And, the second block 60 of the elements And, the element 61 And, a group of 62 elements OR.

The control unit 18 (FIG. 3) comprises an encoding circuit 63, an error detection circuit 64, an OR element group 65, an AND element 66.

Functional diagram of the correction when performing arithmetic operations (figure 4) contains the first element 67 AND, the second element 68 AND, the third element 69 AND, the fourth element 70 AND, the fifth element 71 AND, the sixth element 72 AND, the first element 73 OR, the second element 74 OR, third element 75 OR, fourth element 76 OR, fifth element 77 OR ..

Functional diagram of the correction during the shift operation (Fig. 5) contains the first discontinuity element 78, the second discontinuity element 79, the third discontinuity element 80, the fourth discontinuity element 81, the first element 82 And, the second element 83 And, the third element 84 And, the fourth element 85 AND, fifth element 86 AND, sixth element 87 AND, first element 88 OR, second element 89 OR, third element 90 OR, information inputs 29, input of the control signal shift right, input control signal shift left.

The outputs 33 of the exchange device are connected to the first input of the control unit 5 and to the first input of the second switch 7, the second inputs of which are connected to the outputs of the storage device, the first outputs of the second switch 7 go to the input of the exchange device, the second outputs go to the input of the storage device, and the third outputs respectively connected to the first inputs of the counter 9 commands, counter 10 shifts, register 12 numbers, register 13 adder, register 14 additional, register 15 additional code, to the inputs of the decoder 3 code opera to the second inputs of the control unit 5, to the first input of the first switch 6, the first output of which is connected to the first input of the address register 11, the third input of the control unit 5 is connected to the outputs of the decoder 3 operation code, and the fourth input is connected to the outputs of the clock generator 4 and the fifth input is connected to the first output of the control memory 19, the first output of the control unit 5 is connected to the input of the control memory 19, the first outputs of which are connected to the first inputs of the control unit 18, the second output of the control unit is connected to the second the first switch 6, the third and fourth inputs of which are connected respectively to the outputs of the address register 11 and the command counter 9, and the memory cell address is taken from the second output, the third output of the control unit 5 is connected respectively to the second inputs of the control unit 5, to the second inputs counter 9 commands, counter 10 shifts, register 11 addresses, register 12 numbers, register 13 adders, register 14 additional, register 15 additional code, to the first group of inputs of the third switch 8, to the third group of inputs the second switch 7, to the first group of inputs of the block 17 of logical operations and control and is the output of the clock pulses, the second, third, fourth fifth outputs of the control memory 19 are connected to the third and fourth fifth and sixth inputs of the control unit 18, the second output is connected to the fourth input the second switch 7, and the third, fourth and fifth outputs of the control memory block 19 are connected respectively to the third, fourth fifth and sixth inputs of the instruction counter 9, counter 10 shifts, register 11 addresses, register 12 numbers, register 13 s umator, register 14 additional, register 15 additional code, to the first group of inputs of the third switch 8, to the third group of inputs of the second switch 7, to the first group of inputs of the block 17 of logical operations and control and are the outputs of control signals, read signals, write signals, signals setting the devices to zero, the sixth output of the control memory unit 19 is connected to the fifth input of the control unit 5, the outputs of the register 12, register 13 of the adder, register 14 additional, register 15 additional to yes, they are connected to the second inputs of the third switch 8 and to the fifth inputs of the second switch 7, the output of the shift counter 10 is connected to the sixth inputs of the second switch 7, the first outputs of the third switch 8 are connected respectively to the inputs of the adder 16 and to the second inputs of the block 17 of logical operations and control, the outputs of the adder 16 are connected to the third inputs of the block 17 of logical operations and control, the second, third, fourth, fifth, sixth, seventh and eighth outputs of the third switch 8 are connected to the fourth, fifth, sixth, seventh, eighth, ninth m and tenth input logical operation unit 17 and control outputs of which are connected to the seventh, eighth and ninth second inputs of the switch 7.

The processor includes two main devices: the control node 1 and the operational node 2.

The control node 1 coordinates the actions of the nodes of the operational node 2 with each other and with other computer devices, and also performs a set of operations including memory access commands. It generates control signals in a certain time sequence, under the action of which the required actions are performed in the nodes of the operational node 2.

Each such elementary action performed in the operating unit 2 during one clock period is called microoperation.

In certain clock periods, several microoperations can be performed simultaneously. Such a set of simultaneously performed microoperations is called a microcommand, and the entire set of microcommands designed to solve a specific problem is called a microprogram.

The total time interval during which sampling, storage and conversion of one command into a set of control signals takes place is called the operation cycle of control unit 1.

Thus, the control node 1 converts the command into an appropriate set of control signals and provides:

reading a command located in the next memory cell;

decryption of the operation code (command);

finding operands (numbers) at the specified address contained in the command;

ensure the issuance of control signals to the operating unit to perform actions on them specified in the command operation code.

In this case, the firmware control unit 1 is used, in which the microcommands are stored in the control memory 19.

In this case, the words representing the commands are stored in memory in sequentially numbered cells, which allows you to form the address of the next command by adding a unit to the address of the previous command, while the word consists of several parts: for example, an operation code indicating the type of operation and addresses of numbers, over which the corresponding operation should be made.

The decoder 3 operation code for the selected from the RAM command determines the number of the required firmware in the control memory 19.

The clock generator 4 is designed to generate clock and clock pulses.

The counter 9 commands is designed to generate the address of the memory cell of the next command, by natural sampling, i.e. adding to its contents a unit.

The register 11 addresses is designed to generate the address of the memory cell when the commands conditional or unconditional jump return.

The control unit 5 is designed to determine the address of the next microcommand in the control memory 20, generate the address of the next command (control the operation of the first switch 6), coordinate the work (issuing clock pulses) of the devices of the processor 1.

The control memory 19 is a permanent storage device and is designed to issue (depending on the operation code) the issuance of control signals (control signals, read signals, write signals, set signals to zero state) to the functional units of the processor. Moreover, the memory word contains information bits (for control signals) and control bits formed on the basis of the proposed coding method.

The control unit 18 (Fig. 3) is designed to detect and correct errors that occur when reading information from the control memory 19. In this case, when reading the microcommands, the encoding circuit 63 generates control bits of the received code set whose values are bitwise compared with the accepted values of the control bit circuitry 64 error detection. If the information does not match at the output of the OR element 65, an error signal is generated that passes through the second switch to the inputs of the exchange device.

The operation node 2 is designed to perform arithmetic and logical operations and includes (Fig. 1) a shift counter 10, a number register 12, an adder register 13, an additional register 14, an additional code register 15, an adder 16, a control unit 18.

The counter 10 shifts is designed to count the number of shifts when performing operations of multiplication and division, the number of shifts of intermediate results and normalization.

The address register 11 is a memory register and is intended to store the address of the next command.

The 12th register is a memory register and is intended for storing operands when performing arithmetic and logical operations (storing the multiplicable when performing the multiplication and divisor when performing the division operation).

The register 13 of the adder (accumulator) is a shift register (to the right when performing the multiplication operation and to the left when performing the division operation), and is intended to store the divisible high order bits of the multiplication result.

Note that when performing the division operation, the control unit 5 analyzes the value of the sign discharge of the register 12 of the number and register 13 of the additional adder.

The additional register 14 is a shift register (to the right - when performing the multiplication operation and to the left - when performing the division operation), and is intended to store the multiplier and the least significant bits of the multiplication result when performing the multiplication operation and the division result when performing the division operation).

Note that when performing the multiplication operation, the control unit 5 analyzes the low-order value of the additional register 14.

The register 15 of the additional code is a memory register and is intended to store a negative number in the additional code (when performing the subtraction and division operations).

The adder 16 is a parallel n-bit adder and is designed to perform the operation of adding numbers.

Block 17 of logical operations and control (figure 2) is designed to detect and correct errors that occur when performing arithmetic and logical operations.

The correction formation scheme when performing arithmetic operations (figure 4) is intended to form the correction when performing arithmetic operations.

So, when performing arithmetic operations, the result of the sum from the output of the adder 16 is fed to the second input 21 of the block 17 of logical operations and control. At the same time, the values of the information bits of the terms go to the third input 22 of the block 17 of logical operations and control, while the correction circuit 47 during arithmetic operations generates a carry vector C ₀ , C ₁ ... C _n .

Suppose you want to add two three-digit numbers (there is no transfer to the least significant bit): A = 001 01 and B = 011 10. In this case, the And element 67 opens, which provides a single signal value C ₁ . In turn, the unit value of the second category of the second term and the unit value C ₁ will ensure the opening of element 71 I. As a result, we learn the value of the transport vector: C ₀ = 0; C ₁ = 1; C ₂ = 1.

The value of this vector through the first block 55 of the OR elements (FIG. 2) is input to the first coding block 57, which generates the correction value P in accordance with the selected information encoding method: p ₁ = C ₀ ⊕C ₁ ; p ₂ = C ₁ ⊕C ₂ , i.e. P = 10.

When performing an arithmetic operation with respect to information bits, we obtain the result S = 100. The mod2 addition of the values of the control bits received at the input of the first block 52 of discontinuity elements (input 29 of the block of logical operations and control) will give the result 11. The bitwise addition of mod2 of the obtained value of the control bits 11 with the correction value 10 by the second block of 53 elements of the discontinuity will give the correct value of the control bits 01 relative to the arithmetic sum of 100.

Indeed: r ₁ = у ₁ ⊕у ₂ = 0; r ₂ = у ₂ ⊕у ₃ = 1.

Comparison of the control bits generated relative to the summation result of the second coding unit 58 with the value of the transmitted control bits, taking into account the correction by the third block 54 of unequal elements, will give a zero result, which indicates that there is no error.

When monitoring the operations of shear, the correction formation scheme when performing the shear operation (Fig. 5), the information vector for calculating the corrections are calculated in accordance with the expressions: when shifting to the right x ₁ = y ₁ ¹ ⊕у ₃ ; x ₂ = y ₂ ⊕y ₃ ; x ₃ = y ₂ ⊕y ₁ ; when shifting to the left: x ₁ = y ₃ ⊕y ₂ ; x ₂ = y ₂ ⊕y ₁ ; x ₃ = y ₃ ¹ ⊕y ₁ .

In the absence of transfers from the younger (senior) triad, the correction vectors are obtained from the expressions: x ₁ = 0⊕u ₃ ; x ₂ = y ₂ ⊕y ₃ ; x ₃ = y ₂ ⊕y ₁ ; when shifting to the left: x ₁ = y ₃ ⊕y ₂ ; x ₂ = y ₂ ⊕y ₁ ; x ₁ = 0⊕y ₃ .

Suppose you want to perform a right shift operation on the contents of 11010. (results of private products) of register 13 of the adder). Then, at the output of the first element of ambiguity 78 (Fig. 5), we have a single value, at the output of the second element 79 of ambiguity we have a zero value, and at the output of the third element 80 of ambiguity we also have a single signal value, i.e. we have a vector: 101. The encoding of this vector by the first block 57 by the selected method will give the correction value: 11. When shifting the information to the right, we will teach the value of information bits 011 for which the value of the control bits corresponds to the value 01.

The bitwise addition of mod2 by the second coding unit 53 (FIG. 2) of the initial value of the control bits 10 with the correction value 11 will give the result 01, which corresponds to the correct value of the control bits when shifting the information to the right.

When the information bits of the example in question are shifted to the left, we get the result: 10010. The information vector for calculating the correction with respect to the initial information corresponds to: 010 (we have a zero value of the signals at the outputs of the second element 80 of ambiguity, a single value of the signal at the output of the third 81 elements of ambiguity, and zero signal value the output of the fourth disambiguation element 80. At the output of the first coding unit 57, we have a correction value of 11. When left-shifting the source information, we have a value of 100 for wherein correct value check bits equals 01. bitwise addition of the initial values of check digits 10 with a correction value 11, the second block 53 nonequivalence elements give the correct value of the control bits for left shift operation.

When performing logical multiplication, the value of the vector for calculating the correction to the control bits is carried out by the correction generating circuit 48 when the OR operation is performed by performing the AND operation with respect to the equivalent bits of the terms.

So, for example, when performing an OR operation with respect to information bits and adding control bits in mod2 by the first block 52 of unequal elements (Fig. 2), the numbers A = 00101 and B = 01110 have the result: 01111. The operation AND with respect to information bits will give the value of the vector for calculation corrections: 001. In this case, the correction value is: 10. Then, for the considered example, we have the result: 01101, i.e. we have the correct value of the control bits.

A correction is formed in a similar way when performing logical multiplication, only when the correction vector is formed by the correction formation circuit 49 when performing the AND operation, a bitwise OR operation is performed relative to the same digits of the multiplier and the multiplier.

For operations of logical addition by mod2 by block 43 of addition by mod2 and negation by block 44 of inversion, the formation of an amendment to the control bits is not required.

The values of the control bits generated by the second coding unit 58 with respect to the information bits obtained by performing arithmetic and logical operations are bitwise compared by the third block 54 of discontinuity elements with the transmitted values of the control bits taking into account the correction.

In the absence of errors at its outputs, we have a zero signal value.

The processor starts with the arrival of the "Start" signal at the input group 33 of the inputs of the processor exchange device with peripheral units. By this command, block 5 issues a command to read the contents of the first memory cell from the control memory 19.

The "System Reset" command is located in the first memory cell, which sets the registers and blocks of the processor to the initial state. "1" is written to the 9 command counter, control device 1 issues micro-commands in the following sequence:

1) At the first clock, the micro command signals and the values of the control bits are sent to the output of the control unit 18, where the detection and correction of errors that occur is carried out in accordance with the functional diagram shown in Fig.3.

In this case, when reading the micro-command, the encoding circuit 62 is the formation of the control bits of the received code set.

The error detection circuit 63 performs bitwise comparisons of the generated and transmitted values of the control bits.

In the event of errors, a single signal will appear at the output of the group of 64 OR elements, indicating its presence, which, when a clock pulse arrives at the input of the 65 AND element, is transmitted to the exchange device through the second switch 7.

If there are no errors, the set of microcommands is sent to the input of the counter reading of the instruction 9 and to the input of the write of the address register 11, while the contents of the counter of 9 commands are sent to the address register 11 (or through the first switch 6 to the address inputs of the memory device with a natural selection of commands directly from the counter 9 teams);

2) On the second measure, the unit is added to the contents of the counter of 9 commands - the address of the next command is prepared;

1) On the third clock, the micro command signals are sent to the read input of the address register 11 and to the read input of the contents of the memory cell of the storage device at the specified address. In this case, the command stored in the first memory cell is recorded in the register 12 numbers;

2) At the fourth clock, the micro command signals are sent to the read input of the 12th register, the input of the second switch 7 and to the input of the decoder 3 of the operation code, where they are decoded, after which the control unit 1 proceeds to the second stage of operation.

For example, consider the execution order of one of the commands written in the register on the 12th day after the first four measures.

Let the command for adding the contents of the register 13 of the adder with the number located in the storage device at the address specified in the address field of the register of the 12th number be written in the operation code field of the command for the contents of the 12th register. (when using a unicast command).

The control node 1 thus issues the following microcommands:

3) on the fifth clock, the microcommand signals are fed to the read input of the 12th register, to the input of the second switch 7, the first switch 6, and to the write input of the address register 11 (the address stored in the 12th register is written to the address 11 register, the contents of the 12th register are reset );

4) At the sixth cycle, the microcommand signals are fed to the read input of address register 11, to the input of the first switch 6, to the read input of the storage device and to the write input of the 12th register (the second term is written from the storage device to the 12th register (we assume that the first term already in register 13 of the adder);

5) On the seventh clock, the microcommand signals are fed to the read input of the number register 12 and the adder register 13, while the arithmetic-logic device performs the addition operation and writes the addition result to the adder register 13 as follows.

The result of the sum from the output of the adder 16, is fed to the block 17 of logical operations and control (figure 2), then the device operates in accordance with the example of arithmetic operations above. In this case, the generated values of the control bits relative to the received operation are compared with the transmitted values of the control bits of the third block 54 of the elements of disambiguation (figure 2). If there is no error at its outputs, we have zero signal values. If there is an error and a clock pulse arrives at the output of element 61 AND, a single signal value appears. Information and control bits are removed respectively from the outputs of the first 59 and second 60 groups of elements I.

Similarly, the processor operates when performing logical operations.

8) On the eighth step, the micro-command “End of operations” is issued, the transition to the next operation is carried out, the control unit 5 is initialized and gives permission to start the next command, the address of which is indicated in the counter of 9 commands.

INFORMATION SOURCES

1. Patent for utility model No. 76479 "Memory device with detection of double errors" / Boroday V.E., Tsarkov AN, Osipenko PN, Bobkov SG, Pavlov AA, from o4. 04.04.2008

2. Kalabekov B.A., Microprocessors and their use in signal transmission and processing systems, M .: Radio and communications, 1988, 368 pp. (p. 30, fig. 1.3).

APPENDIX

1. Introduction and statement of the problem

2.

A characteristic feature of modern measuring instruments is the widespread use of automated measurement systems (AIS).

A distinctive feature of AIS from hotel measuring instruments with limited functionality is that it includes a computer that allows centralized automated (automatic) control of the object of study, the process of measuring and processing measurement information [1].

In many cases of practice, the studied object is located at a considerable distance from the consumer of the measurement information. At the same time, along with the task of obtaining information directly from the object, the problem arises of transmitting this information via a communication channel from the object to the consumer.

Regardless of the transmission method, the signals should be presented in the form convenient for processing in a computer, provide unambiguous presentation of messages and be resistant to distortions arising for one reason or another in information storage and transmission devices [1].

The need to control arithmetic and logical operations performed in the arithmetic-logic devices (ALU) of the processor is explained by the fact that this device performs the most complex information conversion, which is the final stage of the operation of the computer as a whole. Therefore, the elements of an arithmetic device (AU) operate in more intense conditions than the elements of other devices, which is the cause of malfunctions.

The control task is to identify emerging failures in the AU and eliminate the consequences of these failures.

The effectiveness of automated systems of measuring technology is largely determined by the reliability of the information that is processed in these systems [4].

In turn, the reliability of the functioning of digital devices substantially depends on the selected method for detecting errors (the detecting ability of the selected method for monitoring information and hardware costs necessary for implementing this method).

Currently, control of arithmetic addition operations modulo, which is based on well-known identities [2], is widely used.

From the theory of numbers it is known that any number can be written as an identity:

(read: A is comparable or identical with the remainder g _{a of the} module q), which establishes the following relation between the numbers A, g _a and q:

where A, q, t and r _a are integers;

A - any controlled n-bit number;

q - module or divider;

t is the quotient;

r _a is the remainder of dividing the number A by the module q (control code of the number A).

Each controlled n-bit number A is given m additional digits in which the control code is written, i.e. the value of the remainder g _a from dividing A by mod q, by which control is carried out.

In modulo control, the condition m <n; otherwise, due to the large amount of control equipment, the reliability of the controlled system is reduced.

In numerical control modulo, the control code of the number is the remainder of dividing the number A itself by mod q. In this type of control, the identity is true:

meaning that the sum of the numbers is comparable to the sum of the remainders of the same numbers in the same module.

If q = p, then A = a _i modp and control does not make sense, since we control only the least significant bit a _{i of} number A, and the higher bits will not take part in the formation of the remainder and errors in these bits will not be detected, i.e. e. control will be ineffective.

The method of controlling information by mod3 has a much greater detecting ability, however, the implementation of this method requires large hardware costs for constructing convolution schemes and time costs associated with the delay in the passage of the signal.

The control code in digital control is the sum of the digits of a given number - modulo some.

Currently, for this purpose, the parity check method is most widely used, which requires minimal hardware costs for detecting binary set errors.

For q = p (control by mod 2), for digital control, identity (1) is satisfied with the additional condition that, when controlling arithmetic operations, it is necessary to take into account all transfers arising from the addition of two numbers.

The disadvantage of this method is its low detecting ability, since only single (odd) errors are detected.

At the same time, under extreme operating conditions of AIS, (exposure to electromagnetic or radiation radiation, etc.), the probability of occurrence of double and errors of other multiplicity increases ..

In this regard, there is a need to develop a method for controlling the execution of arithmetic operations that detects 100% of single errors and the maximum number of double errors, with minimal hardware and time costs for decoding.

For this purpose, in this paper, it is proposed to use the error detection method in information storage and transmission devices proposed in [3.5].

In this case, when encoding a binary set with an arbitrary number of information bits (let the number of information bits be a multiple of three), the binary set is divided into information blocks, three bits in each block:

As a result of encoding the binary set in question by the proposed method, we obtain the code set:

go:

Error detection is performed by bitwise adding mod2 values of the control bits r _1C and r _2C , read from the information storage device, respectively, with the values of the control bits r _1P and r _2P , formed relative to the received information bits:

λ ₁ = r _1C ⊕r _1P ;

A zero result of the sum indicates the absence of an error, and its presence otherwise.

This method allows to detect single errors of 100%, single errors and up to 80% of double errors.

2. 0 detection and correction of errors when performing arithmetic operations

Parallel-action adders, in which the transmission of numbers and the formation of the sum occurs simultaneously for all digits, have a predominant distribution in modern computers.

Consider the basic provisions of the method of controlling the operation of addition by example.

Suppose you want to add two six-digit numbers: A = 001100 and B = 001111. When encoding these numbers using the proposed method, we obtain code sets, respectively:

which will be recorded in the information storage device.

Arithmetic summation of information bits of data of code sets, taking into account transfers, will give the result:

For the sum obtained, the values of the control bits should have the corresponding values: 00.

However, the addition of control bits of the terms in mod 2 will give the result:

which differs from the correct value of 00.

In this regard, for the formation of the correct values of the control bits, it becomes necessary to determine the correction to the value of the control bits S _{k mod2} .

The rules for the formation of the amendment can be obtained on the basis of encoding information that takes into account all transfers that occur when two numbers are added.

For the example under consideration, when adding information bits, the unit signal values are transferred to the fourth and fifth bits (see 9) i.e., the information taking into account the transfers has the form: S _П = 011000.

Property 1. The correction P _to the value of the control bits S _{k mod2} is _generated by encoding the information taking into account the transfers S _{P by the} selected coding method.

For this example, the encoding of the value of S _P = 011000. the proposed method will give the correction value P _to = 10.

The bitwise addition in mod2 of the value of S _{k mod2} = 10 and the correction value of P _k = 10 will give the correct value of the control bits for the arithmetic sum S = 011011.

As a result, we have the correct code set for the sum:

S _k = 011011 00.

3. ALU control method when performing logical operations

Consider ALU control based on the proposed encoding method when performing the following most common logical operations:

a) addition by mod 2

a) shear operations.

b) logical addition,

c) logical multiplication,

e) invert operations,

3.1 Control addition operation by mod 2

We will consider the control of the addition operation by mod2 using an example. Suppose you want to add two six-digit numbers: A = 001100 and B = 001111. When encoding these numbers using the proposed method, we obtain code sets, respectively: A _K = 00110011 and B _K = 00111101,

which will be recorded in the information storage device.

Adding code sets in mod 2 will give the result:

Property 1. The result of addition by mod 2 of the control bits of the terms corresponds to the result of addition by mod 2 of the information bits of the terms being considered.

This property allows you to control the addition operation by mod2 and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

3.2 Shear control

Consider the main provisions of the method of controlling the shift operation on the example of a code set containing three information bits: A _K = 00101

Let it be required to carry out the operation of shifting information bits to the right by one bit, as a result we obtain a code set: A _KP = 00001, whose value of the control bits does not correspond to the result obtained.

In this regard, it becomes necessary to formulate an amendment, which allows one to obtain a set of control bits corresponding to the value of information bits obtained by shifting to the right.

To obtain the correct value of the control bits, we will formulate an amendment to the existing value of the control bits.

The correction value when shifting to the right, is formed on the basis of the initial value of the information bits as follows: x ₁ = 0⊕у ₃ ; (0 if one unit from another register is not transferred to the high order; otherwise x ₁ = y ₁ ⁱ ⊕у ₃ , where y ₁ ^{i is the} value of the transfer signal from another register, for example, to the high order of the register from the adder multiplication) x ₂ = y ₃ ⊕y ₂ ; x ₃ = у ₂ ⊕у ₁ ;.

For the considered example, when shifting to the right (in the absence of transfer from another register) And _K = 00101 we get

A _KP = 00001

The binary set for the correction P is equal to:

X _P = (x ₁ = 0, x ₂ = 0, x ₃ = 1,).

When coding this set by the proposed method, we obtain the correction value P _P = 01.

Adding mod2 to the original value of the control bits with the correction value will give the correct value of the control bits when shifting the information bits to the right:

When the information bits are shifted to the left, the correction values are formed on the basis of the initial value of the information bits in the following way, the bits of the correction matrix are formed as follows: x ₁ = y ₃ ⊕y ₂ ; x ₂ = y ₂ ⊕y ₁ ; x ₃ = y ₃ ⁱ ⊕y ₁

(x ₃ = y ₃ ⁱ ⊕y ₁ where y ₃ ^{i is the} value of the signal of transfer of the highest order of one register to the least significant of the other).

Let it be required to carry out the shift operation to the left (in the absence of transfer from another register) by one bit for the binary set A _K = 00101, as a result we get the code set: A _KL = 01001 in which the value of the control bits does not correspond to the result (the value of the control bits is 11 )

The information for the correction has the form: X _L == (x ₁ = 0, x ₂ = 1, x ₃ = 1,).

When coding this set by the proposed method, we obtain the correction value P _L = 10.

Adding mod2 to the original value of the control bits with the correction value will give the correct value of the control bits when shifting the information bits to the left:

Property 2. Adding mod2 to the original value of the control bits with the correction value when shifting to the right (left) will give the correct value of the control bits when shifting the information bits.

This property allows you to control the shift operation and at the same time detect and correct errors that occur according to the rules of the proposed encoding method.

3.3. Monitoring the logical operation OR

Consider the main provisions of the method of controlling the operation OR by example.

Suppose you want to perform a logical OR operation with respect to two six-digit numbers: A = 001100 and B = 001111. When encoding these numbers using the proposed method, we obtain code sets, respectively: A _K = 00110011 and B _K = 00111101, which will be recorded in the information storage device.

Logical addition of information bits of code sets and addition of mod 2 control bits to give the result:

In this case, the value of the control bits does not correspond to the result obtained (the correct value of the control bits is 01).

In this regard, the need arises for the formation of an amendment that allows you to get a set of control bits corresponding to the value of the information bits obtained during the logical addition operation.

To form the correction, we construct a binary set using the logical AND operation with respect to the information bits of the numbers in question, as a result we obtain the code set: 001100.

The encoding of the received binary set by the selected encoding method will give the correction values to the control bits during the OR operation:

P _OR = 11

The mod2 addition of the obtained value of the control bits with the correction value will give the correct value of the control bits for the operation in question.

Property 3. The operation of adding, by mod2, the obtained values of the control bits and the correction value generated on the basis of the coding of the information obtained during the logical operation AND regarding the information bits, will give the correct value of the control bits.

3.4 Monitoring the execution of logical operations AND

Consider the main provisions of the method of controlling the operation And on an example.

Suppose you want to perform a logical operation AND with respect to two six-digit numbers: A = 001100 and B = 001111. When encoding these numbers using the proposed method, we obtain code sets, respectively: A _K = 00110011 and B _K = 00111101, which will be recorded in the information storage device.

Logical multiplication of information bits of code sets and addition of mod 2 control bits to give the result:

In this case, the value of the control bits does not correspond to the result obtained (the correct value of the control bits is 11).

In this regard, the need arises for the formation of an amendment that allows you to get a set of control bits corresponding to the value of the information bits obtained during the logical addition operation.

To form the correction, we construct a binary set using the logical OR operation with respect to the information bits of the numbers in question, as a result we obtain the code set: 001111.

The encoding of the obtained binary set by the selected encoding method will give the correction values to the control bits during the operation AND:

P _I = 01

The mod2 addition of the obtained value of the control bits with the correction value will give the correct value of the control bits for the operation in question.

Property 5. The operation of adding, according to mod2, the obtained values of the control bits and the correction value generated on the basis of the coding of the information obtained during the logical operation OR regarding information bits, will give the correct value of the control bits.

3.5 Logical operation control NOT

Consider the main provisions of the method of controlling the inversion operation by example.

Suppose you want to perform a logical operation NOT for code dialing: А _К = 00110011

When performing the operation NOT for information bits, we obtain the code set A _K = 11001111, in which the control values correspond to the correct value of the control bits.

Property 6. The values of the control bits when performing a logical operation do NOT have the correct value.

Thus, the proposed error detection method allows to detect all single errors and the maximum number of double errors of ALU with a slight increase in hardware costs in relation to the parity control method, without reducing the speed of information processing.

INFORMATION SOURCES

1. Kulikovsky K.L., Cooper V.Ya. Methods and means of measurement. M .: Enogoatomizdat 1986, 447 p.

2. Putintsev N.D. Hardware control of control digital computers. M .: Soviet Radio, 1966, 424 p.

3. Pavlov A.A., Pavlov P.A. Tsarkov A.N. Khoruzhenko O.V., Functional-code error control in automated systems of measuring equipment. // Measuring technique. 2009, No. 9 p.3-5.

4. Scherbakov N.S. The reliability of digital devices. M: Mechanical Engineering, 1989, 224 s.

5. A.A. Pavlov, P. A. Pavlov A.N. Tsarkov and O. V. Horuzheko Functional cod error monitoring in computerized data-acquisiti systems. / Measurement Techniques, Springer New York, V0f. 52, No. 9, 2009, p. 891-893.

Claims (1)

A computer processor containing a control node, an operating node, the first inputs of the control node are the inputs of the processor, the second group of inputs of the control node is connected to the first outputs of the operational node, the outputs of the control node are connected to the first inputs of the operational node, the second inputs of which are data inputs, and the second outputs are data outputs, characterized in that it further comprises an operation code decoder, a clock, a control unit, a first switch, a second switch, a third mutator, command counter, shift counter, address register, number register, adder register, additional register, additional code register, adder, control unit, control memory, logical operations and control unit, including mod2 logical addition unit, invert unit, logical unit addition, a logical multiplication block, a functional diagram of the formation of the amendment when performing arithmetic operations, a functional diagram of the formation of the amendment when performing the operation OR, a functional diagram of the formation of mandrels during the operation AND, the functional diagram of the formation of the corrections during the shift operation, the delay element, the first block of discontinuity elements, the second block of discontinuity elements, the third block of discontinuity elements, the first block of OR elements, the second block of OR elements, coding block, the first block of And , the second block of elements And, the element And, the outputs of the exchange device are connected to the first input of the control unit and to the first input of the second switch, the second inputs of which are connected to the outputs of the memory device, the first outputs of the second switch go to the input of the exchange device, the second outputs go to the input of the storage device, and the third outputs are connected respectively to the first inputs of the command counter, shift counter, number register, adder register, additional register, additional code register, to the inputs decoder operation code, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register, the third input of the control unit it is connected to the outputs of the operation code decoder, and the fourth input is connected to the outputs of the clock generator, and the fifth input is connected to the first output of the control memory, the first output of the control unit is connected to the input of the control memory, the first outputs of which are connected to the first inputs of the control unit, the second output of the block control is connected to the second input of the first switch, the third and fourth inputs of which are connected respectively to the outputs of the address register and command counter, and the address of the memory cell is removed from the second output device, the third output of the control unit is connected respectively to the second inputs of the control unit, to the second inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group the inputs of the second switch, to the first group of inputs of the block of logical operations and control and is the output of the clock pulses, the second, third, fourth, fifth outputs of the control memory are connected to the third and fourth the fifth, fifth and sixth inputs of the control unit, while the second output is connected to the fourth input of the second switch, and the third, fourth and fifth outputs of the control memory unit are connected respectively to the third, fourth fifth and sixth inputs of the command counter, shift counter, address register, register numbers, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the first group of inputs of the block of logical operations and control and are the outputs of the control signals, read signals, write signals, signals to set the devices to zero, the sixth output of the control memory unit is connected to the fifth input of the control unit, the outputs of the number register, adder register, additional register, auxiliary register are connected to the second inputs of the third switch and to the fifth inputs of the second switch, the output of the shift counter is connected to the sixth inputs of the second switch, the first outputs of the third switch are connected respectively to the inputs of the sums ora and to the second inputs of the block of logical operations and control, the outputs of the adder are connected to the third inputs of the block of logical operations and control, the second, third, fourth, fifth, sixth, seventh and eighth outputs of the third switch are connected to the fourth, fifth, sixth, seventh, eighth , the ninth and tenth inputs of the logical operation and control unit, the outputs of which are connected to the seventh, eighth and ninth inputs of the second switch.