RU2533688C1 - Computer system - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: computer system comprises five computers, three input/output channels, three external users and a control device. Corresponding computer inputs/outputs are connected by buses to corresponding inputs/outputs of the control device; a main shared memory unit and a backup shared memory unit, corresponding inputs/outputs of which are connected by buses to corresponding inputs/outputs of the control device; the first three computers are used as universal computers, the fourth computer is used as a control computer and the fifth computer is a backup computer; the inputs/outputs of each corresponding user are connected by buses to inputs/outputs of the corresponding input/output channel, inputs/outputs of which are connected by buses to corresponding inputs/outputs of the control device.

EFFECT: enabling control of multiple computers of a system in case of different emergency situations by redistributing system resources.

8 cl, 2 tbl, 9 dwg

Description

The invention, the model relates to computer technology and can be used in the construction of multi-machine, multiprocessor computing systems (AC) of high performance and reliability.

Known redundant dual-processor computing system [RF No. 2264648 C1, G06F 11/20, 05.27.2005], containing two identical channels, in each of which the first output of the processor is connected to the first input of the switch, the system generator, the output of which is connected to the first input the processor of the first channel, the initial installation circuit, the output of which is connected to the second input of the processor of the first channel, a pulse generator, an OR element, a temporary health analyzer, a failure counter, a trigger, an OR-NOT element whose output is connected to the second the switch, the second processor output through the OR element is connected to the first input of the trigger and to the second input of the temporary health analyzer, the trigger output is connected to the first input of the OR-NOT element, the second input of the processor is connected to the second input of the OR element and the second input of the failure counter, pulse output the generator through a temporary health analyzer is connected to the first input of the failure counter and to the second input of the trigger, the second output of the failure counter is connected to the second input of the OR-NOT element, and the system gene an herator whose output is connected to the first input of the processor of the second channel, an initial installation circuit, the output of which is connected to the second input of the processor of the second channel, and a comparison circuit, the first input of which is connected to the first output of the failure counter of the first channel, the second input of the comparison circuit is connected to the first output failure counter of the second channel, the first output of the comparison circuit is connected to the third input of the OR-element of the first channel, the second output of the comparison circuit is connected to the third input of the OR-NOT of the second channel, comm outputs tators are connected and are the output of the system.

A disadvantage of the known system is that it can be used only when building reliable computing systems due to channel redundancy.

Closest to the claimed one is a computing system [AS No. 873804 A1, G06F 15/16, 06/15/19941, containing N digital computers (digital computers), N input / output channels, N power supply units, N groups of interface devices, N * M external subscribers (M is the number of external subscribers in the group) and the control unit, with the first input / output of the digital computer connected to the corresponding input-output of the control unit, the second input / output of the digital computer connected to the first input-output of the corresponding input-output channel, the first output of the digital computer with the input of the corresponding power supply unit the second input-output of the input-output channel is connected to the first input-output of the pairing devices of the corresponding group, the second input-output of the pairing device is connected to the inputs-outputs of external subscribers of the corresponding group, characterized in that it contains N adapters to improve performance, N priority blocks and N switches, with one input-output of the adapter connected to the second input-output of the corresponding input-output channel, other input-outputs of one adapter connected to the corresponding inputs and outputs of the other of their adapters, the trigger input of the priority block is connected to the output of the corresponding I / O channel, the request inputs of the priority block are connected to the outputs of the pairing devices of the corresponding group, the outputs of the priority block are connected to the first inputs of the pairing devices of the corresponding group, the second inputs of which are connected to the outputs of the corresponding switch, the output the power supply unit and the second output of the digital computer are connected to the inputs of the corresponding switch, and each input-output of the group of inputs and outputs of the control unit is connected n to a second input-output of the respective coupling device.

The disadvantage of this system is the lack of the ability to control the operation of several computers of the system in the event of various emergency situations due to the redistribution of system resources.

The technical result is the ability to control the operation of several computers of the system in the event of various emergency situations due to the redistribution of system resources.

The technical result is achieved by  what's in a computing system,  containing five electronic computers (computers),  Three input / output channels  three external subscribers and a control device,  moreover, the corresponding inputs and outputs of the computer are connected by buses with the corresponding inputs and outputs of the control device,  additionally introduced a block of main shared memory (OP) and a block of standby OP,  the corresponding inputs and outputs of which are connected by buses with the corresponding inputs and outputs of the control device,  the first three computers are used as universal,  the fourth computer is used as a control,  and the fifth computer is a backup,  the inputs and outputs of each corresponding subscriber are connected by buses the inputs and outputs of the corresponding input-output channel,  the inputs and outputs of which are connected by buses with the corresponding inputs and outputs of the control device,  moreover, the control device contains two blocks of elements OR,  block of elements OR,  consisting of N elements OR,  where N is equal to the number of bits of the transmitted information,  the system control unit when writing and reading the control point of the universal computer,  system control unit in the event of a malfunction of one of the universal computers,  communication unit of all computers of the system with external subscribers,  the system control unit in the event of a malfunction of the universal computer memory,  the system control unit in the event of a malfunction in the OP and four OR elements,  from the first to thirty third inputs of the device are connected respectively from the first to thirty third inputs of the first block of OR elements,  from the thirty-fourth to sixty-eighth inputs of the device are connected respectively from the first to thirty-fifth inputs of the second block of OR elements,  the first to fourth outputs of the first block of OR elements are connected, respectively, from the first to fourth inputs of the system control unit when writing and reading the control point of the universal computers,  the fifth input of which is connected to the output of the block of elements OR,  the second input of the system control unit when writing and reading the control point of the mainframe computer is connected to the combined first inputs,  system control unit in the event of a malfunction of one of the universal computers,  the control unit of the system in the event of a malfunction of the memory of the universal computers and the fourth input of the communication unit of all the computers of the system with external subscribers,  the fifth to twelfth inputs of the first block of OR elements are connected respectively to the sixth to thirteenth inputs of the system control unit when writing and reading the control point of the mainframe computers,  from the thirteenth to the fifteenth inputs of the first block of OR elements are connected respectively from the third to fifth system control unit in the event of a malfunction of one of the mainframes,  from the first to fifth inputs of the second block of OR elements are connected, respectively, from the tenth to fourteenth of the system control unit in the event of a malfunction of one of the mainframes,  the second input of which is connected to the third input of the communication unit of all computers of the system with external subscribers and the seventh output of the second block of OR elements,  the sixth output of which is connected to the second input of the communication unit of all computers of the system with external subscribers,  the first input of which is connected to the third input of the system control unit in the event of a malfunction of one of the universal computers,  the fourth input of which is connected to the sixth input of the communication unit of all computers of the system with external subscribers,  the fifth input of which is connected to the eighth output of the second block of OR elements,  from the ninth to fourteenth outputs of which are connected respectively with the seventh to twelfth inputs of the communication unit of all computers of the system with external subscribers,  from the thirteenth to the fifteenth inputs of which are connected each, respectively, to the OR elements combined from the first to the third inputs of the block of OR elements,  from the fifth to the seventh inputs of the system control unit in the event of a malfunction of the universal computer memory,  from the fourth to sixth inputs of the system control unit when a malfunction occurs in the OP and from the twenty-first to twenty-third outputs of the second block of OR elements,  the fifteenth and sixteenth outputs of which are each connected respectively to the third and fourth inputs of the system control unit in the event of a malfunction of the universal computer memory,  the eighth input of which is connected to the sixth input of the system control unit when writing and reading the control point of the universal computers,  the eighth input of which is connected to the fifteenth input of the system control unit in the event of a malfunction of one of the universal computers,  the eighth input of which is connected to the seventh input of the system control unit when writing and reading the control point of the universal computers,  the eleventh input of which is connected to the seventh input of the system control unit in the event of a malfunction of one of the universal computers,  the ninth input of which is connected to the thirteenth input of the system control unit when writing and reading the control point of the universal computers,  the twelfth input of which is connected to the sixth input of the system control unit in the event of a malfunction of one of the universal computers,  the fifth input of which is connected to the second input of the system control unit in the event of a malfunction of the mainframe memory,  the ninth input of which is connected to the seventeenth output of the second block of OR elements,  from the eighteenth to the twentieth outputs of which are connected respectively from the first to third inputs of the system control unit in the event of a malfunction in the OP,  the seventh and eighth inputs of which are connected respectively to the nineteen fourth and twenty-fifth outputs of the second block of OR elements,  from the first to tenth outputs of the system control unit in the event of a malfunction of the memory of the universal computers are connected respectively to the twenty-ninth to thirty-eighth outputs of the device,  from the thirty-ninth to forty-fifth outputs of which are connected respectively to the first to seventh outputs of the system control unit in the event of a malfunction in the OP,  from the third to eighth outputs of the system control unit when writing and reading the control point of the universal computers are connected respectively to the second to seventh outputs of the device,  the first output of which is connected to the output of the first OR element,  the second input of which is connected by the eleventh output of the system control unit in the event of a malfunction of one of the universal computers,  the first output of which is connected to the second input of the second OR element,  the first input of which is connected to the second output of the system control unit when writing and reading the control point of the universal computers,  the first output of which is connected to the first input of the first OR element,  the output of the second OR element is connected to the eighth output of the device,  the ninth output of which is connected to the second output of the system control unit in the event of a malfunction of one of the universal computers,  from the sixth to tenth outputs of which are connected respectively with the eleventh to fifteenth outputs of the device,  the tenth output of which is connected to the fourth output of the system control unit in the event of a malfunction of one of the universal computers,  the third output of which is connected to the first input of the third OR element,  the second input of which is connected to the first output of the communication unit of all computers of the system with external subscribers,  and the output is connected to the seventeenth output of the device,  the sixteenth output of which is connected to the twelfth output of the system control unit in the event of a malfunction of one of the universal computers,  the fifth output of which is connected to the first input of the fourth OR element,  the second input of which is connected to the eighth output of the communication unit of all computers of the system with external subscribers,  and the output is connected to the twenty-eighth output of the device,  from the eighteenth to twenty-third outputs of which are connected respectively to the second to seventh outputs of the communication unit of all computers of the system with external subscribers,  from the ninth to twelfth outputs of which are connected respectively with the twenty-fourth to twenty-seventh outputs of the device,  wherein the first block of OR elements contains nine OR elements,  from the first to third inputs of the block are connected respectively with the first to third inputs of the first OR element,  the output of which is connected to the first output of the block,  the second output of which is connected to the fourth input of the block,  the fifth to seventh inputs of which are connected from the first to third inputs of the second OR element,  the output of which is connected to the third output of the block,  from the eighth to tenth inputs of which are connected from the first to third inputs of the third OR element,  the output of which is connected to the fourth output of the block,  the eleventh to thirteenth inputs of which are connected from the first to third inputs of the fourth OR element,  the output of which is connected to the fifth output of the block,  the fourteenth and fifteenth inputs of which are connected respectively with its sixth and seventh outputs,  sixteenth to eighteenth whose inputs are connected from the first to third inputs of the fifth OR element,  the output of which is connected to the eighth output of the block,  from the nineteenth to twenty-first inputs of which are connected from the first to third inputs of the sixth element OR,  the output of which is connected to the ninth output of the block,  twenty second,  the twenty third and twenty fourth entrances of which are connected respectively with the tenth,  the eleventh and twelfth outputs of the block,  twenty-fifth through twenty-seventh inputs of which are connected from the first to third inputs of the seventh element OR,  the output of which is connected to the thirteenth output of the block,  from the twenty-eighth to the thirtieth inputs of which are connected from the first to third inputs of the eighth element OR,  the output of which is connected to the fourteenth output of the block,  from the thirty-first to thirty-third inputs of which are connected from the first to third inputs of the ninth element OR,  the output of which is connected to the fifteenth output of the block,  moreover, the second block of OR elements contains five OR elements from the first to fifth inputs of the block are connected respectively each from the first to fifth of its outputs,  from the sixth to the eighth inputs of which are connected from the first to third inputs of the first OR element,  the output of which is connected to the sixth output of the block,  the ninth input of which is connected to the seventh output of the block,  the tenth to twelfth inputs of which are connected from the first to third inputs of the second OR element,  the output of which is connected to the eighth output of the block,  from the thirteenth to the fifteenth inputs of which are connected from the first to the third inputs of the third OR element,  the output of which is connected to the ninth output of the block,  from the sixteenth to the twentieth inputs of the block are connected respectively each from the tenth to fourteenth of its outputs,  twenty-first to twenty-third inputs of which are connected from the first to third inputs of the fourth element OR,  the output of which is connected to the fifteenth output of the block,  twenty-fourth through twenty-sixth inputs of which are connected from the first to third inputs of the fifth element OR,  the output of which is connected to the sixteenth output of the block,  from the twenty-seventh to thirty-fifth inputs of the block are connected respectively each from the seventeenth to twenty-fifth of its outputs,  moreover, the control unit of the system when writing and reading the control point of the universal computer contains a decoder,  address former  trigger,  four blocks of AND elements,  consisting of N elements and each,  two buffer storage blocks and three blocks of AND elements,  consisting of N elements and each,  the outputs of which are connected respectively to the sixth,  seventh and eighth block outputs,  whose first input is connected to its first output,  the second input of the block is connected to the input of the decoder,  the first,  the second and third outputs of which are connected to the first inputs, respectively, of the first second and third blocks of elements And and, accordingly, with the first,  second and third inputs of the address generator,  the output of which is connected to the second output of the block,  the third output of which is connected to the zero input of the trigger and the fourth input of the block,  the third input of which is connected to a single input of the trigger,  whose single output is connected to the first input of the first block of AND elements,  the second input of which is connected to the fifth input of the block,  the sixth input of which is connected to the first input of the fourth block of AND elements and to the third input of the first block of AND elements,  the output of which is connected to the input of the first buffer storage unit,  the output of which is connected to the first input of the second block of AND elements,  the output of which is connected to the fourth output of the block,  the seventh input of which is connected to the first input of the third block of AND elements and the second input of the second block of AND elements,  the third input of which is connected to the eighth input of the block,  the ninth entrance of which is connected to its fifth exit,  the tenth input of the block is connected to the second input of the fourth block of AND elements,  the third input of which is connected to the output of the second buffer storage unit,  the input of which is connected to the output of the third block of AND elements,  the second and third inputs of which are connected respectively with the eleventh and twelfth inputs of the block,  the thirteenth input of which is connected to the fourth input of the fourth block of AND elements,  the output of which is connected to the combined second inputs of the first second and third blocks of AND elements,  moreover, the control unit of the system in the event of a malfunction of one of the universal computers contains a decoder,  address former  trigger,  three blocks of AND elements,  consisting of N elements  four blocks of AND elements,  consisting of N elements and each,  block of elements OR,  consisting of N elements,  a buffer storage unit and an AND element,  the output of which is connected to the fourth output of the block,  the first input of which is connected to the input of the decoder,  the first,  the second and third outputs of which are connected to the first inputs, respectively, of the first second and third blocks of elements And and, accordingly, with the first,  second and third inputs of the address generator,  the output of which is connected to the first output of the block,  the second input of which is connected to the combined first inputs of the first and second blocks of AND elements,  the first input of the And element and the second output of the block,  the third input of which is connected to its third output,  the second input of the And element and the single input of the trigger,  whose single output is connected to the combined second inputs of the first,  second  third and fourth blocks of elements And,  and the zero input of the trigger is connected to the fourth input of the block and its fifth and sixth outputs,  the fifth input of the block is connected to the combined second inputs of the first,  the second and third blocks of elements And,  the outputs of which are connected respectively to the seventh,  eighth and ninth outputs of the block,  the sixth and seventh inputs of which are connected respectively with the third and fourth inputs of the third block of AND elements,  the fifth input of which is connected to the fourth input of the fourth block of AND elements and the eighth input of the block,  the ninth and tenth inputs of which are connected respectively with the fourth and fifth inputs of the second block of AND elements,  the sixth input of which is connected to the fourth input of the third block of AND elements and the eleventh input of the block,  whose twelfth entrance is connected to its eleventh exit,  the thirteenth and fourteenth inputs of the block are connected respectively to the first and third inputs of the third block of AND elements,  the output of which is connected to the second input of the block of elements OR,  the first input of which is connected to the output of the first block of AND elements,  and the output is connected to the input of the buffer storage unit,  the output of which is connected to the combined third input of the second block of AND elements and the first input of the fourth block of AND elements,  the third input of which is connected to the fifteenth input of the block,  and the output is connected to the twelfth output of the block,  the tenth output of which is connected to the output of the second block of AND elements,  moreover, the communication unit of all computers of the system with external subscribers contains two decoders,  trigger,  five elements OR,  the item is NOT  sixteen blocks of elements And,  consisting of N elements and each,  and five blocks of OR elements,  consisting of N elements and each,  the first and second inputs of the block are connected respectively with its first and second outputs and the first and second inputs of the first OR element,  the output of which is connected to a single trigger input,  whose single output is connected to the combined second inputs of the second,  third  the tenth and eleventh blocks of elements And,  and the zero output of the trigger is connected to the combined first inputs of the seventh AND,  of the eighth And  on the ninth And  fourteenth And,  the fifteenth And and the sixteenth And the blocks of elements And,  the third input of the block is connected to the combined first input of the second AND,  the third input of the tenth AND blocks of AND elements and the input of the element NOT,  the output of which is connected to the combined first input of the third AND,  the third input of the eleventh AND blocks of elements AND,  the fourth input of the block is connected to the input of the first decoder,  the first,  the second and third outputs of which are connected to the first inputs of the second, respectively,  third and fourth elements OR,  the second inputs of which are connected with respectively the first,  second and third outputs of the second decoder,  the input of which is connected to the fifth input of the block,  the sixth and seventh inputs of which are connected respectively with its eighth and ninth outputs and, respectively, with the first and second inputs of the fifth OR element,  the output of which is connected to the zero input of the trigger,  eighth,  the ninth and tenth inputs of the block are connected to the second inputs, respectively, of the first,  the second and third blocks of elements And,  the outputs of which are connected to the corresponding inputs of the first block of OR elements,  the output of which is connected to the combined third inputs of the second and third blocks of AND elements,  the outputs of which are connected respectively with the third and fourth outputs of the block,  the eleventh and twelfth inputs of which are connected to the first inputs of the tenth and eleventh blocks of AND elements, respectively  the outputs of which are connected respectively to the first and second inputs of the second block of OR elements,  the output of which is connected to the combined second inputs of the fourth,  fifth and sixth blocks of elements And,  the outputs of which are connected to the first inputs, respectively, of the third,  fourth and fifth blocks of elements OR,  the second inputs of which are connected to the outputs of the seventh,  the eighth and ninth blocks of elements And,  the second inputs of which are connected respectively with the thirteenth,  the fourteenth and fifteenth inputs of the block,  the tenth eleventh and twelfth outputs of which are connected to the outputs, respectively, of the third,  fourth and fifth blocks of elements OR,  fifth,  the sixth and seventh outputs of the block are connected to the outputs of the fourteenth AND, respectively  the fifteenth And and the sixteenth And the blocks of elements And,  the second inputs of which are connected to the second inputs, respectively, of the first,  the second and third blocks of elements And,  the first inputs of which are connected to the outputs of the second,  the third and fourth element OR,  moreover, the control unit of the system when a malfunction of the memory of the universal computer contains a decoder,  address former  trigger,  the three elements of AND,  eight blocks of AND elements,  consisting of N elements and each,  and block of elements OR,  the output of which is connected to the second input of the fourth block of AND elements,  the output of which is connected to the seventh output of the block,  the first input of which is connected to the input of the decoder,  the first output of which is connected to the combined first inputs of the first AND element,  the first and sixth blocks of AND elements and the address generator,  the second input of which is connected to the combined first inputs of the second element And,  second and seventh blocks of elements And and the second output of the decoder,  the third output of which is connected to the combined first inputs of the third AND element,  the third and eighth blocks of elements And and the third input of the address generator,  the output of which is connected to the first output of the block,  second,  the third and fourth outputs of which are connected to the outputs, respectively, of the first,  second and third elements And,  the second inputs of which are combined and connected to the second input of the block,  the third input of which is connected to its fifth output and a single trigger input,  a single output of which is connected to the combined first inputs of the fourth and fifth elements of And,  and the zero input of the trigger is connected to the combined fourth input and sixth output of the block,  fifth,  the sixth and seventh inputs of which are connected to the second inputs, respectively, of the first,  the second and third blocks of elements And,  the outputs of which are connected respectively to the first,  second  and the third inputs of the OR element,  the eighth input of the block is connected to the combined third inputs of the fourth and fifth elements And,  the ninth input of the block is connected to the second input of the fifth element And,  the output of which is connected to the combined second inputs of the sixth,  the seventh and eighth blocks of elements And,  the outputs of which are connected respectively to the eighth,  the ninth and tenth outputs of the block,  moreover, the control unit of the system in the event of a malfunction in the OP contains a decoder,  trigger,  ten blocks of elements And,  consisting of N elements and each,  and two blocks of OR elements,  consisting of N elements OR,  the first input of the block is connected to its first output and a single trigger input,  the zero input of which is connected to the second input of the block and its second output,  the third input of the block is connected to the input of the decoder,  the first output of which is connected to the combined first inputs of the first and sixth blocks of AND elements,  the second output of the decoder is connected to the combined first inputs of the second and seventh blocks of elements And,  the third output of the decoder is connected to the combined first inputs of the third and eighth blocks of AND elements,  fourth,  the fifth and sixth inputs of the block are connected to the second inputs, respectively, of the first,  the second and third blocks of elements And,  the outputs of which are connected respectively to the first,  the second and third inputs of the first block of OR elements,  the output of which is connected to the combined second inputs of the fourth and fifth blocks of AND elements,  the outputs of which are connected respectively with the third and fourth outputs of the block,  fifth,  the sixth and seventh outputs of which are connected to the outputs of the sixth, respectively  the seventh and eighth blocks of elements And,  the second inputs of which are combined and connected to the output of the second block of OR elements,  the first and second inputs of which are connected to the outputs of the ninth and tenth blocks of AND elements, respectively,  the second inputs of which are connected respectively to the seventh and eighth inputs of the block,  the trigger single output is connected to the combined first inputs of the fourth and ninth blocks of AND elements,  and the zero output of the trigger is connected to the combined first inputs of the fifth and tenth blocks of elements I.

The introduction of these additional elements and the sequence of their connection allows you to provide the ability to control the operation of several computers of the system in the event of various emergency situations due to the redistribution of system resources.

Figure 1 - presents a functional diagram of a computing system.

Figure 2 - presents a functional diagram of a control device.

Figure 3 - presents a functional diagram of the first block of OR elements.

Figure 4 - presents a functional diagram of the second block of OR elements.

Figure 5 - presents a functional diagram of the control unit of the system when writing and reading the control point of a universal computer.

Figure 6 - presents a functional diagram of a system control unit in the event of a malfunction of a universal computer.

Figure 7 - presents a functional diagram of the communication unit of all computers of the system with external subscribers.

On Fig - presents a functional diagram of a system control unit in the event of a malfunction of storage devices (memory) of universal computers.

In Fig.9 - presents a functional diagram of the control unit of the system in the event of a malfunction in the shared memory (OP).

The system (figure 1) contains three 1 ₁ -1 ₃ universal computers, a system control device 2, a universal backup computer 3, a control computer 4, three external subscribers 5 ₁ -5 ₃ , three input-output devices 6 ₁ -6 ₃ , block 7 of the main OP and block 8 of the backup OP.

The control device 2 (figure 2) contains two blocks of OR elements 9 ₁ -9 ₂ , block 10, consisting of N OR elements, where N is equal to the number of bits of the transmitted information, the system control unit 11 for writing and reading the control point of the mainframes, block 12 system control in the event of a malfunction of one of the mainframes, the unit 13 for communication of all the system computers with external subscribers, the system control unit 14 in the event of a malfunction of the mainframe memory, the system control unit 15 in the event of a malfunction in the OP and four Re element OR 16 ₁ -16 ₄ .

The first block of elements OR 9 ₁ (figure 3) contains nine elements OR 17 ₁ -17 ₉ .

The second block of elements OR 9 ₂ (figure 4) contains five elements OR 18 ₁ -18 ₅ .

The system control unit when writing and reading the control point of the universal computer 11 (Fig. 5) contains a decoder 19, an address generator 20, a trigger 21, four blocks of elements I 22 ₁ -22 ₄ , consisting of N elements And each, two buffer storage blocks 23 ₁ -23 ₂ and three blocks of elements And 24 ₁ -24 ₃ , consisting of N elements And each.

The system control unit in the event of a malfunction of one of the mainframe computers 12 (Fig. 6) contains a decoder 25, an address former 26, a trigger 27, three blocks of elements And 28 ₁ -28 ₃ , consisting of N elements And, four blocks of elements And 29 ₁ - 29 ₄ , consisting of N elements AND each, a block of elements OR 30, consisting of N elements, a buffer storage unit 31 and an element And 32.

The communication unit of all the computer system with external subscribers 13 (Fig.7) contains two decoders 33 ₁ -35 ₅ , trigger 34, five elements OR 35 ₁ -35 ₅ , element NOT 36, sixteen blocks of elements AND 37 ₁ -37 ₁₆ , consisting of N elements AND each, and five blocks of elements OR 38 ₁ -38 ₅ , consisting of N elements AND each.

The system control unit in the event of a malfunction of the universal computer memory 14 (Fig. 8) contains a decoder 39, an address generator 40, a trigger 41, three elements And 42 ₁ -42 ₃ , eight blocks of elements And 43 ₁ -43 ₈ , consisting of N elements And each, and a block of elements OR 44.

The system control unit in the event of a malfunction in the OP 15 (Fig. 9) contains a decoder 45, a trigger 46, ten blocks of elements AND 47 ₁ -47 ₁₀ , consisting of N elements And each, and two blocks of elements OR 48 ₁ -48 ₂ , consisting of N elements OR.

The system (Fig.1 - Fig.9) contains five electronic computers (computers) 1, 3 and 4, three input-output channels 6, three external subscribers 5 and a control device 2, and the corresponding inputs and outputs of the computer are connected with buses the corresponding inputs and outputs of the control device, block 7 of the main shared memory (OP) and block 8 of the backup OP, the corresponding inputs and outputs of which are connected by buses with the corresponding inputs and outputs of the control device, the first three computers are used as universal 11-13, the fourth computer is used in as a manager 4, and the fifth computer 5 is redundant, the inputs and outputs of each corresponding subscriber are connected by buses the inputs and outputs of the corresponding input-output channel, the inputs and outputs of which are connected by buses with the corresponding inputs and outputs of control device 2, and control device 2 contains two blocks of elements OR 9 _one -9 ₂ , block 10 of OR elements, consisting of N elements OR, where N is equal to the number of bits of transmitted information, block 11 of the system control when writing and reading the control point of the mainframes, block 12 of the system control when a malfunction occurs of one of the mainframes, block 13 of communication of all computers systems with external subscribers, the system control unit 14 when a malfunction of the mainframe memory occurs, the system control unit 15 when a malfunction occurs in the OP and four OR elements 16 _one -16 _four , from the first to thirty-third inputs of the device are connected respectively from the first to thirty-third inputs of the first block of elements OR 9 _one , from the thirty-fourth to sixty-eighth inputs of the device are connected respectively from the first to thirty-fifth inputs of the second block of elements OR 9 ₂ , the first to fourth outputs of the first block of elements OR 9 _one are connected respectively from the first to the fourth inputs of the system control unit 11 when writing and reading the control point of the mainframes, the fifth input of which is connected to the output of the OR block 10, the second input of the system control unit 11 when writing and reading the control point of the universal computers is connected to the combined first inputs , system control unit 12 in the event of a malfunction of one of the mainframes, system control unit 14 in the event of a malfunction of the memory of the universal computers and the fourth input Lock 13 for communication of all computers of the system with external subscribers, from the fifth to twelfth inputs of the first block of elements OR 9 _one connected respectively from the sixth to thirteenth inputs of the system control unit 11 when writing and reading the control point of the mainframes, from the thirteenth to fifteenth inputs of the first block of OR elements 9 _one connected respectively from the third to fifth block 12 of the system control when a malfunction of one of the mainframe computers occurs, from the first to fifth inputs of the second block of elements OR 9 ₂ connected from the tenth to fourteenth block 12 of the system control when a malfunction of one of the mainframes occurs, the second input of which is connected to the third input of the communication unit 13 of all computers in the system with external subscribers and the seventh output of the second block of elements OR 9 ₂ the sixth output of which is connected to the second input of the communication unit 13 of all computers of the system with external subscribers, the first input of which is connected to the third input of the system control unit 12 in the event of a malfunction of one of the mainframes, the fourth input of which is connected to the sixth input of the communication unit 13 of all computers of the system with external subscribers, the fifth input of which is connected to the eighth output of the second block of elements OR 9 ₂ , from the ninth to fourteenth outputs of which are connected respectively with the seventh to twelfth inputs of the communication unit 13 of all computers of the system with external subscribers, from the thirteenth to fifteenth inputs of which are connected each, respectively, to OR from the fifth to seventh inputs of the fifth to seventh inputs unit 14 of the system control when a malfunction of the memory of the mainframes, from the fourth to sixth inputs of the block 15 of the system control when a malfunction occurs in the OP and from the twenty-first to twenty third outputs of the second block elements OR 9 ₂ , the fifteenth and sixteenth outputs of which are connected each to the third and fourth inputs of the system control unit 14, respectively, in the event of a malfunction of the mainframe memory, the eighth input of which is connected to the sixth input of the system control unit 11 when writing and reading the control point of the universal computers, the eighth input of which is connected to the fifteenth input of the system control unit 12 in the event of a malfunction of one of the universal computers, the eighth input of which is connected to the seventh input of the system control unit 11 when writing and reading the control point of the mainframe computer, the eleventh input of which is connected to the seventh input of the system control unit 12 when a malfunction of one of the mainframe computers occurs, the ninth input of which is connected to the thirteenth input of the system control unit 11 when writing and reading the control point of the universal computer the input of which is connected to the sixth input of the system control unit 12 in the event of a malfunction of one of the mainframes, the fifth input of which is connected to the second input of the unit 1 4 control the system in the event of a malfunction of the memory of the universal computer, the ninth input of which is connected to the seventeenth output of the second block of elements OR 9 ₂ , from the eighteenth to the twentieth outputs of which are connected respectively from the first to third inputs of the system control unit 15 when a malfunction occurs in the OP, the seventh and eighth inputs of which are connected to the nineteen fourth and twenty-fifth outputs of the second block of elements OR 9, respectively ₂ , from the first to the tenth outputs of the system control unit 14 when a malfunction of the mainframe memory is connected respectively to the twenty-ninth to thirty-eighth outputs of the device, from the thirty-ninth to forty-fifth outputs of which are connected to the first to seventh outputs of the system control unit 15 in the event of a malfunction in OP, from the third to eighth outputs of the system control unit 11 when writing and reading the control point of the mainframes are connected respectively from the second to the seventh output the device, the first output of which is connected to the output of the first element OR 16 _one , the second input of which is connected to the eleventh output of the system control unit 12 when a malfunction of one of the mainframe computers occurs, the first output of which is connected to the second input of the second OR element 16 ₂ the first input of which is connected to the second output of the system control unit 11 when writing and reading the control point of the mainframes, the first output of which is connected to the first input of the first element OR 16 _one , output of the second element OR 16 ₂ connected to the eighth output of the device, the ninth output of which is connected to the second output of the system control unit 12 in the event of a malfunction of one of the mainframes, the sixth to tenth outputs of which are connected to the eleventh to fifteenth outputs of the device, the tenth output of which is connected to the fourth output of the control unit 12 system in the event of a malfunction of one of the universal computers, the third output of which is connected to the first input of the third element OR 16 ₃ the second input of which is connected to the first output of the communication unit 13 of all computers of the system with external subscribers, and the output is connected to the seventeenth output of the device, the sixteenth output of which is connected to the twelfth output of the system control unit 12 in the event of a malfunction of one of the mainframes, the fifth output of which is connected to the first input of the fourth element OR 16 _four the second input of which is connected to the eighth output of the communication unit 13 of all computers of the system with external subscribers, and the output is connected to the twenty-eighth output of the device, from the eighteenth to twenty-third outputs of which are connected respectively to the second to seventh outputs of the communication unit 13 of all computers of the system with external subscribers , from the ninth to twelfth outputs of which are connected respectively with the twenty-fourth to twenty-seventh outputs of the device, and the first block of elements OR 91 contains nine elements OR 17 _one -17 ₉ , the first to third inputs of the block are connected respectively with the first to third inputs of the first element OR 17 _one whose output is connected to the first output of the block, the second output of which is connected to the fourth input of the block, from the fifth to seventh inputs of which are connected from the first to third inputs of the second element OR 17 ₂ the output of which is connected to the third output of the block, from the eighth to tenth inputs of which are connected from the first to third inputs of the third element OR 17 ₃ whose output is connected to the fourth output of the block, the eleventh to thirteenth inputs of which are connected from the first to third inputs of the fourth element OR 17 _four whose output is connected to the fifth output of the unit, the fourteenth and fifteenth inputs of which are connected respectively to its sixth and seventh outputs, from the sixteenth to eighteenth inputs of which are connected from the first to third inputs of the fifth element OR 17 ₅ whose output is connected to the eighth output of the block, from the nineteenth to twenty-first inputs of which are connected from the first to third inputs of the sixth element OR 17 ₆ whose output is connected to the ninth output of the block, the twenty-second, twenty-third and twenty-fourth inputs of which are connected respectively to the tenth, eleventh and twelfth outputs of the block, from the twenty-fifth to twenty-seventh inputs of which are connected from the first to third inputs of the seventh element OR 17 ₇ whose output is connected to the thirteenth output of the block, from the twenty-eighth to the thirtieth inputs of which are connected from the first to third inputs of the eighth element OR 17 ₈ the output of which is connected to the fourteenth output of the block, from the thirty-first to thirty-third inputs of which are connected from the first to third inputs of the ninth element OR 17 ₉ the output of which is connected to the fifteenth output of the block, the second block of elements OR 9 ₂ contains five elements OR 18 _one -eighteen ₅ , from the first to fifth inputs of the block are connected, respectively, each from the first to fifth of its outputs, from the sixth to eighth inputs of which are connected from the first to third inputs of the first element OR 18 _one whose output is connected to the sixth output of the block, the ninth input of which is connected to the seventh output of the block, from the tenth to twelfth inputs of which are connected from the first to third inputs of the second element OR 18 ₂ , the output of which is connected to the eighth output of the block, from the thirteenth to fifteenth inputs of which are connected from the first to third inputs of the third element OR 18 ₃ , the output of which is connected to the ninth output of the block, from the sixteenth to the twentieth inputs of the block are connected respectively each from the tenth to fourteenth of its outputs, from the twenty-first to twenty-third inputs of which are connected from the first to third inputs of the fourth element OR 18 _four the output of which is connected to the fifteenth output of the block, from the twenty-fourth to twenty-sixth inputs of which are connected from the first to third inputs of the fifth element OR 18 ₅ the output of which is connected to the sixteenth output of the block, from the twenty-seventh to thirty-fifth inputs of the block are connected respectively each from the seventeenth to twenty-fifth of its outputs, and the system control unit, when writing and reading the control point of the universal computers 11, contains a decoder 19, an address former 20, a trigger 21, four blocks of elements And 22 _one -22 _four consisting of N elements AND each, two buffer storage units 23 _one -23 ₂ and three blocks of elements And 24 _one -24 ₃ consisting of N elements And each, the outputs of which are connected respectively to the sixth, seventh and eighth outputs of the block, the first input of which is connected to its first output, the second input of the block is connected to the input of the decoder 19, the first, second and third outputs of which are connected to the first inputs respectively, the first second and third blocks of elements And 24 _one -24 ₃ and, accordingly, with the first, second and third inputs of the address generator 20, the output of which is connected to the second output of the block, the third output of which is connected to the zero input of the trigger 21 and the fourth input of the block, the third input of which is connected to the single input of the trigger 21, the single output of which is connected to the first input of the first block of elements And 22 _one the second input of which is connected to the fifth input of the block, the sixth input of which is connected to the first input of the fourth block of elements And 22 _four and with the third input of the first block of elements And 22 _one the output of which is connected to the input of the first buffer storage unit 23 _one the output of which is connected to the first input of the second block of elements And 22 _one the output of which is connected to the fourth output of the block, the seventh input of which is connected to the first input of the third block of elements And 22 ₃ and the second input of the second block of elements And 22 ₂ the third input of which is connected to the eighth input of the block, the ninth input of which is connected to its fifth output, the tenth input of the block is connected to the second input of the fourth block of elements And 22 _four the third input of which is connected to the output of the second buffer storage unit 23 _one whose input is connected to the output of the third block of elements And 22 ₃ , the second and third inputs of which are connected respectively with the eleventh and twelfth inputs of the block, the thirteenth input of which is connected with the fourth input of the fourth block of elements And 22 _four the output of which is connected to the combined second inputs of the first second and third blocks of elements And 24 _one -24 ₃ moreover, the control unit of the system in the event of a malfunction of one of the mainframe computers 12 contains a decoder 25, a shaper address 26, a trigger 27, three blocks of elements And 28 _one -28 ₃ consisting of N elements AND, four blocks of elements AND 29 _one -29 _four consisting of N elements AND each, a block of elements OR 30, consisting of N elements, a buffer storage unit 31 and an element And 32, the output of which is connected to the fourth output of the block, the first input of which is connected to the input of the decoder 25, the first, second and third outputs which are connected to the first inputs, respectively, of the first second and third blocks of elements And 28 _one -28 ₃ and accordingly, with the first, second and third inputs of the address shaper 26, the output of which is connected to the first output of the block, the second input of which is connected to the combined first inputs of the first and second blocks of elements And 29 _one and 29 ₂ , the first input of the And 32 element and the second output of the block, the third input of which is connected to its third output, the second input of the And 32 element and the single input of the trigger 27, the single output of which is connected to the combined second inputs of the first 29 _one second 29 ₂ third 29 ₃ and fourth 29 _four blocks of elements And, and the zero input of the trigger 27 is connected to the fourth input of the block and its combined fifth and sixth outputs, the fifth input of the block is connected to the combined second inputs of the first 28 _one second 28 ₂ and third 28 ₃ blocks of elements And, the outputs of which are connected respectively with the seventh, eighth and ninth outputs of the block, the sixth and seventh inputs of which are connected respectively with the third and fourth inputs of the third block of elements And 29 ₃ the fifth input of which is connected to the fourth input of the fourth block of elements And 29 ₃ and the eighth input of the block, the ninth and tenth inputs of which are connected respectively with the fourth and fifth inputs of the second block of elements And 29 ₂ the sixth input of which is connected to the fourth input of the third block of elements And 29 ₃ and the eleventh input of the block, the twelfth input of which is connected to its eleventh output, the thirteenth and fourteenth inputs of the block are connected respectively to the first and third inputs of the third block of elements And 29 ₃ the output of which is connected to the second input of the block of elements OR 30, the first input of which is connected to the output of the first block of elements AND 29 _one and the output is connected to the input of the buffer storage unit 31, the output of which is connected to the combined third input of the second block of elements And 29 ₂ and the first input of the fourth block of elements And 29 _four the third input of which is connected to the fifteenth input of the block, and the output is connected to the twelfth output of the block, the tenth output of which is connected to the output of the second block of AND elements 29 ₂ moreover, the communication unit 13 of all computers of the system with external subscribers contains two decoders 33 _one -33 ₂ , trigger 34, five elements OR 35 _one -35 ₅ , element NOT 36, sixteen blocks of elements AND 37 _one -37 ₁₆ consisting of N elements AND each, and five blocks of elements OR 38 _one -38 ₅ consisting of N elements AND each, the first and second inputs of the block are connected respectively with its first and second outputs and the first and second inputs of the first element OR 35 _one the output of which is connected to the single input of the trigger 34, the single output of which is connected to the combined second inputs of the second 37 ₂ third 37 ₃ tenth 37 ₁₀ and eleventh 37 _one blocks of elements And, and the zero output of the trigger 34 is connected to the combined first inputs of the seventh AND 37 ₇ eighth and 37 ₈ Ninth And 37 ₉ Fourteenth And 37 _fourteen Fifteenth And 37 _fifteen and sixteenth And 37 ₁₆ blocks of elements AND, the third input of the block is connected to the combined first input of the second AND 37 ₂ the third entrance of the tenth And 37 ₁₀ blocks of elements AND and the input of the element NOT 36, the output of which is connected to the combined first input of the third AND 37 ₃ the third entrance of the eleventh and 37 _eleven blocks of elements And, the fourth input of the block is connected to the input of the first decoder 33 _one , the first, second and third outputs of which are connected to the first inputs, respectively, of the second 35 ₂ third 35 ₃ and fourth 35 _four OR elements, the second inputs of which are connected with respectively the first, second and third outputs of the second decoder 33 ₂ the input of which is connected to the fifth input of the block, the sixth and seventh inputs of which are connected respectively with its eighth and ninth outputs and, respectively, with the first and second inputs of the fifth 35 ₅ OR element, the output of which is connected to the zero input of the trigger 34, the eighth, ninth and tenth inputs of the block are connected to the second inputs, respectively, of the first 37 _one second 37 ₂ and third 37 ₃ blocks of elements And, the outputs of which are connected to the corresponding inputs of the first 38 _one block of elements OR, the output of which is connected to the combined third inputs of the second 37 ₂ and third 37 ₃ blocks of elements And, the outputs of which are connected respectively to the third and fourth outputs of the block, the eleventh and twelfth inputs of which are connected to the first inputs, respectively, of the tenth 37 ₁₀ and eleventh 37 _eleven blocks of elements And, the outputs of which are connected respectively with the first and second inputs of the second 38 ₂ block of elements OR, the output of which is connected to the combined second inputs of the fourth 37 _four fifth 37 ₅ and sixth 37 ₆ blocks of elements And, the outputs of which are connected to the first inputs, respectively, of the third 38 ₃ fourth 38 _four and fifth 38 ₅ blocks of elements OR, the second inputs of which are connected to the outputs, respectively, of the seventh 37 ₇ eighth 37 ₈ and ninth 37 ₉ blocks of elements And, the second inputs of which are connected respectively with the thirteenth, fourteenth and fifteenth inputs of the block, the tenth eleventh and twelfth outputs of which are connected with the outputs of the third 38 ₃ fourth 38 _four and fifth 38 ₃ blocks of elements OR, the fifth, sixth and seventh outputs of the block are connected to the outputs of the fourteenth AND 37, respectively _fourteen Fifteenth And 37 _fifteen and sixteenth And 37 ₁₆ blocks of elements And, the second inputs of which are connected to the second inputs, respectively, of the first 37 _one second 37 ₂ and third 37 ₃ blocks of elements And, the first inputs of which are connected to the outputs, respectively, of the second 35 ₂ third 35 ₃ and fourth 35 _four OR element, and the system control unit in the event of a malfunction of the mainframe memory 14 contains a decoder 39, an address generator 40, a trigger 41, three elements And 42 _one -42 ₃ , eight blocks of elements AND 43 _one -43 ₈ consisting of N elements AND each, and a block of elements OR 44, the output of which is connected to the second input of the fourth block of elements AND 43 _four the output of which is connected to the seventh output of the block, the first input of which is connected to the input of the decoder 39, the first output of which is connected to the combined first inputs of the first 42 _one element And, the first 43 _one and the sixth 43 ₆ blocks of elements And and the shaper address 40, the second input of which is connected to the combined first inputs of the second 42 ₂ element And, second 43 ₃ and seventh 43 ₇ blocks of elements And and the second output of the decoder 39, the third output of which is connected to the combined first inputs of the third 42 ₃ element And, third 43 ₃ and eighth 43 ₈ blocks of elements And and the third input of the address generator 40, the output of which is connected to the first output of the block, the second, third and fourth outputs of which are connected to the outputs, respectively, of the first 42 _one second 42 ₂ and 42 ₃ the third elements And, the second inputs of which are combined and connected to the second input of the block, the third input of which is connected to its fifth output and the single input of the trigger 41, the single output of which is connected to the combined first inputs of the fourth 43 _four and fifth 43 ₅ elements And, and the zero input of the trigger is connected to the combined fourth input and sixth output of the block, the fifth, sixth and seventh inputs of which are connected to the second inputs, respectively, of the first 43 _one second 43 ₂ and third 43 ₃ blocks of AND elements, the outputs of which are connected respectively to the first, second, and third inputs of the OR element 44, the eighth input of the block is connected to the combined third inputs of the fourth 43 _four and fifth 43 ₅ elements And, the ninth input of the block is connected to the second input of the fifth 43 ₅ element And, the output of which is connected to the combined second inputs of the sixth 43 ₆ seventh 43 ₇ and eighth 43 ₈ blocks of elements And, the outputs of which are connected respectively with the eighth, ninth and tenth outputs of the block, and the control unit of the system in the event of a malfunction in the OP 15 contains a decoder 45, a trigger 46, ten blocks of elements And 47 _one -47 ₁₀ consisting of N elements AND each, and two blocks of elements OR 48 _one -48 ₂ consisting of N elements OR, the first input of the block is connected to its first output and a single input of the trigger 46, the zero input of which is connected to the second input of the block and its second output, the third input of the block is connected to the input of the decoder 45, the first output of which is connected to the combined first the entrances of the first 47 _one and the sixth 47 ₆ blocks of elements And, the second output of the decoder 45 is connected to the combined first inputs of the second 47 ₂ and seventh 47 ₇ blocks of elements And, the third output of the decoder 45 is connected to the combined first inputs of the third 47 ₃ and eighth 47 ₈ blocks of elements And, the fourth, fifth and sixth inputs of the block are connected to the second inputs, respectively, of the first 47 _one second 47 ₂ and third 47 ₃ blocks of elements And, the outputs of which are connected respectively with the first, second and third inputs of the first 48 _one block of elements OR, the output of which is connected to the combined second inputs of the fourth 47 _four and fifth 47 ₅ blocks of elements And, the outputs of which are connected respectively with the third and fourth outputs of the block, the fifth, sixth and seventh outputs of which are connected with the outputs, respectively, of the sixth 47 ₆ seventh 47 ₇ and eighth 47 ₈ blocks of elements And, the second inputs of which are combined and connected to the output of the second 48 ₂ block of elements OR, the first and second inputs of which are connected to the outputs, respectively, of the ninth 47 ₉ and tenth 47 ₁₀ blocks of elements And, the second inputs of which are connected respectively to the seventh and eighth inputs of the block, a single output of the trigger 46 is connected to the combined first inputs of the fourth 47 _four and ninth 47 ₉ blocks of elements And, and the zero output of the trigger 46 is connected to the combined first inputs of the fifth 47 ₅ and tenth 47 ₁₀ blocks of elements I.

In the table. 1 provides information about the input, and in table 2 - about the output signals of the control device 2.

Table number 1 one. input of a request to record CT in the memory of the control computer from the first universal computer 2. input of a request to record CT in the memory of the control computer from the second universal computer 3. input of a request to record CT in the memory of the control computer from the third universal computer four. the input of the number of the universal computer, which turned to the control computer to record information CT 5. readiness input of the first universal computer for transmitting CT information 6. readiness input of the second universal computer for transmitting CT information 7. readiness input of the third universal computer for transmitting CT information 8. input end of the transmission of information of the first universal computer for transmitting CT information 9. input end of the transmission of information of the second universal computer for transmitting CT information 10. input end of the transmission of information of the third universal computer for transmitting CT information eleven. clock input of the first universal computer 12. clock input of the second universal computer 13. clock input of the third universal computer fourteen. control computer clock input fifteen. control computer readiness input for receiving CT information from the backup 16. failure signal input from the first universal computer 17. failure signal input from the second universal computer eighteen. fault input from a third universal computer 19. readiness input of the first universal computer for receiving CT information twenty. readiness input of the second universal computer for

receiving CT information 21. readiness input of the third universal computer for receiving CT information 22. control computer information output 23. control computer readiness input for information output 24. input end of the output of the information of the control computer to the buffer 25. fault input of the first universal computer 26. fault input of the second mainframe computer 27. fault input of the third universal computer 28. health signal input of the first universal computer 29. health signal input of the second universal computer thirty. health signal input of the third universal computer 31. stop / start input of the first universal computer from the host computer 32. stop / start input of the second universal computer from the host computer 33 stop / start input of the third universal computer from the host computer 34 standby input for receiving information from CT 35 backup clock input 36 input request for recording CT from the backup to the memory of the control computer at the address of the faulty 37 backup standby input for transmitting CT information 38 Information output of the backup computer 39 overload signal input of the first universal computer 40 overload signal input of the second universal computer 41 overload signal input of the third universal computer 42 signal input that the backup computer is not busy running the program 43 the input of the overload number of the first universal computer that turned to the control computer 44 the input of the overload number of the second universal computer which turned to the control computer 45 the input of the overload number of the third universal computer which turned to the control computer 46 overload elimination signal input first

universal computer 47. overload elimination signal input of the second universal computer 48. input overload elimination signal of the third universal computer 49. information input of the first battery fifty. second battery information input 51. information input of the third battery 52. backup computer information input 53. information input control computer 54. fault signal input of the memory of the first universal computer 55. fault signal input of the second universal computer memory 56. fault signal input of the memory of the third universal computer 57. service signal input of the memory of the first universal computer 58 service signal input memory of the second universal computer 59 service signal input memory of the third universal computer 60 Information input communication with OP 61 OP fault input 62 operability signal input OP 63 number of the universal computer that turned to the OP for a record 64 information output of the first universal computer 65 information output of the second universal computer 66 information output of the third universal computer 67 backup input information input 68 information input of the main OP

Table number 2 one. the output of the request for recording CT on the input of the control computer 2. output signal transmission about the end of the recording from the mainframe of information in the buffer UU 3. information output of the transfer of information from the buffer UU to the input of the control computer four. fault output 5. information output of information transfer from the UU buffer to the input of the first universal computer 6. information output of the transfer of information from the buffer UU to the input of the second universal computer 7. information output of the transfer of information from the buffer UU to the input of the third universal computer 8. output address of the reception / transmission of information to the input of the control computer 9. signal output that the backup computer is not busy running the program 10. output start backup computer eleven. output stop the backup computer on a signal serviceable universal computer 12. stop / start output of the first universal computer 13. stop / start output of the second universal computer fourteen. stop / start output of the third universal computer fifteen. information output of the transfer of information from the buffer UU to the input of the backup computer 16. information output of information transfer from the UU buffer to the input of the control computer from the backup computer 17. mainframe malfunction signal output eighteen. universal computer overload signal output 19. information output of information transfer from an external subscriber to the backup computer input twenty. information output of information transfer from an external subscriber to the control computer input 21. information output of information transfer from an external subscriber to the input of the first universal computer 22. information output of information transfer from an external subscriber to the input of the second universal computer 23. information output of information transfer from an external subscriber to the input of a third universal computer 24. mainframe no-load signal output 25. information output of the transfer of information from a backup or control computer to the input of the first

external input 26. information output of information transfer from the backup or control computer to the input of the second external subscriber to the input 27. information output of information transfer from the backup or control computer to the input of the third external subscriber to the input 28. universal computer health signal output 29. output address of the reception / transmission of information to the input OP thirty. stop / start output of the first universal computer 31. stop / start output of the second universal computer 32. stop / start output of the third universal computer 33. the fault signal output of the mainframe memory to the control computer input 34. the output of the working condition of the memory of the universal computer to the input of the control computer 35. communication output with OP 36. information output OP for the first universal computer 37. information output OP for the second universal computer 38. information output OP for the third universal computer 39. OP fault signal output to the control computer input 40. output signal health OP to the input of the control computer 41. communication output from the backup OP 42. information output of communication with the main OP 43. communication output of the first universal computer with the main or standby OP 44. communication output of the first universal computer with the main or standby OP 45. communication output of the first universal computer with the main or standby OP

During operation of the aircraft (figure 1), each universal computer 1 executes an independent program or an independent element of one program, and the control computer 4 monitors the operation of universal computers. In each universal machine, a diagnostic (control) task is periodically launched, designed to determine the degree of processor and memory utilization with a predetermined time interval for its solution and the required amount of memory. During normal operation of the computer, i.e. receiving the correct result of the diagnostic task for a fixed time interval, the processor of each machine generates internal signals of compliance with the correct operation. In the event of a failure in the operation of any universal computer, for example, in the first computer 11, the diagnostic problem cannot be solved in a given time interval or in the absence of the necessary memory, therefore, mismatch signals from this computer are generated for correct operation. Inconsistency signals are fed to the input of the host computer 4. To access the host computer 4, an additional command is entered in the codes of the universal machine commands, when it appears, a signal is sent to the host machine.

If at the time of the call to the host computer 4 she had not completed the subroutine of the previous call, then the processing of the new call will be accepted for execution after the processing of the previous call.

Each subroutine of the host computer 4 begins with an exchange command, from which the corresponding exchange subroutine is selected from (memory). A set of such routines is stored in the memory of the host computer 4 and is intended for flexible control of the exchange of information between the host computer 4 and other computers of the system. After each cycle of the standard routine and the exchange of information, the control computer 4 returns to its initial state.

In the host computer 4, a determination is made which of the mainframe computers turned to it, and the type of non-compliance signal, which has its own code, is determined. Depending on the type of non-compliance signal in the control computer 4, the corresponding subprogram is selected and its execution begins. The reasons for which a non-compliance signal can be issued can be different: this is a malfunction of the computer or its elements; the inability of the processor of the universal computer 1 to execute the program for a certain time; high load of the general memory of the aircraft 7 or 8, or the memory of a universal computer 4.

As an example, we consider the operation of the aircraft in the event of a mismatch signal, which corresponds to a malfunction of one of the three universal computers 1 ₁ -1 ₃ .

In this case, three universal computers 1 are considered basic and solve dependent or independent tasks. The fourth computer. 3 is a universal backup computer. Universal backup computer, backup computer 3, is in the hot standby mode. At each point in time, all external subscribers 5 ₁ -5 _{3 are} connected to working computers 1 ₁ -1 ₃ .

During the operation of the system, as necessary (the need is determined by a specific algorithm of the system) in each universal computer 1, at certain given intervals, a control point (CT) is executed, i.e. saving intermediate results of program execution. The results of the program execution at a given moment in time of each mainframe computer 1 are stored and fed through the control device 2 to the memory of the control computer 4. This allows you to return to the interrupted program at any time at the time of the last stored in the CT.

The recording signal in the CT (Figure 2 ... Figure 5) from the output of, for example, the first universal computer 11 is fed to the first input of the control device 2 and then through the block of elements OR 9 _{1, the} request signal for writing the CT to the control computer is received at the first input 4 of the system control unit 11 when writing and reading the control point of the universal computer (Figure 5). At its second input, the number of the mainframe computer (in this case, the first universal computer 1 ₁ ) is received, which turned to the control computer for recording CT information, and at the third input, the readiness signal of the universal computer for transmitting CT information. The request signal for recording CT in the memory of the host computer 4 is fed to the first output of the unit and then through the first output of the control device of system 2 to the input of the host computer 4 to prepare for receiving information on the CT. The number of the first universal computer 1 ₁ comes from the second output of the block to the input of the decoder 19, and from its outputs to the inputs of the address generator 20. In the address generator 20, the starting address is formed in the memory of the control computer 4, which corresponds to the number of the universal computer 1 ₁ , which comes through the eighth the output of the control system 2 to the input of the control computer 4. The signal of readiness of the first universal computer 11 for transmitting CT information is supplied to the single input of the trigger 21 and sets it to a single state. The signal from the single output of the trigger 21 is supplied to the first inputs of the first block of elements And 22 ₁ , the second and third inputs of which respectively receive CT information from the fifth input and clock pulses of the first universal computer 11 from the sixth input. According to the clock signals of the first universal computer 11, the CT information is recorded in the first buffer storage unit 23 ₁ .

Upon completion of the recording of information CT in the first buffer storage unit 23 ₁ from the fourth input of the block receives the signal the end of the transmission of information of the first universal computer 1 ₁ for transmitting information CT. This signal is fed to the output of the block and sets the trigger 21 to zero. The recording of information in the first buffer storage unit 231 is terminated and upon the availability of the host computer 4 can be transferred to its memory. The signal of readiness of the control computer for receiving CT information from the eighth input of the block is fed to the third input of the second block of AND 22 ₂ elements, the first input of which receives CT information from the output of the buffer storage unit 23 ₁ , and the clock from the seventh input of the control computer 4. According to the clock signals of the host computer 4, the information of the CT through the third output of the control device of the system 2 is recorded at the appropriate address in the memory of the host computer 4.

The failure signal, for example, from the first universal computer 11, which is fed to the sixteenth input of the system control device 2 and then through the first block of OR elements 9 ₁ to the ninth input and fifth output of the system control unit 11 when writing and reading the control point of the universal computer, is received the fourth output of the control device of system 2, and from it to the input of the control computer 4. By the signal of readiness of the control computer 4 to output CT information, which through the first block of OR elements 9 ₁ enters the twelfth input of the system control block 11 when writing and reading the control point of the mainframe computers and then to the third input of the third block of elements And 223, the first and second inputs of which receive clock pulses and CT information from the host computer 4, respectively. Based on the clock signals of the host computer 4, the CT information is recorded in the second buffer memory block 23 ₂ .

The signals of the end of the issuance of the information of the control computer 4 to the second buffer storage unit 23 _{2 of the} readiness of the first universal computer 11 for receiving information from the CT and its clock pulses, which from the corresponding outputs of the first block of elements OR 9 _{1 of} the control system 2 are supplied to the thirteenth, tenth and sixth inputs, respectively block and then to the fourth, second and first inputs of the fourth block of elements And 22 _4, respectively. According to these signals, information from the output of the second buffer storage unit 23 ₂ is issued through the fifth output of the system control device 2 to the input of the first universal computer 1 ₁ .

When recording CT information or its issuance for the second mainframe computer 1 ₂ or the third universal computer 1 _{3, the} process in the system control unit 11 when writing and reading the control point of the universal computer is the same. The only difference is the number of the universal computer. So when issuing information from the memory of the host computer 4 to the input of the corresponding universal computer is determined by the decoder 19 and the blocks of elements And 24 ₁ -24 ₃ .

In the event of a malfunction of one of the universal computers 1 _i, the mismatch signal "malfunction_i", where i is equal to the number of the computer, is output from the output of this computer to the input of the system control unit 2. The malfunctioning computer is detected in the control device of system 2, and the malfunction signal is "malfunction_i" with its output goes to the input of the control computer 4.

Upon receipt of the mismatch signal "malfunction_i" at the input of the control computer 4, the control computer 4 determines the malfunction of the i-th universal computer 1 _i and the signal arrival time and stops its operation.

Next, the system control device 2 checks whether the universal backup computer 3 is occupied or not. If the universal backup computer 3 is not busy with the program, the control computer 4 reads the data of the last CT from the memory and transfers them to the universal backup computer 3 through the control device of the system 2 along with a signal to start work on the program.

At the same time, signals are generated in the control device of system 2, which, by controlling the I / O channel, switch the external subscriber from the faulty computer 1 _i to the universal standby computer 3. After connecting the universal standby computer 3, the input / output channel goes into the mode of receiving and transmitting information. Information is transferred between the universal standby computer 3 and the host computer 4 until the input / output channel gives an end signal for the exchange. The inter-machine exchange takes place, as a rule, in exclusive mode, the control computer 4 begins with the command “Start I / O”. This command specifies the address of one of the directions of the input-output channel. After the end of the exchange, the universal backup computer 3 begins to work with the arrival of a start pulse.

If the universal backup computer 3 is busy with the execution of the program, then the control computer 4 takes on the role of the universal backup computer 3. In this case, the inter-machine exchange is not performed, but only the data transmission channels are reconfigured with the control computer 4.

Subsequently, the universal backup computer 3 or the control computer 4 operates as the main one, and the faulty universal computer 1 _i switches to the troubleshooting mode and repair mode.

Thus, despite the failure of one computer 1 _{i, the} system continues to perform its functions, information is exchanged between all necessary external subscribers 5 _i and the computer 1 _{i of the} system.

In the event of a malfunction of one of the mainframes 1 _{i, the} control and information signals to the system control units 12 in the event of a malfunction of one of the mainframes and 13 of the connection of the mainframes 1 _{i of the} system with external subscribers (Fig.6 and Fig.7) coming through the inputs and the outputs of the control system 2 (Figure 2 ... Figure 4).

The malfunction signal and number, for example, of the first universal computer 11, simultaneously arrives at the third and first inputs of the system control unit 12, respectively, in the event of a malfunction of one of the universal computers and at the first and fourth inputs of the communication unit 13 of the universal computer 1 _{i of the} system with external subscribers. The signal number of the first universal computer 1 ₁ , which turned to the control computer 4 from the first input of the system control unit 12 when a malfunction of one of the universal computers occurs (Fig. 6), is fed to the input of the decoder 25, and from its outputs to the inputs of the address shaper 26. In the shaper address 26 is formed, the starting address in the memory of the host computer 4, corresponding to the number of the first universal computer 1 ₁ , which from the first output of the block is fed to the input of the host computer 4. The fault signal of the first mainframe computer 1 ₁ comes from the third the input of the block to its third output and then to the input of the control computer 4, as well as to the single input of the trigger 27 and sets it to a single state. When a malfunction signal is received at the input of the control computer 4 from its output to the fifth input of the block, the stop / start signal of the universal computer 1 _i is issued, which is fed to the second inputs of the blocks of elements And 28 ₁ -28 ₃ , the first inputs of which receive signals from the output of the decoder 25 Depending on the number of the faulty universal computer (in this case, the first universal computer 1 ₁ ), a stop / start signal is issued to the seventh output of the unit and then to the input of the first universal computer 1 ₁ . The first universal computer 1 ₁ stops. Then, a check is made whether the universal backup computer 3 is busy or not. If the universal backup computer 3 is not busy with the program, then a signal is sent to the second input and then to the second output of the block that the universal backup computer 3 is not busy with the program. This signal from the second output is fed to the input of the control computer 4, as well as to the first inputs of the element And 32 of the first and second block of elements And 29 ₁ and 29 ₂ . To ensure the execution of the program of the faulty first universal computer 11 on the universal backup computer 3, it is necessary to load information from the memory of the control computer 4 from the last CT in its memory. Information from the memory of the host computer 4 for the last CT is received from the seventh input of the block to the fourth input of the first block of elements And 29 ₁ , the second input of which receives a signal from the single output of trigger 27, and the fifth input receives clock pulses of the host computer 4. As soon as the host computer 4 is ready for issuing information from the sixth block input to the third input of the first block elements and 29 ₁ Received signal control computer 4 ready for delivery of the information in the buffer for a universal backup computer 3. sync signals yn control computer 4 deformations of CT through the block elements 30 or written into the buffer memory unit 31. After the CT issuing information on the ninth block end signal is input to buffer data output from the control computer 4, which is supplied to the fourth input element of the second block and 29 ₂ on the fifth and the sixth inputs of which are received from the block inputs, respectively, the readiness signals of the universal standby computer 3 for receiving CT information and synchronization pulses of the universal standby computer 3. The signal from e is received at the second input of the second block of elements And 29 ₂ trigger output 27, and its third input receives information from the output of the buffer storage unit 31. By these signals, information from the output of the buffer storage unit 31 is provided to the input of the universal backup computer 3. Since the second input of the And 32 element from the third input of the block If the mainframe malfunctions, then after receiving the CT information, the start-up signal of the universal backup computer 3 is issued to the fourth output of the block. The universal backup computer 3 starts to run the program.

During the operation of the universal backup computer 3, as necessary, at certain specified intervals, a control point (CT) is performed, i.e. saving intermediate results of program execution. The results of the program execution at a given moment in time by the universal backup computer 3 are stored in the same way as during the operation of the universal computer 1 _i through the third block of elements AND 29 ₃ , the block of elements OR 30, the buffer storage block 31 and the fourth block of elements AND 29 ₄ of the control unit 12 system in the event of a malfunction of one of the universal computers (Fig.6) are received in the memory of the host computer 4.

In addition, in the event of a malfunction of the mainframe computer 1 _i, it is necessary to switch the external subscriber 5 _i from the faulty computer 1 _i to the universal backup computer 3. To enable the ability to switch the external subscriber 5 _i, the fault signal and the number, for example, of the first mainframe computer 1 _{1 are} respectively the first and fourth inputs of the communication unit 13 of the universal computer 1 _i system with external subscribers (Fig.7). Moreover, if the universal standby computer 3 is not busy with the execution of the program, then a signal is received at the third input of the block that the backup computer is not busy with the execution of the program. The signal number of the first universal computer 1 ₁ , which is faulty, from the fourth input of the block goes to the input of the first decoder 33 ₁ , from the outputs of which go to the second inputs of the second 35 ₂ , third 35 ₃ and fourth 35 ₄ OR elements, respectively, and from their outputs to the first inputs, respectively, from the first to the third 37 ₁ -37 ₃ blocks of elements I. The second inputs from the first to the third 37 ₁ -37 ₃ blocks of elements And are connected to the information inputs from the first to third external subscribers 5 ₁ -5 ₃ . Thus, depending on which universal computer 1 _{i is} faulty (the first one in this case), the subscriber’s information input with this number will be connected to the universal backup computer 3. Information from the first external subscriber 5 ₁ from the eighth block input comes through the open first a block of AND elements 37 ₁ and a first block of OR elements 38 ₁ to the third inputs of the second 37 ₂ and third 37 ₃ blocks of AND elements, the second inputs of which receive a signal from a single output of a trigger 34. The single input of a trigger 34 enters through the first element OR 35 ₁ si I detected a malfunction of the universal computer 11. The first input of the second 37 ₂ block of elements AND receives a signal from the third input of the block that the universal backup computer 3 is not busy with the program, and the first input of the third 37 ₃ blocks of elements And receives through the element NOT 36 inverse a signal that the universal backup computer 3 is not busy with the program, i.e. universal backup computer 3 is busy running the program. In this case, information from the first external subscriber 5 ₁ through the open second 37 ₂ block of elements And is fed to the third output of the block and then to the input of the universal backup computer 3.

If the universal backup computer 3 turns out to be busy with the program, then the third 37 ₃ block of AND elements will be opened at the first input and the information from the first external subscriber 5 ₁ will go to the fourth output of the block and then to the input of the control computer 4.

Information obtained as a result of running a program in a universal backup computer 3 or control computer 4, which comes from the eleventh and twelfth outputs of the block, respectively, is supplied to the first inputs of the tenth 37 ₁₀ and eleventh 37 ₁₁ blocks of AND elements, respectively, the second inputs of which are combined and connected to a single output of the trigger 34. If the universal backup computer 3 is not busy, then the tenth 37 ₁₀ block of AND elements is open at the third inputs, and the eleventh 37 ₁₁ block of AND elements will be closed. Information from the universal backup computer 3 through the open tenth 37 ₁₀ block of AND elements and the second block of OR elements 38 _{2 is} fed to the second inputs from the fourth 37 ₄ through the sixth 37 ₆ blocks of AND elements, one of which (in this case the fourth, since the first is faulty universal computer 1 ₁ ) the signal from the first output of the first decoder 33 ₁ through the second element OR 35 ₂ is open. From the output of the fourth 37 ₄ block of elements AND through the third block of elements OR 38 _{3 the} information goes to the tenth output of the block and then to the input of the first external subscriber 5 ₁ .

If the universal backup computer 3 is busy, then the eleventh 37 ₁₁ block of AND elements is open, and the tenth 37 ₁₀ block of AND elements will be closed. Information from the control computer 4 through the open eleventh 37 ₁₁ block of AND elements is supplied to the second block of OR elements 38 ₂ and then to the tenth output of the block and to the input of the first external subscriber 5 ₁ .

After eliminating the malfunction, the signal of operability of the universal computer through the fifth element OR 35 ₁ trigger 34 is set to zero. The second 37 ₂ , the third 37 ₃ , the tenth 37 ₁₀ and the eleventh 37 ₁₁ blocks of elements And will be closed, from the seventh to the ninth 37 ₇ -37 ₉ and from the fourteenth to sixteenth 37 ₁₄ -37 ₁₆ will be open. Through the open blocks of elements And the information inputs of external subscribers 5 ₁ -5 ₃ will be connected to the information inputs of the corresponding universal computers 1 ₁ -1 ₃ .

The work of the aircraft in the event of a mismatch signal that corresponds to an emergency situation in the operation of one of the universal computers 1 _i , which most likely can be caused by overload, associated for example with insufficient memory or the execution time of a given program

If the memory load decreases, the signal “overload” will not be issued, in a similar way, the control computer 4 will restore the memory data of the i-th universal computer 1 _i through the control device 2 and its operation will continue in normal mode.

The overload of the universal computer 1 _i can be determined by the external subscriber 5 _i . For example, the external subscriber 5 _i in the process of functioning counts the execution time of the program at his request or the excess of the maximum number of queued requests. These signals from external subscribers 5 _i are fed through the control device 2 to the input of the control computer 4, which controls the state of the aircraft.

In this case, part of the functions for processing and obtaining results during the execution of the universal computer program 1 _i takes the universal backup computer 3 or the control computer 4, if the universal backup computer 3 is busy.

In any case, the overload signal of the universal computer 1 _{i is} fed to the second input of the communication unit 13 of all computers of the system with external subscribers (Fig. 7), and the fifth input is the number of the overloaded universal computer 1 _i . The work of the aircraft in the event of the overload signal of the mainframe 1 or elimination of the overload of the mainframe 1 _i arriving at the seventh input of the unit, is performed similarly to the issuing of malfunctions of the mainframe and the health of the mainframe. The difference lies in the fact that when overloaded, the second decoder 33 ₂ and the first 35 ₁ and fifth 35 ₂ OR elements are activated (Fig. 7).

During the operation of one of the universal computers 1 _i , a mismatch signal can be generated that corresponds to an emergency situation in the memory operation, which most likely can be caused by overload, associated, for example, with insufficient memory or its malfunction.

The signal of the malfunction of the mainframe memory comes to the third input and then to the fifth output of the system control unit 14 in the event of a malfunction of the mainframe memory (Fig. 8). The signal from the fifth output of the block is fed to the input of the control computer 4. By this signal, the control computer 4 determines the fact of an emergency situation in operation, the signal arrival time, from which universal computer 1 _{i the} signal arrived and issues a command to check the operability by the memory unit by means of self-monitoring. Since a CT is performed in advance at predetermined time intervals, the control computer 4 reads the data of the last CT from the memory and, through control device 2, transfers them to the aircraft operating system. The control device 2 switches this universal computer 1 _i to work with the OP and start it if the program has been suspended. At the time of checking the operability of the memory, this i-th universal computer 1 _i switches to work with the general memory (OP) of the aircraft through the BU buffer (in the OP, a backup zone is usually provided for this case).

The failed memory is self-controlled by reading the same information first in the first cycle from one section, and after a while in another cycle from another section. The read information goes to the memory error signal generating unit for comparison.

In this case, two options for the functioning of the system are possible. In the first variant, the information read at different times and from different sections coincides (a failure actually occurred). The output generates a signal "no error", which is fed to the input of the host computer 4.

If the information read at different times and from different sections does not match, then an “error” signal is issued. This signal is fed to the input of the host computer 4. This signal from the output to the host computer 4 is fed to the fifty-fourth, fifty-fifth or fifty-sixth (depending on which of the universal computers 1 _i turned out to be a faulty memory) the inputs of the control system 2 and further to the third input of the system control unit 14 in the event of a malfunction of the mainframe memory.

Simultaneously with the fault signal of the mainframe memory, the signal of the number of the fault of the universal computer memory 1 _i is received at the first input of the block. The number of the first universal computer 1 ₁ (for example, a memory malfunction occurred in the first universal computer 1 ₁ ) comes from the first output of the block to the input of the decoder 39, and from its outputs to the inputs of the address generator 40. In the address generator 40, the initial address in block 7 of the main OP corresponding to the number of the universal computer 1 ₁ . In addition, the outputs of the decoder 39 are connected to the first inputs of the corresponding first to third blocks of elements AND 43 ₁ -43 ₃ , the second inputs of which are connected to the corresponding information inputs of the universal computer 1 _i . The first block of AND 43 ₁ elements turns out to be open at the first input, and information from the first universal computer 1 ₁ enters through the block of OR elements 44 to the second inputs of the fourth block of AND 43 ₁ elements. The fourth block of elements And 43 ₁ is open at the first inputs from the single output of the trigger 41, which was set to a single state by a fault signal of the mainframe memory from the third input of the block. According to the clock signals of the first universal computer 1 ₁ , coming from the eighth input of the block to the third inputs of the fourth block of elements AND 43 ₁ , information from it is transmitted to the seventh output of the block and then to the input of block 7 of the main OP.

Information is transmitted from the output of block 7 of the main OP to the first universal computer 1 ₁ by sync pulses through the open fifth and sixth blocks of AND 43 ₅ elements (Fig. 8).

After troubleshooting, the fourth input of the block receives a working signal of the memory of the universal computer, which sets the trigger 41 to zero. The fourth 434 and fifth 435 blocks of AND elements will be closed at the first inputs, and information through them will not be received and issued, the aircraft will operate normally.

At the time of switching to work with block 7 of the main OP, the universal computer 1 _i stops at the stop / start signal of the universal computer, which is fed to the second inputs from the first to third elements AND 42 ₁ -42 ₃ , the first inputs of which receive signals from the corresponding outputs of the decoder 39. After performing the switch, the universal computer 1 _{i is} similarly started.

An abnormal situation during the operation of the aircraft may occur in block 7 of the main OP, which may be associated with the occurrence of a malfunction, overload, or malfunction when writing or reading information. Self-monitoring and error correction is possible only if redundancy of information capacity is ensured in comparison with the necessary, therefore, the aircraft uses memory with excess information capacity. The signal about the occurrence of an emergency in the memory goes to the control computer 4 BC. According to this signal, the control computer 4 through the control device 2 ensures the operation of the aircraft with memory in block 8 of the backup OP, which is located in the hot reserve. In this case, the work of the aircraft will not stop, but only, perhaps, its overall performance will decrease during the switching to block 8 of the standby OP.

The OP malfunction signal (Fig. 9) from the first input of the system control unit 15 when a malfunction occurs in the OP is supplied to the first output of the unit and then to the input of the control computer 4. In addition, this signal is fed to the single input of the trigger 46. The signal from the single output of the trigger 46 opens on the first inputs the fourth 47 ₄ and the ninth 47 ₉ blocks of elements I. When the aircraft is operating, the universal computers 1 _i turn to the OP for writing or reading. The number of the universal computer 1 _i , which turned to the OP, goes to the third input of the block, and from it to the input of the decoder 45. Suppose that the second universal computer 13 turned to the OP. From the second output of the decoder 45, an enable signal will be issued to the first inputs of the second 47 ₂ and seventh 47 ₇ blocks of elements I. The information from the second universal computer 13 comes to the second input of the second 47 ₂ blocks of elements And from the fifth input of the block 13. This information is output from the second 47 ₂ blocks of AND elements through the first 48 ₁ block of OR elements and the open fourth 47 ₄ block elements And comes n and the output of the block and further to the input of block 8 of the backup OP.

Information from the output of block 8 of the standby OP goes to the seventh input of the block, and from it to the second inputs of the ninth 47 ₉ blocks of AND elements, which is open at the first inputs. From the output of the ninth 47 ₉ block of AND elements, information through the second 48 ₃ block of OR elements and the open seventh 47 ₇ block of AND elements is fed to the output of the block and then to the input of the second universal computer 12. Thus, communication between any universal computer 1 _i with block 8 is provided backup OP.

After troubleshooting in block 7 of the main OP to the second input of the block (Fig. 9), the OP operational signal is received, which is fed to the second output of the block and then to the control computer 4. In addition, this signal from the second input of the block sets the trigger to zero 46, thereby closing on the first inputs the fourth 47 ₄ and 9th 47 ₉ blocks of elements And and opening on the first inputs the fifth 47 ₅ and tenth 47 ₁₀ blocks of elements I. Due to the open fifth 47 ₅ and tenth 47 ₁₀ blocks of elements And between any universal computer 1; with block 7 of the main OP and the aircraft will continue to operate normally.

The work of the aircraft in providing control over the progress of programs

The system works when monitoring the progress of programs as follows.

In any universal computer 1 _{i, the} processor via the address range loading bus places in its memory block ranges of the controlled addresses of the random access memory, and for each address range, signs of permitted states (permitted actions) are assigned:

- the allowed privilege level of the current program;

- type of appeal (read / write);

- access mode (fetching commands, working with the stack, system tables, working with data, etc.);

- processor operating mode (real mode, protected mode, system management mode, hypervisor mode, etc.).

When the processor, during the execution of the program, makes a request to the RAM of the universal computer 1 _i by forming the current address of the random access memory, the following actions occur:

- the current address is compared with all ranges of monitored addresses recorded in the memory block of address ranges;

- when the current address falls into any of the ranges of monitored addresses recorded in the address range memory block, the address comparison unit reads from the memory block of the mainframe computer 1 _i address ranges the allowed states for this address range;

- allowed states for a read range of addresses are compared with the current state of the processor (privilege level, type of access, access mode, operation mode, etc.);

- if the allowed states correspond to the current state of the processor, then the address comparison unit in the mainframe computer 1 _i does not initiate an error signal and the program (calculation) execution process is not interrupted;

- if a mismatch is detected, then the address comparison unit issues a processor interruption signal;

- this signal stops the process of executing the program in which the violation is detected, and, for example, starts the monitoring program (through the interrupt system);

The control procedures are entered by the Call machine command, and the return point (address of the next command) is stored in the call stack of the universal computer processor 1 _i .

After the test is completed, the control procedure is exited by the Ret command, which reads the return address from the call stack and transfers control to the processor to it.

When monitoring the progress of programs in the universal computer 1 _i, during the loading of data blocks from the network or external media into the RAM device, the memory addresses of the location of these data blocks are stored.

In addition, for each such data block of the mainframe computer 1 _i in the hash function calculation unit, the corresponding hash function is calculated.

The addresses of the placement of data blocks from external media and the network, and the calculated hash functions corresponding to these blocks are stored in the data address memory block and the hash functions of the universal computer 1 _i, respectively.

When executing the program in the universal computer 1 _{i, the} addresses of the instruction fetch by the processor are compared with the addresses of the location of data blocks from the network or external media stored in the block.

If the addresses and the hash function of the program blocks do not match, program execution is interrupted and the processor proceeds to the control procedures with the corresponding signal being sent to control device 2 and to the input of the control computer. If the hash function addresses match, then the program execution continues.

The cancellation of information in the memory block of the addresses of the placement of data blocks and the calculation unit of the hash function of the data blocks occurs after the information is rewritten into the address space of the random access memory.

If the interruption of the universal computer program 1 _{i is} carried out, then to ensure a return to the execution of the interrupted program due to the selection and reception of CT information (Figure 5).

The interruption of programs is as follows.

The interrupt signal from the control device of the mainframe computer 1 _i stores the state of the interrupted program by simultaneously transferring the contents of all the registers to the memory cells of the storage devices and writing this information as CT information to the memory, for example, to the top of the corresponding stack of the universal computer 1 _i . The same signal sets the time for recording information in the storage device and enters the first input of the stack pointer and increases its contents by one, thereby forming the address code of the next free memory cell in the stack pointer. As a result of this, an interrupt vector will be loaded into the general registers of the universal computer processor 1 _i , which will be used by the processor to go to the interrupt program. The interrupt program ends with the "Restore" command, by which the control unit of the mainframe processor 1 _i generates a recovery signal. This signal is fed to the input of the stack pointer and reduces its contents by one, thereby forming the address code of the last occupied memory cell, which is fed to the address inputs of all storage devices. As a result of this, the state of the interrupted program will be restored in the general registers and the processor will continue its execution.

If, when monitoring the progress of the programs, the universal computers 1 _i operate in the normal mode, then the “mismatch” signals will not be output to the control device and to the input of the control computer 4. If, for some reason, the universal computers 1 _i during the execution of the programs will produce "non-compliance" signals, then the aircraft will work, as described above, in accordance with the issued signal.

Thus, it is possible to control the operation of several computers of the system in the event of various emergency situations due to the redistribution of system resources.

Claims (8)

1. A computing system comprising five electronic computers (computers), three input-output channels, three external subscribers and a control device, the corresponding inputs and outputs of the computer are connected by buses to the corresponding inputs and outputs of the control device, characterized in that in addition, a main shared memory (OP) block and a reserve OP block were introduced, the corresponding inputs and outputs of which are connected by buses to the corresponding inputs and outputs of the control device, the first three computers are used as universal computers, the fourth computer is used as the control, and the fifth computer is the backup, the inputs and outputs of each corresponding subscriber are connected by the bus inputs and outputs of the corresponding input-output channel, the input-outputs of which are connected by the buses with the corresponding inputs and outputs of the control device, and the control device contains two blocks OR elements, an OR element block consisting of N OR elements, where N is equal to the number of bits of the transmitted information, the system control unit when writing and reading the control point a host computer, a system control unit in the event of a malfunction of one of the universal computers, a communication unit of all the system computers with external subscribers, a system control unit in the event of a malfunction of the universal computer memory, a system control unit in the event of a malfunction in the OP and four OR elements, from first to thirty the third inputs of the device are connected respectively from the first to thirty-third inputs of the first block of OR elements, from the thirty-fourth to sixty-eighth inputs of the device are connected respectively to the first to thirty-fifth inputs of the second block of OR elements, the first to fourth outputs of the first block of OR elements are connected respectively from the first to fourth inputs of the system control unit when writing and reading the control point of the mainframes, the fifth input of which is connected to the output of the block of OR elements, the second input the system control unit when writing and reading the control point of the universal computer is connected to the combined first inputs of the system control unit in the event of a malfunction of one of the station wagons computers, the system control unit in the event of a malfunction of the memory of the universal computers and the fourth input of the communication unit of all computers of the system with external subscribers, the fifth to twelfth inputs of the first block of OR elements are connected respectively to the sixth to thirteenth inputs of the system control unit when writing and reading the control point of universal Computers from the thirteenth to fifteenth inputs of the first block of OR elements are connected respectively from the third to fifth system control units in the event of a malfunction of one and mainframes, from the first to fifth inputs of the second block of OR elements, respectively, are connected from the tenth to fourteenth block of the system control unit in the event of a malfunction of one of the mainframes, the second input of which is connected to the third input of the communication block of all the computer systems with external subscribers and the seventh output of the second block of elements OR, the sixth output of which is connected to the second input of the communication unit of all computers of the system with external subscribers, the first input of which is connected to the third input of the system control unit a malfunction of one of the universal computers, the fourth input of which is connected to the sixth input of the communication unit of all computers of the system with external subscribers, the fifth input of which is connected to the eighth output of the second block of OR elements, from the ninth to fourteenth outputs of which are connected respectively to the seventh to twelfth inputs of the communication block all computers of the system with external subscribers, from the thirteenth to fifteenth inputs of which are connected each, respectively, to the fifth to gray combined from the first to third inputs of the block of OR elements my inputs of the system control unit in the event of a malfunction of the universal computer memory, from the fourth to sixth inputs of the system control unit in the event of a malfunction in the OP and with the twenty-first to twenty-third outputs of the second block of OR elements, the fifteenth and sixteenth outputs of which are connected each to the third and fourth the inputs of the system control unit in the event of a malfunction of the mainframe memory, the eighth input of which is connected to the sixth input of the system control unit during recording and with washing the control point of a universal computer, the eighth input of which is connected to the fifteenth input of the system control unit when a malfunction of one of the universal computers occurs, the eighth input of which is connected to the seventh input of the system control unit when writing and reading the control point of universal computers, the eleventh input of which is connected to the seventh input the system control unit in the event of a malfunction of one of the universal computers, the ninth input of which is connected to the thirteenth input of the system control unit when writing and reading the control point of a universal computer, the twelfth input of which is connected to the sixth input of the system control unit when a malfunction of one of the universal computers occurs, the fifth input of which is connected to the second input of the system control unit when a malfunction of the universal computer memory occurs, the ninth input of which is connected to the seventeenth the output of the second block of OR elements, from the eighteenth to the twentieth outputs of which are connected respectively from the first to third inputs of the system control unit at a malfunction in the OP, the seventh and eighth inputs of which are connected respectively to the nineteen fourth and twenty-fifth outputs of the second block of OR elements, from the first to tenth outputs of the system control unit when a malfunction of the mainframe memory is connected respectively to the twenty-ninth to thirty-eighth device outputs, with thirty-ninth to forty-fifth outputs of which are connected respectively with the first to seventh outputs of the system control unit in the event of a malfunction in the OP, with of the eighth outputs of the system control unit when writing and reading the control point of the universal computers are connected respectively to the second to seventh outputs of the device, the first output of which is connected to the output of the first OR element, the second input of which is connected to the eleventh output of the system control unit in the event of a malfunction of one of the universal computers the first output of which is connected to the second input of the second OR element, the first input of which is connected to the second output of the system control unit during recording and reading a control point of a universal computer, the first output of which is connected to the first input of the first OR element, the output of the second OR element is connected to the eighth output of the device, the ninth output of which is connected to the second output of the system control unit in the event of a malfunction of one of the universal computers, from the sixth to tenth outputs which are connected respectively with the eleventh to fifteenth outputs of the device, the tenth output of which is connected to the fourth output of the system control unit in case of failure In particular, one of the universal computers, the third output of which is connected to the first input of the third OR element, the second input of which is connected to the first output of the communication unit of all computers of the system with external subscribers, and the output is connected to the seventeenth output of the device, the sixteenth output of which is connected to the twelfth output of the control unit system in the event of a malfunction of one of the universal computers, the fifth output of which is connected to the first input of the fourth OR element, the second input of which is connected to the eighth output of the communication unit of all computers systems with external subscribers, and the output is connected to the twenty-eighth output of the device, from the eighteenth to twenty-third outputs of which are connected respectively to the second to seventh outputs of the communication unit of all computers of the system with external subscribers, from the ninth to twelfth outputs of which are connected respectively from twenty-fourth to twenty seventh device outputs. 2. The computing system according to claim 1, characterized in that the first block of OR elements contains nine OR elements, the first to third inputs of the block are connected respectively from the first to third inputs of the first OR element, the output of which is connected to the first output of the block, the second output of which connected to the fourth input of the block, from the fifth to seventh inputs of which are connected from the first to third inputs of the second OR element, the output of which is connected to the third output of the block, from the eighth to tenth inputs of which are connected from the first to third inputs of the fifth OR element, the output of which is connected to the fourth output of the block, the eleventh to thirteenth inputs of which are connected to the first to third inputs of the fourth OR element, the output of which is connected to the fifth output of the block, the fourteenth and fifteenth inputs of which are connected respectively with its sixth and seventh outputs, from the sixteenth to eighteenth inputs of which are connected from the first to third inputs of the fifth OR element, the output of which is connected to the eighth output of the unit, from the nineteenth to twenty-first inputs of which They are connected from the first to the third inputs of the sixth OR element, the output of which is connected to the ninth output of the block, the twenty second, twenty third and twenty fourth inputs of which are connected to the tenth, eleventh and twelfth outputs of the block, from the twenty fifth to twenty seventh inputs of which are connected to the first the third inputs of the seventh OR element, the output of which is connected to the thirteenth output of the block, from the twenty-eighth to the thirtieth inputs of which are connected from the first to third inputs of the eighth OR element, the output of which connected to the output of the fourteenth, the thirty-first to thirty third inputs of which are connected to first to third inputs of the ninth OR gate whose output is connected to the output of the fifteenth. 3. The computing system according to claim 1, characterized in that the second block of OR elements contains five OR elements, the first to fifth inputs of the block are connected respectively each from the first to fifth of its outputs, from the sixth to eighth inputs of which are connected to the first to third inputs the first OR element, the output of which is connected to the sixth output of the block, the ninth input of which is connected to the seventh output of the block, the tenth to twelfth inputs of which are connected from the first to third inputs of the second OR element, the output of which is connected to the eighth output ohm of the block, from the thirteenth to fifteenth inputs of which are connected from the first to third inputs of the third OR element, the output of which is connected to the ninth output of the block, from the sixteenth to twentieth inputs of the block are connected each from the tenth to fourteenth outputs, from the twenty first to twenty third inputs, respectively which is connected from the first to third inputs of the fourth OR element, the output of which is connected to the fifteenth output of the block, from the twenty-fourth to twenty-sixth inputs of which are connected from the first to third inputs and a fifth OR gate, whose output is connected to the output of the sixteenth, the twenty-seventh through thirty-fifth inputs of each unit are connected respectively to the seventeenth of the twenty-fifth its outputs. 4. The computing system according to claim 1, characterized in that the system control unit when writing and reading the control point of the universal computer contains a decoder, address generator, trigger, four blocks of AND elements, consisting of N elements AND each, two buffer storage blocks and three block of AND elements, consisting of N elements AND each, the outputs of which are connected respectively to the sixth, seventh and eighth outputs of the block, the first input of which is connected to its first output, the second input of the block is connected to the input of the decoder, the first, second and t the third outputs of which are connected to the first inputs of the first second and third blocks of AND elements, respectively, and respectively to the first, second and third inputs of the address generator, the output of which is connected to the second output of the block, the third output of which is connected to the zero input of the trigger and the fourth input of the block, the third input which is connected to the single input of the trigger, the single output of which is connected to the first input of the first block of AND elements, the second input of which is connected to the fifth input of the block, the sixth input of which is connected to the first m the input of the fourth block of elements And and with the third input of the first block of elements And, the output of which is connected to the input of the first buffer storage unit, the output of which is connected to the first input of the second block of elements And, the output of which is connected to the fourth output of the block, the seventh input of which is connected to the first the input of the third block of AND elements and the second input of the second block of AND elements, the third input of which is connected to the eighth input of the block, the ninth input of which is connected to its fifth output, the tenth input of the block is connected to the second input of of the fourth block of AND elements, the third input of which is connected to the output of the second buffer memory block, the input of which is connected to the output of the third block of AND elements, the second and third inputs of which are connected respectively to the eleventh and twelfth inputs of the block, the thirteenth input of which is connected to the fourth input of the fourth block of elements And, the output of which is connected to the combined second inputs of the first second and third blocks of elements I. 5. The computing system according to claim 1, characterized in that the control unit of the system in the event of a malfunction of one of the mainframes contains a decoder, address generator, trigger, three blocks of AND elements consisting of N elements AND, four blocks of AND elements consisting of N And each element, an OR element block, consisting of N elements, a buffer storage unit and an AND element, the output of which is connected to the fourth output of the block, the first input of which is connected to the input of the decoder, the first, second and third outputs of which are connected to the first the inputs of the first and second and third blocks of AND elements, respectively, and the first, second, and third inputs of the address generator, the output of which is connected to the first output of the block, the second input of which is connected to the combined first inputs of the first and second blocks of AND elements, and the first input of the AND element and the second output of the block, the third input of which is connected to its third output, the second input of the element And and the single input of the trigger, the single output of which is connected to the combined second inputs of the first, second, third of the fourth and fourth blocks of AND elements, and the zero input of the trigger is connected to the fourth input of the block and its fifth and sixth outputs combined, the fifth input of the block is connected to the combined second inputs of the first, second and third blocks of AND elements, the outputs of which are connected to the seventh, eighth and the ninth outputs of the block, the sixth and seventh inputs of which are connected respectively to the third and fourth inputs of the third block of elements And, the fifth input of which is connected to the fourth input of the fourth block of elements And and the eighth input a, the ninth and tenth inputs of which are connected respectively to the fourth and fifth inputs of the second block of elements And, the sixth input of which is connected to the fourth input of the third block of elements And and the eleventh input of the block, the twelfth input of which is connected to its eleventh output, the thirteenth and fourteenth inputs of the block are connected respectively, with the first and third inputs of the third block of AND elements, the output of which is connected to the second input of the block of OR elements, the first input of which is connected to the output of the first block of AND elements, and the output connected to the input of the buffer storage unit, the output of which is connected to the combined third input of the second block of elements AND and the first input of the fourth block of elements AND, the third input of which is connected to the fifteenth input of the block, and the output is connected to the twelfth output of the block, the tenth output of which is connected to the output of the second block of elements I. 6. The computing system according to claim 1, characterized in that the communication unit of all the computers of the system with external subscribers contains two decoders, a trigger, five OR elements, an NOT element, sixteen blocks of AND elements consisting of N elements AND each, and five blocks of elements OR, consisting of N elements AND each, the first and second inputs of the block are connected respectively with its first and second outputs and the first and second inputs of the first OR element, the output of which is connected to a single input of a trigger, a single output of which is connected to the combined second inputs Dams of the second, third, tenth and eleventh blocks of elements And, and the zero output of the trigger is connected to the combined first inputs of the seventh AND, eighth And, ninth And, fourteenth And, fifteenth And and sixteenth And blocks of elements And, the third input of the block is connected to the combined first input second AND, the third input of the tenth AND blocks of elements AND and the input of the element NOT, the output of which is connected to the combined first input of the third AND, the third input of the eleventh AND blocks of elements AND, the fourth input of the block is connected to the input of the first a fractor, the first, second and third outputs of which are connected to the first inputs of the second, third and fourth OR elements, respectively, the second inputs of which are connected to the first, second and third outputs of the second decoder, the input of which is connected to the fifth input of the block, the sixth and seventh inputs which are connected respectively with its eighth and ninth outputs and, respectively, with the first and second inputs of the fifth OR element, the output of which is connected to the zero input of the trigger, the eighth, ninth and tenth inputs of the block are connected the second inputs of the first, second and third blocks of AND elements, respectively, whose outputs are connected to the corresponding inputs of the first block of OR elements, the output of which is connected to the combined third inputs of the second and third blocks of AND elements, the outputs of which are connected respectively to the third and fourth outputs of the block, eleventh and the twelfth inputs of which are connected to the first inputs of the tenth and eleventh blocks of elements And, respectively, whose outputs are connected respectively to the first and second inputs of the second the first block of OR elements, the output of which is connected to the combined second inputs of the fourth, fifth and sixth blocks of AND elements, the outputs of which are connected to the first inputs of the third, fourth and fifth blocks of OR elements, the second inputs of which are connected to the outputs of the seventh, eighth and ninth blocks, respectively elements And, the second inputs of which are connected respectively with the thirteenth, fourteenth and fifteenth inputs of the block, the tenth eleventh and twelfth outputs of which are connected with the outputs, respectively of the fourth, fifth, and fifth blocks of OR elements, the fifth, sixth, and seventh outputs of the block are connected to the outputs of the fourteenth AND, fifteenth AND, and sixteenth AND of the blocks of AND elements, the second inputs of which are connected to the second inputs of the first, second, and third blocks of AND elements, respectively, the first the inputs of which are connected to the outputs of the second, third and fourth elements, respectively. 7. The computing system according to claim 1, characterized in that the system control unit in the event of a malfunction of the mainframe memory contains a decoder, address generator, trigger, three AND elements, eight blocks of AND elements consisting of N elements AND each and an OR block of elements, the output of which is connected to the second input of the fourth block of AND elements, the output of which is connected to the seventh output of the block, the first input of which is connected to the input of the decoder, the first output of which is connected to the combined first inputs of the first AND element, the first o and the sixth block of elements And and the address generator, the second input of which is connected to the combined first inputs of the second element And, the second and seventh blocks of elements And and the second output of the decoder, the third output of which is connected to the combined first inputs of the third element And, the third and eighth blocks of elements And the third input of the address generator, the output of which is connected to the first output of the block, the second, third and fourth outputs of which are connected to the outputs of the first, second and third elements And, second the inputs of which are combined and connected to the second input of the block, the third input of which is connected to its fifth output and the single input of the trigger, the single output of which is connected to the combined first inputs of the fourth and fifth elements And, and the zero input of the trigger is connected to the combined fourth input and sixth output of the block , the fifth, sixth and seventh inputs of which are connected to the second inputs of the first, second and third blocks of AND elements, respectively, the outputs of which are connected respectively to the first, second, and third inputs of the element that OR, the eighth input of the block is connected to the combined third inputs of the fourth and fifth elements And, the ninth input of the block is connected to the second input of the fifth element And, the output of which is connected to the combined second inputs of the sixth, seventh and eighth blocks of elements And, the outputs of which are connected respectively to the eighth , ninth and tenth block outputs. 8. The computing system according to claim 1, characterized in that the system control unit in the event of a malfunction in the OP contains a decoder, a trigger, ten blocks of AND elements consisting of N elements AND each, and two blocks of OR elements consisting of N OR elements, the first input of the block is connected to its first output and a single input of the trigger, the zero input of which is connected to the second input of the block and its second output, the third input of the block is connected to the input of the decoder, the first output of which is connected to the combined first inputs of the first and sixth blocks of elements And, the second output of the decoder is connected to the combined first inputs of the second and seventh blocks of elements And, the third output of the decoder is connected to the combined first inputs of the third and eighth blocks of elements And, the fourth, fifth and sixth inputs of the block are connected to the second inputs of the first, second and of the third block of AND elements, the outputs of which are connected respectively to the first, second and third inputs of the first block of OR elements, the output of which is connected to the combined second inputs of the fourth and fifth about blocks of AND elements, the outputs of which are connected respectively to the third and fourth outputs of the block, the fifth, sixth and seventh outputs of which are connected to the outputs of the sixth, seventh and eighth blocks of AND elements, the second inputs of which are combined and connected to the output of the second block of OR elements, the first and the second inputs of which are connected to the outputs of the ninth and tenth blocks of AND elements, respectively, the second inputs of which are connected respectively to the seventh and eighth inputs of the block, a single trigger output connected to the first first inputs of the fourth and ninth blocks of AND elements, and the zero output of the trigger is connected to the combined first inputs of the fifth and tenth blocks of AND elements.

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