CN115705267A

CN115705267A - Monitoring acquisition equipment, and main/standby switching method and system based on monitoring acquisition equipment

Info

Publication number: CN115705267A
Application number: CN202110920907.XA
Authority: CN
Inventors: 张术; 颜小云; 姚强耀; 王林
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2021-08-11
Filing date: 2021-08-11
Publication date: 2023-02-17

Abstract

The application discloses a monitoring acquisition device, and a main/standby switching method and system based on the monitoring acquisition device, and belongs to the technical field of monitoring. The monitoring and collecting device comprises: the system comprises a first CPU module, a second CPU module, a communication module, a shared hardware module, a main/standby switching module and a signal switching switch array; the first CPU module is connected with the second CPU module through the communication module; the first CPU module and the second CPU module are both connected with the input end of the main-standby switching module, and the output end of the main-standby switching module is connected with the control end of the signal switching switch array; the first CPU module is connected with the shared hardware module through the signal change-over switch array, and the second CPU module is connected with the shared hardware module through the signal change-over switch array. According to the monitoring and collecting device, when the first CPU module has software and hardware faults, the monitoring and collecting device can be quickly switched to the second CPU module to continue working, and the stability of the system is effectively improved.

Description

Monitoring acquisition equipment, and main/standby switching method and system based on monitoring acquisition equipment

Technical Field

The application relates to the field of edge computing equipment, the field of gateway equipment of the Internet of things or the field of monitoring, in particular to monitoring acquisition equipment, and a master-slave switching method and system based on the monitoring acquisition equipment.

Background

With the rapid development of science and technology, monitoring systems are widely applied in various fields. The monitoring and collecting device is used for collecting data of power environment scenes such as independent data centers, machine rooms, telecommunication base stations and the like, intelligent medical scenes or gateway scenes of the internet of things, and reporting the data to the monitoring center so as to monitor the machine room devices and the environment data in real time and maintain the normal operation of each application scene device.

In order to improve the reliability of the monitoring and collecting system, in the related art, a dual-computer hot standby scheme is often adopted, that is, two monitoring and collecting devices are deployed in the monitoring and collecting system, and communicate with each other through a network or other communication interfaces, so as to synchronize the state information of the two monitoring and collecting devices. Only the main collector works in a normal state, and when the main collector breaks down, the standby collector is immediately switched to continue working. The scheme not only can play a role in redundant fault tolerance on power supply faults and network faults, but also can effectively fault tolerance on other software and hardware faults of the collector.

However, two monitoring and collecting devices are deployed in the monitoring and collecting system, which brings expensive cost on one hand, and on the other hand, when the two monitoring and collecting devices are deployed, the two monitoring and collecting devices need to be wired separately, resulting in large workload for construction, wiring and the like.

Disclosure of Invention

The application provides a monitoring acquisition device, and a main/standby switching method and system based on the monitoring acquisition device, which can quickly switch to a second CPU module to continue working when a software fault and a hardware fault occur in a first CPU module. The technical scheme is as follows:

according to an aspect of the present application, there is provided a monitoring acquisition apparatus including: the system comprises a first CPU module, a second CPU module, a communication module, a shared hardware module, a main/standby switching module and a signal switching switch array;

the first CPU module is connected with the second CPU module through the communication module;

the first CPU module and the second CPU module are both connected with the input end of the main/standby switching module, and the output end of the main/standby switching module is connected with the control end of the signal switching switch array;

the first CPU module is connected with the shared hardware module through the signal change-over switch array, and the second CPU module is connected with the shared hardware module through the signal change-over switch array;

the main-standby switching module is used for switching the CPU module connected with the shared hardware module from the first CPU module to the second CPU module. In an alternative design of the present application, a communication module includes: the system comprises a first communication module and a second communication module which are parallel;

the first communication module is used for transmitting at least one of a first heartbeat signal and a first main/standby switching command between the first CPU module and the second CPU module;

the second communication module is used for transmitting at least one of a second heartbeat signal and a second main/standby switching command between the first CPU module and the second CPU module.

In an alternative design of the present application, the first communication module includes an ethernet switch chip;

the second communication module comprises a hardware handshake circuit, and an Interface protocol adopted by the hardware handshake circuit comprises at least one of a Serial port, a General-purpose input/output port (GPIO), a Universal Asynchronous Receiver/Transmitter (UART), a Universal Serial Bus Interface (USB), and a High Definition Multimedia Interface (HDMI).

In an alternative design of the present application, the first CPU module further includes a first watchdog circuit, and the second CPU module further includes a second watchdog circuit.

In an optional design of the present application, the shared hardware module includes at least one of a monitoring data module, a mobile communication module, and a solid state disk SSD.

The monitoring data module includes: at least one of a remote communication protocol interface RS485, a near field data transmission communication protocol interface RS232, a digital signal input interface DI, a digital signal output interface DO, a universal serial bus interface USB and a high definition multimedia interface HDMI.

According to another aspect of the present application, a method for switching between a main device and a standby device of a monitoring and collecting device is provided, where the method includes:

the first CPU module collects monitoring data through a shared hardware module;

the second CPU module sends a first switching signal to the main/standby switching module under the condition that the first CPU module meets the main/standby switching condition;

and the main/standby switching module switches the CPU module connected with the shared hardware module from the first CPU module to the second CPU module according to the first switching signal.

In an optional design of the present application, the second CPU module sends the first switching signal to the active/standby switching module when the first CPU module meets the active/standby switching condition, and further includes:

and the second CPU module sends a first switching signal to the main/standby switching module under the condition that the communication module receives a main/standby switching command sent by the remote server.

According to another aspect of the present application, there is provided a monitoring acquisition system, the system comprising:

the system comprises a data sensor, monitoring acquisition equipment and a monitoring center server, wherein the data sensor is connected with the monitoring acquisition equipment through a shared hardware module, and the monitoring acquisition equipment is connected with the monitoring center server through a communication module.

According to another aspect of the present application, there is provided a computer readable storage medium having stored therein at least one instruction, at least one program, code set or set of instructions, which is loaded and executed by a processor to implement the method of tracking video data as described above.

The beneficial effect that technical scheme that this application provided brought includes at least:

two CPU modules are simultaneously arranged in one monitoring acquisition device: the first CPU module and the second CPU module realize that the monitoring and acquisition equipment can be quickly switched to the second CPU module to continue working when the first CPU module has software and hardware faults, effectively improve the stability of the system and improve the fault-tolerant capability of a single-machine scheme. Meanwhile, compared with a dual-computer hot standby scheme, the two CPU modules share one group of shared hardware module, so that the same wiring construction mode as that of a single-computer scheme can be kept, complicated construction wiring work in the dual-computer hot standby scheme is omitted, and the cost advantage is higher.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a surveillance acquisition system provided in an exemplary embodiment of the present application;

FIG. 2 is a schematic view of a monitoring acquisition device provided in an exemplary embodiment of the present application;

fig. 3 is a schematic diagram of a main-standby switching method of a monitoring acquisition device according to an exemplary embodiment of the present application;

FIG. 4 is a schematic view of a monitoring acquisition device provided in an exemplary embodiment of the present application;

fig. 5 is a schematic diagram of a main-standby switching method of a monitoring acquisition device according to an exemplary embodiment of the present application;

fig. 6 is a schematic diagram of a main-standby switching method of a monitoring acquisition device according to an exemplary embodiment of the present application;

fig. 7 is a schematic diagram of a main/standby switching method of a monitoring acquisition device according to an exemplary embodiment of the present application;

FIG. 8 is a schematic diagram of a latch circuit of a monitoring acquisition device provided in an exemplary embodiment of the present application;

FIG. 9 is a schematic diagram of a first signal switch of a monitoring acquisition device provided in an exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of a second signal switch of a monitoring acquisition device provided in an exemplary embodiment of the present application;

FIG. 11 is a schematic diagram of a third signal switch of a monitoring acquisition device provided in an exemplary embodiment of the present application;

FIG. 12 is a schematic diagram of a fourth signal switch of a monitoring acquisition device provided in an exemplary embodiment of the present application;

fig. 13 is a block diagram of a computer device of a monitoring and acquisition device according to an exemplary embodiment of the present application.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a monitoring and acquisition system according to an embodiment of the present application. The monitoring and collecting system comprises: data sensors 110, monitoring acquisition equipment 120 and monitoring center server 130.

The data sensor 110 is used to collect information in a power environment scenario, an intelligent medical scenario, or an internet of things gateway scenario, taking a power environment application scenario as an example.

The power environment refers to a machine room environment applied to a data center, a machine room, a telecommunication base station and the like. The data sensor 110 may be at least one sensor selected from a battery monitor, a temperature sensor, a humidity sensor, a door sensor, an audible and visual alarm, a camera, and a touch display screen, but is not limited thereto. The data sensor 110 may be one or more sensors, and the number of the data sensors 110 may be more or less, which is not limited by the embodiment. For example, the number of the data sensors 110 may be only one, or the number of the data sensors 110 may be several tens or hundreds, or more. Optionally, the data sensor 110 and the monitoring and acquiring device 120 are directly or indirectly connected through a wired or wireless communication manner, which is not limited in this embodiment, the data sensor 110 and the monitoring and acquiring device 120 are connected through a shared hardware module 207. The shared hardware modules 207 correspond to the data sensors 110 one to one.

The monitoring and collecting device 120 is configured to collect monitoring data collected by the data sensor 110 and report the monitoring data to the monitoring center server 130. The monitoring and collecting device 120 includes a first CPU module 201, a second CPU module 202, a first communication module 203, a second communication module 204, a main/standby switching module 205, a signal switching switch array 206, and a shared hardware module 207.

The first CPU module 201 of the monitoring acquisition device refers to a control unit that undertakes a main work task in a normal working state of the monitoring acquisition device 120. The second CPU module 202 is a control unit that does not assume a main task when the first CPU module 201 is normal, or the second CPU module 202 is a control unit that assumes a main task when the first CPU module 201 is abnormal, or the second CPU module 202 is a control unit that assumes a part of a task when the first CPU module 201 is normal. Each CPU module includes at least a processor and a memory, and optionally, auxiliary circuits such as a power supply circuit and a watchdog circuit. The two CPU modules may be identical or may differ.

The first CPU module 201 is connected to the second CPU module 202 through the first communication module 203, and the first CPU module 201 is connected to the second CPU module 202 through the second communication module 204. The first CPU module 201 can transmit information to the second CPU module 202 through the first communication module 203 or the second communication module 204. Optionally, the information transmitted by the first communication module 203 or the second communication module 204 includes at least one of a heartbeat signal and a master/slave switching command, and the type of the information is not limited thereto, which is not limited in this application.

The active/standby switching module 205 is configured to receive a first switching signal sent by the second CPU module 202, and send a second switching signal to the signal switch array 206 when the received first switching signal meets a time sequence condition. The signal switch array 206 includes a plurality of sets of signal switches, each set of signal switches corresponds to one shared hardware module 207, or each shared hardware module 207 corresponds to a respective signal switch, and the signal switches of different shared hardware modules 207 are independent from each other and are configured to receive a second switching signal sent by the active/standby switching module 205.

The first CPU module 201 and the second CPU module 202 are both connected to the input end of the main/standby switching module 205, the output end of the main/standby switching module 205 is connected to the control end of the signal switch array 206, and meanwhile, the first CPU module 201 and the second CPU module 202 are both connected to the shared hardware module 207 through the signal switch array 206. When the first CPU module 201 meets the main/standby switching condition, the second CPU module 202 sends a first switching signal to the main/standby switching module 205. After the main/standby switching module 205 receives the first switching signal, the main/standby switching module 205 sends a second switching signal to the signal switch array 206, so as to control the signal switch array 206 to switch the CPU module connected to the shared hardware module 207 from the first CPU module 201 to the second CPU module 202, thereby avoiding interruption of service work.

Optionally, the active/standby switching condition includes at least one of the following three conditions:

firstly, the second CPU module 202 receives the heartbeat signal periodically sent by the first CPU module 201 through the first communication module 203 and the second communication module 204, and the second CPU module 202 sends a first switching signal to the main/standby switching module 205 when not receiving the heartbeat signal within a predetermined time period;

second, the first CPU module 201 sends a main/standby switching command to the second CPU module 202 through the first communication module 203 and the second communication module 204, and the second CPU module 202 sends a first switching signal to the main/standby switching module 205 when receiving two main/standby switching commands at the same time;

third, when the second CPU module 202 receives the active/standby switching command sent by the remote server, the second CPU module 202 sends a first switching signal to the active/standby switching module 205.

The main/standby switching conditions are not limited in the present application.

The monitoring and collecting device 120 and the monitoring center server 130 may be directly or indirectly connected through wired or wireless communication, which is not limited in the embodiment of the present application.

The monitoring center server 130 is used for receiving and storing the monitoring data acquired by the monitoring acquisition equipment 120, so as to realize monitoring of the power environment. The monitoring center server 130 includes at least one of a server, a plurality of servers, a cloud computing platform, and a virtualization center. The monitoring center server 130 is a server corresponding to the monitoring acquisition device 120 and is configured to provide a service for the monitoring acquisition device 120.

One skilled in the art will appreciate that the number of monitoring center servers 130 described above may be greater or fewer. For example, the number of the monitoring center servers 130 may be only one, or the number of the monitoring center servers 130 may be several tens or hundreds, or more. The number and the device type of the monitoring center server 130 are not limited in the embodiment of the present application.

In an illustrative example, the temperature sensor in the data sensor 110 acquires the current temperature of the power environment, and directly or indirectly transmits the current temperature to the monitoring and acquisition device 120 through wired or wireless communication, and when the first CPU module 201 in the monitoring and acquisition device 120 operates normally, the temperature information is uploaded to the monitoring center server 130 through the first CPU module 201; under the condition that the first CPU module 201 of the monitoring and collecting device 120 has software and hardware failures or receives a main/standby switching command sent by a remote server, the temperature information is uploaded to the monitoring center server 130 through the second CPU module 202, so that the real-time monitoring of the power environment is realized. Under the condition that the first CPU module 201 meets the main/standby switching condition, the first CPU module 201 can be quickly switched to the scheme that the second CPU module 202 continues to work, which not only greatly improves the reliability of the monitoring and collecting device 120, does not cause service interruption, but also effectively improves the stability of the whole system.

According to the method and the device, the monitoring and acquisition equipment can be switched from the first CPU module 201 to the second CPU module 202 quickly under the condition that the first CPU module 201 has software and hardware faults or meets the main-standby switching condition, and the continuity of business work is guaranteed.

Fig. 2 shows a schematic diagram of a monitoring and acquisition device provided in an exemplary embodiment of the present application. The monitoring acquisition equipment comprises a first CPU module 201, a second CPU module 202, a main/standby switching module 205, a signal switching switch array 206, a shared hardware module 207 and a communication module 210.

The first CPU module 201 is connected to the second CPU module 202 through the communication module 210, and the first CPU module 201 and the second CPU module 202 are further connected to a remote server through the communication module 210.

The first CPU module 201 refers to a control unit that takes a main work task in a normal working state of the monitoring acquisition device 120. The second CPU module 202 is a control unit that does not undertake the main job task when the first CPU module 201 is normal, or the second CPU module 202 is a control unit that undertakes the main job task when the first CPU module 201 is abnormal, or the second CPU module 202 is a control unit that undertakes a part of the job task when the first CPU module 201 is normal. Each CPU module includes at least a processor and a memory, and optionally further includes auxiliary circuits such as a power supply circuit and a watchdog circuit. The two CPU modules may be identical or may differ.

The communication module 210 can realize information transmission between the first CPU module 201 and the second CPU module 202. The transmitted information includes at least one of a heartbeat signal or a master/slave switching command, and the type of the information is not limited thereto, which is not limited in this application.

The first CPU module 201 and the second CPU module 202 are both connected to the input end of the main/standby switching module 205, and the output end of the main/standby switching module 205 is connected to the control end of the signal switch array 206;

the active/standby switching module 205 is configured to receive a first switching signal sent by the second CPU module 202, and send a second switching signal to the signal switch array 206. The output end of the active/standby switching module 205 and the control end of the signal switching switch array 206 may be directly or indirectly connected through a wired or wireless communication manner, which is not limited in this embodiment of the present application. The signal switch array 206 includes a plurality of sets of signal switches, each set of signal switches corresponds to one shared hardware module 207, or each shared hardware module 207 corresponds to a respective signal switch, and the signal switches of different shared hardware modules 207 are independent from each other and are configured to receive a second switching signal sent by the active/standby switching module 205.

The control of the active/standby switching module 205 on the signal switching switch array 206 may be directly or indirectly controlled by direct connection, or by chip implementation or by latch circuit implementation, which is not limited in this embodiment of the application.

The active/standby switching module 205 controls the signal switch array 206 by direct connection, in this implementation, the signal switch array 206 can be directly controlled by simple high/low level signals, but this implementation is too simple and is prone to misoperation.

The active/standby switching module 205 controls the signal switching switch Array 206 by using a chip, and optionally, the chip includes at least one of a single chip microcomputer or a Programmable hardware chip (FPGA), which is not limited in this embodiment of the present application. In the implementation mode, the second CPU module 202 sends the first switching signal to the single chip microcomputer or the FPGA chip, and the single chip microcomputer and the FPGA chip output the second switching signal to the signal switch array 206.

In this embodiment, a latch circuit is used to implement control, the second CPU module 202 outputs a first switching signal in accordance with a certain timing sequence, and outputs a second switching signal to the signal switch array 206 when the first switching signal meets the timing sequence requirement. The first CPU module 201 is connected to the shared hardware module 207 through the signal switch array 206, and the second CPU module 202 is connected to the shared hardware module 207 through the signal switch array 206;

the shared hardware module 207 is a hardware interface for connecting external data, and the shared hardware module includes at least one of an RS485 interface, an RS232 interface, a DI interface, a DO interface, a USB interface, an HDMI interface, a mobile communication module, and an SSD hard disk, which is not limited in this embodiment.

The signal switch array 206 and the shared hardware module 207 may be directly or indirectly connected by a wired or wireless manner, which is not limited in the embodiment of the present application. After receiving the second switching signal output by the active/standby switching module 205, the signal switch array 206 switches the switch array, and switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module.

In summary, in the monitoring and collecting device provided in this embodiment, the first CPU module 201 is connected to the second CPU module 202 through the communication module 210; the first CPU module 201 and the second CPU module 202 are both connected to the input end of the main/standby switching module 205, and the output end of the main/standby switching module 205 is connected to the control end of the signal switch array 206; the first CPU module 201 is connected to the shared hardware module 207 through the signal switch array 206, and the second CPU module 202 is connected to the shared hardware module 207 through the signal switch array 206. Collected monitoring data can be transmitted to the first CPU module 201 through the shared hardware module 207, and when the master-slave switching is required, the master-slave switching module 205 outputs a first switching signal to control the signal switch array 206 to implement the signal switch switching, so that the collected monitoring data can be transmitted to the second CPU module 202 through the shared hardware module 207, thereby ensuring that the service operation is not interrupted.

Fig. 3 is a schematic diagram illustrating a main/standby switching method of a monitoring acquisition device according to an exemplary embodiment of the present application. The method may be applied to the monitoring and acquisition device 120, and in the embodiment of the present application, the monitoring and acquisition method is described with the monitoring and acquisition device 120 as an execution subject. The embodiment specifically comprises the following steps:

step 302: the first CPU module 201 collects monitoring data through the shared hardware module 207;

the first CPU module 201 is a control unit that undertakes a main work task in a normal working state of the monitoring acquisition device. The shared hardware module 207 is used for connecting an external data sensor, where the data sensor includes at least one of a thermometer, a hygrometer, a battery monitor, a door sensor, a camera, and a touch display screen, and this is not limited in this embodiment of the present application. The shared hardware module 207 includes at least one of an RS485 interface, an RS232 interface, a DI acquisition interface, a DO control interface, a USB interface, an HDMI interface, a mobile communication module, and an SSD hard disk, which is not limited in this embodiment of the present application. The monitoring data may be one or more of temperature information, humidity information, door sensor information, audible and visual alarm information, and camera picture information, which is not limited in the embodiments of the present application.

Illustratively, the temperature sensor in the external data sensor shows that this time is 32 degrees celsius, and the temperature sensor transmits this temperature information to the first CPU module 201 via the serial port in the shared hardware module 207.

Step 304: the second CPU module 202 sends a first switching signal to the main/standby switching module 205 when the first CPU module 201 meets the main/standby switching condition;

the main/standby switching condition includes at least one of the following switching conditions: firstly, the second CPU module 202 does not receive the heartbeat signal within the first duration; secondly, the first CPU module 201 sends a main/standby switching command to the second CPU module 202; third, the remote server sends one or more of the active/standby switching commands to the second CPU module 202, which is not limited in this embodiment of the present application.

The first CPU module 201 and the second CPU module 202 are both connected to an input end of the active/standby switching module 205, and the active/standby switching module 205 is configured to receive a first switching signal sent by the second CPU module 202.

Step 306: the main/standby switching module 205 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module according to the first switching signal.

The first CPU module 201 and the second CPU module 202 are connected to the shared hardware module 207 through the signal switch array 206, and according to the on-off state of the signal switch, one of the first CPU module 201 and the second CPU module 202 is conducted with the shared hardware module 207, which is not limited in the embodiment of the present application. Under the condition that the first CPU module 201 operates, the first CPU module 201 is conducted with the shared hardware module 207; the second CPU module 202 is not conductive with the shared hardware module 207. Under the condition that the main/standby switching module 205 receives the first switching signal sent by the second CPU module 202 and meets the main/standby switching condition, the main/standby switching module 205 controls the signal switch array 206 corresponding to the shared hardware module 207 to change the state of the signal switch, and after the state of the signal switch changes, the first CPU module 201 is not connected to the shared hardware module 207; the second CPU module 202 is in communication with the shared hardware module 207.

Illustratively, the temperature sensor in the external data sensor shows that this time is 32 degrees celsius, and the temperature sensor transmits this temperature information to the first CPU module 201 via the serial port in the shared hardware module 207. After the first CPU module 201 fails, the second CPU module 202 sends a first switching signal to the main/standby switching module 205, and the main/standby switching module 205 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module when determining that the first switching signal satisfies the main/standby switching condition, so that, after the first CPU module 201 fails, the temperature information detected by the temperature sensor is directly transmitted to the second CPU module 202 through the serial port in the shared hardware module 207.

In summary, in the active/standby switching method of the monitoring acquisition device provided in this embodiment, the first CPU module acquires the monitoring data through the shared hardware module, and the second CPU module sends the first switching signal to the active/standby switching module when the first CPU module meets the active/standby switching condition; and the main/standby switching module switches the CPU module connected with the shared hardware module from the first CPU module to the second CPU module according to the first switching signal. Under the condition that the first CPU module meets the main/standby switching condition, the CPU module connected with the shared hardware module can be switched from the first CPU module to the second CPU module, so that the main/standby switching method of the monitoring acquisition equipment is provided, and the uninterrupted service work can be ensured.

Fig. 4 shows a schematic diagram of a monitoring and acquisition device provided in another exemplary embodiment of the present application, where the monitoring and acquisition device includes: the system comprises a first CPU module 201, a second CPU module 202, a main/standby switching module 205, a signal switching switch array 206, a shared hardware module 207, an Ethernet switching chip 208, a hardware handshake circuit 209, an Ethernet interface circuit 211 and a power supply module 212.

The first CPU module 201 includes: the memory device comprises a first CPU, a first memory, a first integrated circuit PMIC, a first watchdog circuit and a first power supply circuit, wherein the first memory includes one or more of a first memory DDR and a first Flash memory Flash, but is not limited thereto. The first integrated circuit PMIC is configured to manage power devices within the first CPU module 201; the first watchdog circuit is used for regularly checking the internal condition of the first CPU module 201, and sending a restart signal to the first CPU module 201 once an error occurs; the first power supply circuit is used to supply power to the first CPU module 201.

The second CPU module 202 includes: the second CPU, the second memory, the second PMIC, the second watchdog circuit, and the second power supply circuit, where the second memory includes one or more of a second DDR and a second Flash, but is not limited thereto, and this is not limited by the embodiment of the present application. The second integrated circuit PMIC is configured to manage power devices within the second CPU module 202; the second watchdog circuit is used for regularly checking the internal condition of the second CPU module 202, and sending a restart signal to the second CPU module 202 once an error occurs; the second power circuit is used to provide power to the second CPU module 202.

The first CPU module 201 and the second CPU module 202 have independent configurations, so the first CPU module 201 and the second CPU module 202 can operate completely independently.

The first CPU module 201 is connected to the second CPU module 202 through the communication module 210, and the communication module 210 can implement information transmission between the first CPU module 201 and the second CPU module 202. The transmitted information includes at least one of a heartbeat signal or a master/slave switching command, and the type of the information is not limited thereto, which is not limited in this application.

The communication module 210 includes a first communication module and a second communication module arranged in parallel. The first communication module is configured to transmit at least one of a first heartbeat signal and a first active/standby switching command between the first CPU module and the second CPU module, which is not limited in this application. The second communication module is configured to transmit at least one of a second heartbeat signal and a second active/standby switching command between the first CPU module and the second CPU module, which is not limited in this application.

Illustratively, the first communication module includes an ethernet switch chip 208, the first CPU module 201 is connected to the second CPU module 202 through the ethernet switch chip 208, and the first CPU module 201, the second CPU module 202 are connected to the ethernet switch chip 208 through a media independent interface MII. Optionally, the Media Independent Interface (RMII) includes at least one of a Reduced Media Independent Interface (RMII), a Gigabit Media Independent Interface (GMII), and a Gigabit Media Independent Interface (GMII), which is not limited in this embodiment. The ethernet switching chip 208 further includes an ethernet interface circuit 211 and an expansion interface PHY, and the ethernet switching chip 208 leads out the PHY interface to the outside of the monitoring and collecting device through the ethernet interface circuit 211 to be used as a universal network port.

Illustratively, the second communication module includes a hardware handshake circuit 209, the first CPU module 201 is connected to the second CPU module 202 through the hardware handshake circuit 209, and an interface protocol adopted by the hardware handshake circuit includes at least one of a serial port, a GPIO, a UART, a USB, and an HDMI, but is not limited thereto, and this is not limited in this embodiment of the present application. The first CPU module 201 can perform information transmission to the second CPU module 202 through the hardware handshake circuit. The transmitted information includes at least one of a heartbeat signal or a master/slave switching command, and the type of the information is not limited thereto, which is not limited in this application.

the active/standby switching module 205 is configured to receive a first switching signal sent by the second CPU module 202, and send a second switching signal to the signal switch array 206.

The active/standby switching module 205 includes a latch circuit, and the latch circuit is configured to send a second switching signal to the signal switch array 206 when the first switching signal sent by the second CPU module 202 satisfies the timing condition.

The input end of the latch circuit may be connected to the first CPU module 201 and the second CPU module 202 through one or more of a signal line, UART, GPIO, USB, HDMI, and PCLE, which is not limited in this embodiment of the present invention.

The output terminal of the latch circuit and the control terminal of the signal switch array 206 may be directly or indirectly connected through wired or wireless communication, which is not limited in the embodiment of the present application. The signal switches in the signal switch array 206 include one or more analog signal switches and differential signal switches, which are not limited in this embodiment of the present application. For example, in a case where the shared hardware module 207 receives UART and GPIO signals, the signal switch corresponding to the shared hardware module 207 may be an analog signal switch due to a low signal speed; when the shared hardware module 207 receives the USB signal, the PCIE signal, and the HDMI signal, since the signal is a high-speed differential signal and is sensitive, the signal switch corresponding to the shared hardware module 207 may be a differential signal switch.

The first CPU module 201 is connected to the shared hardware module 207 through the signal switch array 206, and the second CPU module 202 is connected to the shared hardware module 207 through the signal switch array 206;

after receiving the second switching signal output by the active/standby switching module 205, the signal switch array 206 switches the switch array, and switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module.

The shared hardware module 207 is configured to connect to an external data sensor, and the shared hardware module includes at least one of an RS485 interface, an RS232 interface, a DI acquisition interface, a DO control interface, a USB interface, an HDMI interface, an SSD hard disk, and a mobile communication module, which is not limited in this embodiment of the present application. The control terminal of the signal switch array 206 and the shared hardware module 207 may be directly or indirectly connected through a wired or wireless communication manner, which is not limited in the embodiment of the present application. The signal switch array 206 includes a plurality of sets of signal switches, each set corresponds to one shared hardware module 207, or each shared hardware module 207 corresponds to a respective switch, and different shared hardware modules 207 are independent of each other, which is not limited in this application.

The shared hardware module 207 includes one or more shared hardware modules 207, which in this embodiment is illustrated as including at least a first shared hardware module and a second shared hardware module, but the number of the shared hardware modules 207 is not limited, and the first shared hardware module corresponds to the first switch array in the signal switch array 206; the second shared hardware module corresponds to a second switch array in the signal switch array 206.

The monitoring acquisition device further comprises a power supply module 212, wherein the power supply module 212 comprises a first power supply circuit and a second power supply circuit which are arranged in parallel. The first power supply circuit comprises a power interface 1 and a power module 1; the second power supply circuit comprises a power interface 2 and a power module 2. The output end of the power supply module 212 is connected to the power supply ends of the first CPU module 201 and the second CPU module 202, respectively.

In summary, in the monitoring and collecting device provided in this embodiment, the first CPU module 201 is connected to the second CPU module 202 through the ethernet switching chip 208 and the hardware handshake circuit 209; the first CPU module 201 may send a heartbeat signal or a main/standby switching command through the ethernet switch chip 208 and the hardware handshake circuit 209, both the first CPU module 201 and the second CPU module 202 are connected to an input end of the main/standby switching module 205, and an output end of the main/standby switching module 205 is connected to a control end of the signal switch array 206.

Based on the received heartbeat signal or the main/standby switching command, the main/standby switching module 205 outputs a first switching signal to control the signal switch array 206 to switch the signal switch when the main/standby switching condition is satisfied, so that the collected monitoring data can be transmitted to the second CPU module 202 through the shared hardware module 207, thereby ensuring that the service operation is not interrupted.

Fig. 5 is a schematic diagram illustrating a main/standby switching method of a monitoring acquisition device according to another exemplary embodiment of the present application. The method may be applied to the monitoring and collecting device 120, and in the embodiment of the present application, the monitoring and collecting method is described with the monitoring and collecting device 120 as an execution subject. The embodiment specifically comprises the following steps:

the monitoring data may be one or more of temperature information, humidity information, door sensor information, audible and visual alarm information, and camera picture information, which is not limited in the embodiments of the present application.

The first CPU module 201 periodically sends a first heartbeat signal to the second CPU module 202; the first CPU module 201 periodically sends a second heartbeat signal to the second CPU module 202.

Step 304a: the second CPU module 202 receives a first heartbeat signal periodically sent by the first CPU module 201 through the first communication module;

illustratively, the first communication module takes the ethernet switch chip 208 as an example, the first CPU module 201 periodically sends the first heartbeat signal in the form of an ethernet packet through the ethernet switch chip 208, for example, the first CPU module 201 is connected to a first interface on the ethernet switch chip 208, the second CPU module 202 is connected to a second interface on the ethernet switch chip 208, the first interface is communicated with the second interface, and the first heartbeat signal sent by the first CPU module 201 reaches the second CPU module after passing through the first interface, the ethernet switch chip 208, and the second interface in sequence.

Step 304b: the second CPU module 202 receives a second heartbeat signal periodically sent by the first CPU module 201 through the second communication module;

illustratively, the second communication module takes the hardware handshake circuit 209 as an example, the first CPU module 201 sends the first heartbeat signal in a hardware handshake signal manner through the hardware handshake circuit 209, and an interface protocol adopted by the hardware handshake circuit includes at least one of a serial port, a GPIO, a UART, a USB, and an HDMI, but is not limited thereto, and this is not limited in this embodiment of the present application.

Step 304c: the second CPU module 202 does not receive the first heartbeat signal and the second heartbeat signal within the first duration;

the first CPU module 201 sends a first heartbeat signal and a second heartbeat signal to the second CPU module 202 through the ethernet switch chip 208 and the hardware handshake circuit 209, respectively, and if the second CPU module 202 does not receive the first heartbeat signal and the second heartbeat signal within the first duration, the second CPU module 202 sends the first switching signal to the active/standby switching module 205. If the second CPU module 202 receives the first heartbeat signal or the second heartbeat signal within the first time duration, or receives the first heartbeat signal and the second heartbeat signal simultaneously, the heartbeat signal within the time duration is ignored, where the first time duration is longer than a period in which the first CPU module 201 sends the first heartbeat signal and the second heartbeat signal to the second CPU module 202 through the ethernet switch chip 208 and the hardware handshake circuit 209, respectively, optionally, the first time duration may be 2 periods or 3 periods, and the like, which is not limited in this embodiment.

Exemplarily, the first CPU module 201 sends a first heartbeat signal to the second CPU module 202 every 8 seconds through the ethernet switch chip 208, the first CPU module 201 sends a second heartbeat signal to the second CPU module 202 every 8 seconds through the hardware handshake circuit 209, the first duration is set to 10 seconds, the 10 seconds are set as the first duration, the second CPU module 202 receives only the first heartbeat signal or the second heartbeat signal or receives the first heartbeat signal simultaneously within the first duration, that is, within 10 seconds, and under the condition of the second heartbeat signal, the heartbeat signal within the duration is ignored within the first duration, that is, within 10 seconds, thereby reducing the risk of false switching; when the second CPU module 202 does not receive the first heartbeat signal and the second heartbeat signal within the first time period, that is, within 10 seconds, the second CPU module 202 sends the first switching signal to the active/standby switching module 205.

304h: transmitting a first switching signal;

if the second CPU module 202 does not receive the first heartbeat signal and the second heartbeat signal within the first time period, the second CPU module 202 sends the first switching signal to the active/standby switching module 205.

Step 306: when the first switching signal satisfies the timing condition, the active/standby switching module 205 sends a second switching signal to the signal switching switch array 206, and switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module.

The first CPU module 201 and the second CPU module 202 are both connected to the shared hardware module 207 through the signal switch array 206, and the connection manner may be directly or indirectly connected through a wired or wireless communication manner, which is not limited in this embodiment of the present application.

The active/standby switching module 205 includes a latch circuit, and the latch circuit is configured to send a second switching signal to the signal switch array 206 when the first switching signal sent by the second CPU module 202 satisfies the timing condition. When the latch circuit receives that the first switching signal sent by the second CPU module 202 satisfies the timing condition, the latch circuit sends a second switching signal to the signal switch array 206, and the signal switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module.

In summary, in the active-standby switching method of the monitoring acquisition device provided in this embodiment, the first CPU module 201 acquires the monitoring data through the shared hardware module, the second CPU module 202 receives the first heartbeat signal periodically sent by the first CPU module 201 through the first communication module, the second CPU module 202 receives the second heartbeat signal periodically sent by the first CPU module 201 through the second communication module, and the second CPU module 202 ignores the first heartbeat signal and the second heartbeat signal if it does not receive the first heartbeat signal and the second heartbeat signal within the first duration, so as to reduce the risk of false switching; under the condition that the second CPU module 202 receives the first heartbeat signal and the second heartbeat signal within the first time period, the second CPU module 202 sends a first switching signal to the latch circuit; when the latch circuit receives that the first switching signal sent by the second CPU module 202 satisfies the timing condition, the latch circuit sends a second switching signal to the signal switch array 206, and the signal switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module. Whether the first CPU module 201 meets the switching condition or not is judged by judging whether the first heartbeat signal and the second heartbeat signal can be received in the first time period, and therefore the method for switching the main and standby monitoring acquisition equipment is provided, and the uninterrupted service work can be guaranteed.

Fig. 6 is a schematic diagram illustrating a main/standby switching method of a monitoring acquisition device according to another exemplary embodiment of the present application. The method may be applied to the monitoring and collecting device 120, and in the embodiment of the present application, the monitoring and collecting method is described with the monitoring and collecting device 120 as an execution subject. The embodiment specifically comprises the following steps:

The first CPU module 201 sends a first main/standby switching command to the second CPU module 202; the first CPU module 201 sends a second primary/standby switching command to the second CPU module 202.

Step 304d: the first CPU module 201 sends a first primary/standby switching command to the second CPU module 202 through the first communication module;

illustratively, the first communication module ethernet switch chip 208 is taken as an example, the first CPU module 201 sends a first primary/secondary switching command in the form of an ethernet packet through the ethernet switch chip 208, for example, the first CPU module 201 is connected to a first interface on the ethernet switch chip 208, the second CPU module 202 is connected to a second interface on the ethernet switch chip 208, the first interface is communicated with the second interface, and the first primary/secondary switching command sent by the first CPU module 201 reaches the second CPU module after passing through the first interface, the ethernet switch chip 208, and the second interface successively.

Step 304e: the first CPU module 201 receives a second main/standby switching command sent by the second CPU module through the second communication module;

Step 304f: the second CPU module 202 receives the first main/standby switching command and the second main/standby switching command at the same time within the second duration;

first CPU module 201 sends first primary/secondary switching command and second primary/secondary switching command to second CPU module 202 through ethernet switch chip 208 and hardware handshake circuit 209, respectively, and if second CPU module 202 receives first primary/secondary switching command and second primary/secondary switching command simultaneously within a second duration, second CPU module 202 sends first switching signal to primary/secondary switching module 205. If the second CPU module 202 does not receive the first primary/secondary switching command and the second primary/secondary switching command at the same time within the second time period, the first primary/secondary switching command and the second primary/secondary switching command are ignored, where the second time period is that the second CPU module 202 receives the second primary/secondary switching command within the second time period after receiving the first primary/secondary switching command, and then the second CPU module 202 sends the first switching signal to the primary/secondary switching module 205. Optionally, the second duration may be a default value, or may be set according to a customer requirement, which is not limited in this embodiment.

Illustratively, the first CPU module 201 sends a first primary/secondary switching command to the second CPU module 202 through the ethernet switch chip 208, and the first CPU module 201 sends a second primary/secondary switching command to the second CPU module 202 through the hardware handshake circuit 209, and the second duration is set to 10 seconds. Under the condition that the second CPU module 202 does not receive the second main/standby switching command within 10 seconds after the second CPU module 202 receives the first main/standby switching command, ignoring the first main/standby switching command and the second main/standby switching command within the second duration, thereby reducing the risk of false switching; when receiving the first primary/secondary switching command and the second primary/secondary switching command at the same time, the second CPU module 202 sends a first switching signal to the primary/secondary switching module 205.

304h: transmitting a first switching signal;

if the second CPU module 202 does not receive the first heartbeat signal and the second heartbeat signal within the first duration, the second CPU module 202 sends the first switching signal to the active/standby switching module 205.

Illustratively, after the first CPU module 201 fails, the second CPU module 202 sends a first switching signal to the latch circuit, the latch circuit sends a second switching signal to the signal switching switch array 206 when judging that the received first switching signal meets the timing condition, and the signal switching switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module after receiving the second switching signal.

In summary, in the active-standby switching method of the monitoring acquisition device provided in this embodiment, the first CPU module 201 acquires the monitoring data through the shared hardware module, the second CPU module 202 receives the first active-standby switching command sent by the first CPU module 201 through the first communication module, the second CPU module 202 receives the second active-standby switching command sent by the first CPU module 201 through the second communication module, and the second CPU module 202 ignores the first active-standby switching command and the second active-standby switching command in the second duration when not receiving the first active-standby switching command and the second active-standby switching command simultaneously in the second duration, so as to reduce the risk of false switching; under the condition that the second CPU module 202 receives the first main/standby switching command and the second main/standby switching command at the same time, the second CPU module 202 sends a first switching signal to the latch circuit; when the latch circuit receives that the first switching signal sent by the second CPU module 202 satisfies the timing condition, the latch circuit sends a second switching signal to the signal switch array 206, and the signal switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module. Whether the first CPU module 201 meets the switching condition is judged by judging whether the first main/standby switching command and the second main/standby switching command can be received at the same time in the second time length, so that the main/standby switching method of the monitoring acquisition equipment is provided, and the uninterrupted service work can be ensured.

Fig. 7 is a schematic diagram illustrating a main/standby switching method of a monitoring acquisition device according to another exemplary embodiment of the present application. The method may be applied to the monitoring and acquisition device 120, and in the embodiment of the present application, the monitoring and acquisition method is described with the monitoring and acquisition device 120 as an execution subject. The embodiment specifically comprises the following steps:

Step 304g: the second CPU module 202 receives the active/standby switching command sent by the remote server through the communication module 210;

the communication module 210 includes a first communication module and a second communication module arranged in parallel. The first communication module comprises an ethernet switch chip 208, the first CPU module 201 is connected to the second CPU module 202 through the ethernet switch chip 208, and the first CPU module 201, the second CPU module 202 and the ethernet switch chip 208 are connected through a media independent interface MII. Optionally, the media independent interface MII includes at least one of a hundred megabyte media independent interface RMII, a gigabit media independent interface GMII, and a ten gigabit media independent interface XGMII, which is not limited in this embodiment of the present application. The ethernet switching chip 208 further includes an ethernet interface circuit 211 and at least one expansion interface PHY, the ethernet switching chip 208 uses the ethernet interface circuit 211 to lead out the PHY interface to the outside of the monitoring and collecting device as a universal network port, the PHY interfaces may be interconnected, in this embodiment, taking a first PHY interface and a second PHY interface as an example, the monitoring data collected by the shared hardware module 207 is transmitted to the external monitoring center server 130 through the first PHY interface, and in case that a communication link between the first PHY interface and the external monitoring center server 130 fails, the ethernet switching chip 208 may switch the first PHY interface to the second PHY interface in time, that is, the monitoring data collected by the shared hardware module 207 is transmitted to the external monitoring center server 130 through the second PHY interface.

Illustratively, the first CPU module 201 and the second CPU module 202 are respectively connected to an ethernet switch chip 208, the ethernet switch chip 208 is connected to the external monitoring center server 130 through a first PHY interface, and the remote server transmits the active/standby switching command to the second CPU module 202 through the ethernet switch chip 208. The second CPU module 202 sends a first switching signal to the main/standby switching module 205 after receiving the main/standby switching command. In the case of purposefully switching the first CPU module 201 and the second CPU module 202, the purposefully switching includes at least one of maintenance, replacement, and updating of the first CPU module 201, which is not limited in this embodiment. Taking the first CPU module 201 as an example for maintenance, when the first CPU module 201 is maintained, the active-standby switching needs to be actively performed on the first CPU module 201 and the second CPU module 202, and the active-standby switching can be completed by sending an active-standby switching command to the second CPU module 202 through the remote server.

304h: transmitting a first switching signal;

The active/standby switching module 205 includes a latch circuit, and the latch circuit is configured to send a second switching signal to the signal switch array 206 when the first switching signal sent by the second CPU module 202 satisfies the timing condition. When the latch circuit receives that the first switching signal sent by the second CPU module 202 satisfies the timing condition, the latch circuit sends a second switching signal to the signal switch array 206, and the signal switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module. For example, before the primary/standby switching of the first CPU module 201 and the second CPU module 202 does not occur, the monitoring data collected by the shared hardware module 207 transmits the monitoring data to the monitoring center server 130 through the first CPU module 201 and the first PHY interface of the ethernet switch chip 208; the remote server transmits the main/standby switching command to the second CPU module 202 through the PHY interface of the ethernet switch chip 208, the second CPU module 202 transmits the first switching signal to the latch circuit, the latch circuit transmits the second switching signal to the signal switch array 206 when determining that the received first switching signal satisfies the timing condition, the signal switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module 201 to the second CPU module 202 after receiving the second switching signal, and after the main/standby switching occurs, the monitoring data collected by the shared hardware module 207 transmits the monitoring data to the monitoring center server 130 through the first PHY interfaces of the second CPU module 202 and the ethernet switch chip 208.

In summary, in the active/standby switching method for monitoring a collector provided in this embodiment, the first CPU module 201 collects monitoring data through the shared hardware module, the second CPU module 202 receives an active/standby switching command sent by the remote server through the communication module 210, and after receiving the active/standby switching command sent by the remote server, the second CPU module 202 sends a first switching signal to the latch circuit; when the latch circuit receives that the first switching signal sent by the second CPU module 202 satisfies the timing condition, the latch circuit sends a second switching signal to the signal switch array 206, and the signal switch array 206 switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module. Whether the first CPU module 201 meets the switching condition is judged by judging whether the first main/standby switching command and the second main/standby switching command can be received at the same time in the second time length, so that the main/standby switching method of the monitoring collector is provided, and the uninterrupted service work can be ensured.

Fig. 8 shows a schematic diagram of a latch circuit of a monitoring acquisition device according to another exemplary embodiment of the present application.

The active/standby switching module 205 includes a latch circuit, and the latch circuit is configured to send a second switching signal to the signal switch array 206 when the first switching signal sent by the second CPU module 202 satisfies the timing condition. Illustratively, in the present embodiment, the SN54LS273 chip is used as a core of the first latch circuit, the SN54LS273 chip may make a determination on the timing of the first switching signal sent by the second CPU module 202, and in a case that the timing of the first switching signal satisfies a timing condition, the latch circuit sends the second switching signal to the signal switch array 206; when the timing sequence of the first switching signal does not satisfy the timing sequence condition, the signal switch array 206 ignores the first switching signal, so as to prevent the signal switch array 206 from generating a false switching due to an interference signal.

Illustratively, when the latch circuit receives the first switching signal sent by the second CPU block 202, the chip-on working signal EN, the clock signal CLK and the first switching signals D0 to D7 sent by the second CPU block 202 are output according to the timing logic requirement of the SN54LS273, and when the latch circuit receives the first switching signal sent by the second CPU block 202 and meets the timing condition, the latch circuit sends the second switching signal to the signal switch array 206 through the pin. Meanwhile, the first CPU module 201 and the second CPU module 202 can read the states of the pins SWT0 to SWT7 of the signal switch array 206 through the second latch circuit, and the SN54LS244 chip is adopted as a core of the second latch circuit in this embodiment.

Fig. 9 is a schematic diagram illustrating a first signal switch of a monitoring acquisition device according to another exemplary embodiment of the present application.

The signal switch array 206 includes a plurality of sets of signal switches, each set corresponds to one shared hardware module 207, or each shared hardware module 207 corresponds to a respective signal switch, different shared hardware modules 207 are independent from each other, and different types of signal switches are required for different types of signals.

Aiming at the signal of the UART interface, the signal speed is low, and the requirement can be met by selecting a common analog signal switch. Schematically, in this embodiment, an NX3DV3899 chip is adopted, where the NX3DV3899 chip includes SWT0 and SWT1 control pins, and is connected to an output end of a latch circuit, and is used to control the active-standby switching of each channel in a signal switch; the CPU0-TXD0 pins, the CPU1-TXD0 pins and the TXD0 pins form a group of combined channels, the CPU0-TXD0 pins and the CPU1-TXD0 pins are respectively connected with the first CPU module 201 and the second CPU module 202, and the TXD0 pins are connected with the shared hardware module 207. Similarly, the pins CPU0-RXD0, CPU1-RXD0 and RXD0 in the NX3DV3899 chip are another group of combined channels; the CPU0-TXD1 pin, the CPU1-TXD1 pin and the TXD1 pin form another group of combined channels; the CPU0-RXD0 pins, the CPU1-RXD0 pins and the RXD1 pin are another group of combined channels. Illustratively, taking a group of channels as an example in the NX3DV3899 chip, in the case that the SWT0 and SWT1 control pins do not receive the second switching signal, the monitoring data is transmitted to the TXD0 pin through the CPU0-TXD0 pins; and when the SWT0 and SWT1 control pins receive the second switching signal, the monitoring data are transmitted to the TXD0 pin through the CPU1-TXD0 pin.

Fig. 10 is a schematic diagram illustrating a second signal switch of a monitoring acquisition device according to another exemplary embodiment of the present application.

Aiming at the signal of the GPI0 interface, the signal speed is low, and the requirement can be met by selecting a common analog signal switch. Schematically, in this embodiment, an NX3DV3899 chip is adopted, where the NX3DV3899 chip includes SWT2 and SWT3 control pins, and is connected to an output end of a latch circuit, and is used to control the active-standby switching of each channel in a signal switch; the CPU0-DI0 pins, the CPU1-DI0 pins and the DI0 pin are a group of combined channels, the CPU0-DI1 pins and the CPU1-DI1 pins are respectively connected with the first CPU module 201 and the second CPU module 202, and the DI1 pin is connected with the shared hardware module 207. Similarly, the CPU0-DO0 pin, the CPU1-DO0 pin and the DO0 pin in the NX3DV3899 chip are another group of combined channels; the CPU0-DO1 pins, the CPU1-DO1 pins and the DO1 pin are another group of combined channels; CPU0-DI1 pins, CPU1-DI1 pins, and DI1 pins are another set of combined channels. Illustratively, taking a group of channels as an example in the NX3DV3899 chip, when the SWT2 and SWT3 control pins do not receive the second switching signal, the monitoring data is transmitted to the CPU0-DI0 pins through the DI0 pin; and when the control pins SWT2 and SWT3 receive the second switching signal, the monitoring data are transmitted to the pins CPU1 to DI0 through the DI0 pin.

Fig. 11 is a schematic diagram illustrating a third signal switch of a monitoring acquisition device according to another exemplary embodiment of the present application.

For the signals of the USB interface, since the signals are high-speed differential signals and are sensitive, a differential signal switch is required. Schematically, the present embodiment employs an NX3DV221 chip, where the NX3DV221 chip includes a CTL0 control pin and an SWT4 control pin. The SWT4 pin is connected with the output end of the latch circuit and is used for controlling the main-standby switching of each channel in the signal switch; and the CTL0 pin is connected with the second CPU module and is used for controlling the selection of the functional pin in the signal switch.

A CPU0-USBD + pin and a CPU 0-USBD-pin are a group of input channels; the CPU1-USBD + pin and the CPU 1-USBD-pin are another group of input channels, and the two groups of channels share one group of output channels, namely USB + and USB-. Exemplarily, in the case that the CTL0 control pin selects to use the USB function pin, when the SWT4 control pin does not receive the second switching signal, the monitoring data is transmitted to the USB + and USB-pins through the CPU0-USBD +, CPU 0-USBD-pin; and under the condition that the SWT4 control pin receives the second switching signal, the monitoring data is transmitted to the USB + and USB-pins through the CPU1-USBD + and the CPU 1-USBD-pins.

Fig. 12 is a schematic diagram illustrating a fourth signal switch of a monitoring acquisition device according to another exemplary embodiment of the present application.

Signals of a PCIE interface and a HDMI interface are sensitive due to high-speed differential signals, and a differential signal switch is required. Schematically, the CBTL06GP213 chip is adopted in the present embodiment, and the CBTL06GP213 chip includes a CTL1 control pin and an SWT5 control pin. The SWT5 pin is connected with the output end of the latch circuit and used for controlling the main-standby switching of each channel in the signal switch; and the CTL1 pin is connected with the second CPU module and is used for controlling the selection of the functional pin in the signal switch.

In this embodiment, two groups of data channels are taken as an example, a CPU0-PCIE-RX + pin and a CPU 0-PCIE-RX-pin are taken as a group of input channels; the CPU1-PCIE-RX + pin and the CPU 1-PCIE-RX-pin are another set of input channels, and the two sets of channels share one set of output channels PCIE-RX +, PCIE-RX-, and there may be more signals of the PCIE interface, which is not limited in this embodiment. Exemplarily, in the case that the CTL1 control pin selects to use the PCIE function pin, when the SWT5 control pin does not receive the second switching signal, the monitoring data is transmitted to the PCIE-RX +, PCIE-RX-pins through the CPU0-PCIE-RX +, CPU 0-PCIE-RX-pins; and under the condition that the SWT5 control pin receives the second switching number, the monitoring data is transmitted to the PCIE-RX + and the PCIE-RX-pins through the CPU0-PCIE-RX + and the CPU 0-PCIE-RX-pins.

The application also provides another implementation scheme of the monitoring acquisition equipment. In the embodiment of the present application, the first CPU module 201 and the second CPU module 202 are both connected to the shared hardware module 207 through the signal switch array 206. The shared hardware module 207 includes a first shared hardware module and a second shared hardware module.

The first scheme is as follows: at the same time, the first shared hardware module and the second shared hardware module may both be connected and conducted with the first CPU module 201.

For example, there may be a plurality of shared hardware modules, and the present embodiment takes the first shared hardware module and the second shared hardware module as an example. When the monitoring and collecting device works, the first shared hardware module and the second shared hardware module are both connected with the first CPU module 201, the second CPU module 202 is in an idle state, when the first CPU module 201 has a hardware fault or a software fault, the first CPU module 201 and the second CPU module 202 have a main-standby switching, and the second CPU module 202 is used for executing a task.

The second scheme is as follows: at the same time, the first shared hardware module is connected and conducted with the first CPU module 201, and the second shared hardware module is connected and conducted with the second CPU module 202.

Illustratively, for example, a total of m shared hardware modules need to be connected to the CPU module, n shared hardware modules among the m shared hardware modules are connected to the first CPU module 201, and m-n shared hardware modules are connected to the second CPU module 202. When a software or hardware fault occurs in the first CPU module 201, the primary/standby switching occurs between the first CPU module 201 and the second CPU module 202, and all the n shared hardware modules connected to the first CPU module 201 are switched to the second CPU module 202, that is, the second CPU module 202 is connected to the m shared hardware modules.

According to the scheme, system tasks and hardware resources can be respectively distributed to the first CPU module 201 and the second CPU module 202 according to a certain strategy, so that the first CPU module 201 and the second CPU module 202 can be operated separately and cooperatively to execute different tasks, the CPU occupancy rate can be effectively reduced, the response speed of the monitoring acquisition equipment is improved, and the processing capacity of the monitoring acquisition equipment is improved.

An embodiment of the present application further provides a computer device, where the computer device includes: the tracking device comprises a processor and a memory, wherein at least one instruction, at least one program, a code set or an instruction set is stored in the memory, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to realize the tracking method of the video data provided by the above method embodiments.

Optionally, the computer device is a server. Illustratively, fig. 13 is a block diagram of a server according to an exemplary embodiment of the present application.

In general, the server 1100 includes: a processor 1101 and a memory 1102.

Processor 1101 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like.

The processor 1101 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array), an ARM (Advanced RISC Machine, RISC microprocessor), a cpu X86 (central Processing unit), a PowerPC (reduced instruction set architecture), a single chip microcomputer, and an open instruction set architecture RISC-V based on the reduced instruction set principle. The processor 1101 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 1101 may be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content that the display screen needs to display. In some embodiments, the processor 1101 may further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

Memory 1102 may include one or more computer-readable storage media, which may be non-transitory. Memory 1102 can also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer readable storage medium in the memory 1102 is configured to store at least one instruction for execution by the processor 1101 to implement the method for master-slave switching of a monitoring acquisition device provided by the method embodiments of the present application.

In some embodiments, the server 1100 may also optionally include: an input interface 1103 and an output interface 1104. The processor 1101, the memory 1102, and the input interface 1103 and the output interface 1104 may be connected by a bus or signal lines. Various peripheral devices may be connected to input interface 1103 and output interface 1104 via buses, signal lines, or circuit boards. The Input interface 1103 and the Output interface 1104 can be used to connect at least one peripheral device related to I/O (Input/Output) to the processor 1101 and the memory 1102. In some embodiments, the processor 1101, the memory 1102 and the input and

output interfaces

1103, 1104 are integrated on the same chip or circuit board; in some other embodiments, the processor 1101, the memory 1102, and any one or both of the input interface 1103 and the output interface 1104 may be implemented on separate chips or circuit boards, which is not limited in this application.

Those skilled in the art will appreciate that the architecture shown in FIG. 13 does not constitute a limitation on the server 1100, and may include more or fewer components than those shown, or combine certain components, or employ a different arrangement of components.

The embodiment of the present application further provides a computer storage medium, where at least one program code is stored in the computer readable storage medium, and when the program code is loaded and executed by a processor of a computer device, the method for switching between a main device and a standby device of a monitoring acquisition device provided in the foregoing method embodiments is implemented.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the above readable storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only an example of the present application and should not be taken as limiting, and any modifications, equivalent switches, improvements, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A monitoring acquisition device, characterized in that it comprises: the system comprises a first Central Processing Unit (CPU) module, a second CPU module, a communication module, a shared hardware module, a main/standby switching module and a signal switching switch array;

the main/standby switching module is used for switching the CPU module connected with the shared hardware module from the first CPU module to the second CPU module.

2. The monitoring acquisition device of claim 1 wherein the communication module comprises: the first communication module and the second communication module are arranged in parallel;

the second communication module is configured to transmit at least one of a second heartbeat signal and a second active/standby switching command between the first CPU module and the second CPU module.

3. The monitoring acquisition device of any one of claims 1 to 2, wherein the active-standby switching module comprises a latch circuit;

the latch circuit is used for sending a second switching signal to the signal switch array under the condition that a first switching signal sent by the second CPU module meets a time sequence condition.

4. The monitoring acquisition device of any one of claims 1 to 2 wherein the first CPU module comprises: the first CPU, the first memorizer, the first integrated circuit and the first power supply circuit, the said second CPU module includes: a second CPU, a second memory, a second integrated circuit, and a second power supply circuit.

5. The monitoring acquisition device of any of claims 1 to 2 wherein the shared hardware modules comprise a first shared hardware module and a second shared hardware module,

the first shared hardware module corresponds to a first switch array in the signal switch arrays;

the second shared hardware module corresponds to a second switch array of the signal switch arrays.

6. The monitoring acquisition device of any of claims 1 to 2, further comprising: the power supply module comprises a first power supply circuit and a second power supply circuit which are arranged in parallel;

and the output end of the power supply module is connected with the power supply ends of the first CPU module and the second CPU module.

7. A method for switching between a master device and a slave device of a monitoring and collecting device, wherein the monitoring and collecting device is the monitoring and collecting device according to any one of claims 1 to 6, the method comprising:

the first CPU module collects monitoring data through the shared hardware module;

8. The method according to claim 7, wherein the second CPU module sends a first switching signal to the main/standby switching module when the first CPU module satisfies a main/standby switching condition, including:

the second CPU module receives heartbeat signals periodically sent by the first CPU module through the communication module;

and the second CPU module sends the first switching signal to the main/standby switching module under the condition that the heartbeat signal is not received within a preset time length.

9. The method of claim 8, wherein the communication module comprises a first communication module and a second communication module in parallel;

the second CPU module receives the heartbeat signal periodically sent by the first CPU module through the communication module, and includes:

the second CPU module receives a first heartbeat signal periodically sent by the first CPU module through the first communication module, and receives a second heartbeat signal periodically sent by the first CPU module through the second communication module;

the second CPU module sends the first switching signal to the active/standby switching module when not receiving the heartbeat signal within a first time period, including:

and the second CPU module sends the first switching signal to the main/standby switching module under the condition that the first heartbeat signal and the second heartbeat signal are not received within the first time length.

10. The method according to claim 7, wherein the second CPU module sends a first switching signal to the active/standby switching module when the first CPU module satisfies an active/standby switching condition, including:

the first CPU module sends a main/standby switching command to the second CPU module through the communication module;

and the second CPU module sends the first switching signal to the main/standby switching module under the condition of receiving the main/standby switching command.

11. The method of claim 10, wherein the communication module comprises a first communication module and a second communication module in parallel;

the first CPU module sends a master-slave switching command to the second CPU module through the communication module, and the master-slave switching command comprises the following steps:

the first CPU module sends a first main/standby switching command to the second CPU module through the first communication module, and receives a second main/standby switching command sent by the second CPU module through the second communication module;

the second CPU module sends the first switching signal to the active/standby switching module when receiving the active/standby switching command, where the first switching signal includes:

and the second CPU module sends the first switching signal to the main/standby switching module under the condition that the first main/standby switching command and the second main/standby switching command are simultaneously received within the second time length.

12. The method according to any one of claims 7 to 10, wherein the active/standby switching module comprises a latch circuit;

the main/standby switching module switches the CPU module connected to the shared hardware module from the first CPU module to the second CPU module according to the first switching signal, including:

and the latch circuit sends a second switching signal to the signal switch array under the condition that a first switching signal sent by the second CPU module meets a time sequence condition, wherein the second switching signal is used for controlling the signal switch array to switch the CPU module connected with the shared hardware module from the first CPU module to the second CPU module.

13. The method according to any of claims 7 to 10, wherein the shared hardware modules comprise a first shared hardware module and a second shared hardware module,

the method further comprises the following steps:

in the same time, the first shared hardware module and the second shared hardware module are both connected and conducted with the first CPU module;

or the like, or, alternatively,

and in the same time, the first shared hardware module is connected and conducted with the first CPU module, and the second shared hardware module is connected and conducted with the second CPU module.

14. A monitoring acquisition system, characterized in that the system comprises a data sensor, a monitoring acquisition device and a monitoring center server, wherein the monitoring acquisition device is the monitoring acquisition device according to any one of claims 1 to 6;

the data sensor is connected with the monitoring acquisition equipment through the shared hardware module;

the monitoring acquisition equipment is connected with the monitoring center server through the communication module.

15. A computer-readable storage medium having stored therein at least one instruction, at least one program, set of codes, or set of instructions, which is loaded and executed by a processor to implement the method for master-slave switching of a supervisory capture device according to any of claims 7 to 13.