RU204275U1 - FAIL-SAFE PROCESSOR WITH ERROR CORRECTION IN THE DATA BYTE - Google Patents

Abstract

The utility model relates to the field of computing. The technical result of the claimed utility model is the correction of errors in the information byte that occur in the computer processor when performing arithmetic and logical operations due to the absence or occurrence of unnecessary transfers. The technical result is achieved due to a fault-tolerant processor with error correction in the information byte containing the control node, the operational node, the operation code decoder, the clock pulse generator, the control unit, the first switch, the second switch, the third switch, the command counter, the shift counter, the address register, number register, adder register, additional register, additional code register, adder, block of logical operations and control, including block of logical addition according to mod2, block of inversion, block of logical addition, block of logical multiplication, functional diagram of correction formation when performing arithmetic operations, functional diagram forming a correction when performing an OR operation, a functional diagram of forming a correction when performing an AND operation, a functional diagram of generating a correction when performing a shift operation, a delay element, a first block of unequal elements, a second block of unequal elements, a third block of unequal elements, the first block of OR elements, the second block of OR elements, a coding block, the first block of AND elements, the second block of AND elements, an AND element. 3 Il.

Description

The utility model relates to computer technology. Known device for storing and transmitting data with error correction in information bytes and error detection in information bytes (Patent for invention No. 2448359 "Device for storing and transmitting data with error correction in information bytes and error detection in information bytes" authors: Borisov K.Yu. , Malofeev Yu.G., Osipenko P.N., Pavlov A.A., Pavlov P.A., Pavlov A.A., Horuzhenko O.V., Tsar'kov A.N., dated April 5, 2011 .) containing a memory unit, an input coding unit, an output coding unit, an error syndrome calculation unit, a decoder, a switch, a switch unit, a corrector, a corrector unit, characterized in that it additionally contains a first block of OR elements, a second block of OR elements, an inverter , element And, block of elements And, input of setting the device to zero state, write input, read input, address inputs, twenty-four-bit information inputs, synchronization input, information outputs, signal output "error", input of setting to zero, input records, read input, address inputs, are connected respectively to the first, second, third and fourth inputs of the memory unit, the synchronization input is connected to the fifth input of the memory unit and to the first input of the block of elements AND, information inputs are connected to the sixth inputs of the memory unit and to the inputs of the input a coding unit that generates the values of the check bits r ₁ , r ₂ , r ₃ , r ₄ , r ₅ , r ₆ , r ₇ , r ₈ by adding modulo 2 information symbols x ₁ x ₂ x ₃ , z ₁ z ₂ z ₃ , a ₁ a ₂ a ₃ , c ₁ c ₂ c ₃ , e ₁ e ₂ e ₃ , f ₁ f ₂ f ₃ , g ₁ g ₂ g ₃ , h ₁ h ₂ h _3. , arriving at the inputs of the input coding unit , in accordance with the rule: r ₁ = x ₁ ⊕z ₁ ⊕а ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕h ₁ ; r ₂ = x ₂ ⊕z ₂ ⊕а ₂ ⊕с ₂ ⊕е ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ; r ₃ = x ₃ ⊕z ₃ ⊕a ₃ ⊕c ₃ ⊕e ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ; r ₄ = x ₁ ⊕ z ₃ ⊕ a ₂ ⊕ a ₃ ⊕ c ₂ ⊕ е ₁ ⊕ е ₃ ⊕ f ₁ ⊕ f ₂ ⊕ f ₂ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ; r ₅ = x ₂ ⊕ x ₃ ⊕ z ₁ ⊕ a ₃ ⊕ c ₁ ⊕ c ₃ ⊕е ₁ ⊕е ₂ ⊕ f ₂ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ; r ₆ = x ₃ ⊕ z ₂ ⊕ z ₃ ⊕ a ₁ ⊕ c ₁ ⊕ c ₂ ⊕ е ₂ ⊕ f ₁ ⊕ f ₃ g ₁ ⊕ g ₂ ⊕ g ₃ ; r ₇ = x ₃ ⊕ z ₃ ⊕ a ₁ ⊕ a ₃ ⊕ c ₂ ⊕ е ₁ ⊕ f ₂ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ; r ₈ = x ₁ ⊕ x ₂ ⊕ z ₂ ⊕ а ₂ ⊕ а ₃ ⊕ с ₃ ⊕ е ₃ ⊕ f ₂ ⊕f ₃ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ , which arrive at the seventh inputs of the memory node, the information outputs of the node memory are connected, respectively, to the first inputs of the equalizer, the block of correctors and to the inputs of the output coding unit, which generates the values of the check check digits r _P1 , r _2P , r _3P , r _4P , r _5P , r _6P r _7P r _8P by adding modulo 2 information characters x _1P x _2P x _3P , z _1P z _2P z _3P , a _1P a _2P a _3P , s _1P with _2P with _3P , e _1P e _2P e _3P , f _1P f _2P f _3P , g _1P g _2P g _3P , h _1P h _2P h _3P arriving at the inputs of the input coding block from the information outputs of the memory node, in accordance with the rule :: r _1P = x _1P ⊕z _1P ⊕a _1P ⊕s _1P ⊕е _1P ⊕f _1P ⊕g _1P ⊕h _1P ; r = x _{2P 2P 2P} ⊕z ⊕a ⊕s _{2P 2P 2P} ⊕e ⊕f ⊕g _{2P 2P 2P} ⊕h; r _3P = x _3P ⊕z _3P ⊕a _3P ⊕c _3P ⊕e _3P ⊕f _3P ⊕g _3P ⊕h _3P ; r _4P = x _1P ⊕ z _3P ⊕ a _2P ⊕ a _3P ⊕ s _2P ⊕ e _1P ⊕ e _3P ⊕ f _1P ⊕ f _2P ⊕g _1P ⊕ g _2P ⊕ g _3P ; r _5P = x _2P ⊕ x _3P ⊕ z _1P ⊕ a _3P ⊕ s _1P ⊕ s _3P ⊕е _1P ⊕е _2P ⊕ f _2P ⊕g _1P ⊕ g _2P ⊕ g _3P ; r _6P = x _3P ⊕ z _2P ⊕ z _3P ⊕ a _1P ⊕ s _1P ⊕ s _2P ⊕ e _2P ⊕ f _1P ⊕ f _3P ⊕g _1P ⊕ g _2P ⊕ g _3P ; r _7P = x _3P ⊕ z _3P ⊕ a _1P ⊕ a _3P ⊕ s _2P ⊕ e _1P ⊕ f _2P ⊕g _1P ⊕ g _2P ⊕ g _3P ; r _8P = x _1P ⊕ x _2P ⊕ z _2P ⊕ a _2P ⊕ a _3P ⊕ s _3P ⊕ e _3P ⊕ f _2P ⊕f _3P ⊕g _1P ⊕ g _2P ⊕ g _3P , the outputs of the output coding block are connected to the first inputs of the syndrome computation unit errors to the second inputs of which, the outputs of the control bits of the memory unit are connected, the first outputs of the error syndrome calculation unit are connected to the first inputs of the decoder, to the first inputs of the switch, to the inputs of the first block of OR elements and to the first inputs of the switch unit, the second outputs of the error syndrome calculation unit are connected to the second inputs of the decoder and to the second inputs of the first block of OR elements, the outputs of the decoder are connected to the inputs of the second block of OR elements, while the first output of the decoder is connected to the second input of the switch, and the second outputs are connected to the second inputs of the block of switches, the output of the second block of OR elements through the inverter is connected to the first input of the AND element, the second input of which is connected to the output of the first block of OR elements, the output of the AND element is the output of the signal "error", out The switch odes are connected to the second inputs of the corrector, the outputs of the switch block are connected to the second inputs of the correctors, the outputs of the corrector and the correctors block are connected to the second inputs of the I element block, the outputs of which are the information outputs of the device.

The disadvantage of the device is the limited scope of its application, since it does not allow correcting errors in information processing devices.

The closest in technical solution is a processor with increased reliability of functioning (Patent for invention No. 2439667 "Processor with increased reliability of functioning" authors: Bobkov S.G., Osipenko P.N., Pavlov A.A., Pavlov P.A., Pavlov A A.A., Khoruzhenko O.V., Tsar'kov A.N., dated 08.07.2010), containing a control node, an operational node, the first inputs of the control node are the inputs of the processor, the second group of inputs of the control node is connected to the first outputs of the operational node , the outputs of the control node are connected to the first inputs of the operational node, the second inputs of which are data inputs, and the second outputs are data outputs, characterized in that it additionally contains an operation code decoder, a clock pulse generator, a control unit, the first switch, the second switch, the third switch, command counter, shift counter, address register, number register, adder register, additional register, complementary code register, adder, block to control, control memory, block of logical operations and control, including block of logical addition according to mod2, block of inversion, block of logical addition, block of logical multiplication, functional diagram of correction formation when performing arithmetic operations, functional diagram of correction formation when performing OR operation, functional diagram of formation corrections when performing an AND operation, a functional diagram of forming a correction when performing a shift operation, a delay element, a first block of unequal elements, a second block of unequal elements, a third block of unequal elements, a first block of OR elements, a second block of OR elements, a coding block, a first block of AND elements , the second block of elements And, the element And, the outputs of the exchange device are connected to the first input of the control unit and to the first input of the second switch, the second inputs of which are connected to the outputs of the memory device, the first outputs of the second switch go to the input of the device about exchange, the second outputs go to the input of the memory device, and the third outputs are connected, respectively, to the first inputs of the command counter, shift counter, number register, adder register, additional register, additional code register, to the inputs of the operation code decoder, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register, the third input of the control unit is connected to the outputs of the operation code decoder, and the fourth input is connected to the outputs of the clock pulse generator, and the fifth input is connected to the first output of the control memory, the first output of the control unit is connected to the input of the control memory, the first outputs of which are connected to the first inputs of the control unit, the second output of the control unit is connected to the second input of the first switch, the third and fourth inputs of which are connected respectively to the outputs of the address register and the command counter, and from the second output the address of the memory cell is removed. th device, the third output of the control unit is connected, respectively, to the second inputs of the control unit, to the second inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group inputs of the second switch, to the first group of inputs of the block of logical operations and control and is the output of sync pulses, the second, third, fourth fifth outputs of the control memory are connected to the third and fourth fifth and sixth inputs of the control unit, while the second output is connected to the fourth input of the second switch, and the third, fourth and fifth outputs of the control memory unit are connected, respectively, to the third, fourth, fifth and sixth inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the first group of inputs of the block of logical operations and control and are outputs of control signals, read signals, write signals, signals for setting devices to a zero state, the sixth output of the control memory unit is connected to the fifth input of the control unit, outputs of the number register, adder register, register additional, additional code register are connected to the second inputs of the third switch and to the fifth inputs of the second switch, the output of the shift counter is connected to the sixth inputs of the second switch, the first outputs of the third switch are connected respectively to the inputs of the adder and to the second inputs of the logical operations and control unit, the outputs of the adder are connected to the third inputs of the block of logical operations and control, the second, third, fourth, fifth, sixth, seventh and eighth outputs of the third switch are connected to the fourth, fifth, sixth, seventh, eighth, ninth and tenth inputs of the block of logical operations and control, the outputs of which are connected by the seventh th, eighth and ninth inputs of the second switch.

The disadvantage of the device is the insufficient fault tolerance of the processor, since no correction of the arising errors is provided.

The task of the utility model is to correct errors in the information byte that occur in the computer processor when performing arithmetic and logical operations due to the absence or occurrence of unnecessary hyphens.

The essence of the utility model lies in the fact that a processor containing a control unit, an operating unit, an operation code decoder, a clock pulse generator, a control unit, a first switch, a second switch, a third switch, a command counter, a shift counter, an address register, a number register, a register adder, additional register, additional code register, adder, block of logical operations and control, including block of logical addition according to mod2, block of inversion, block of logical addition, block of logical multiplication, functional diagram of correction formation when performing arithmetic operations, functional diagram of correction formation during execution OR operations, a functional diagram of the correction generation when performing an AND operation, a functional diagram of a correction generation when performing a shift operation, a delay element, the first block of unequal elements, the second block of unequal elements, the third block of unequal elements, the first block is an element s OR, second block of OR gates, coding block, first block of AND gates, second block of AND gates, AND gate, first, second, third, fourth, fifth inputs of logical operations and control block, first, second, third outputs of logical operations block and control, control memory, inputs from an exchange device, data inputs from a storage device, an output to an exchange device, data outputs to a storage device, an output of a storage device address, sync pulse outputs, outputs for control signals, outputs for a read command, outputs for write signals, outputs for signals of setting to zero, outputs of the exchange device are connected to the first input of the control unit and to the first input of the second switch, the second inputs of which are connected to the outputs of the memory device, the first outputs of the second switch go to the input of the exchange device, the second outputs go to the input of the memory device , and the third outputs are connected respectively to the first inputs of the count chik commands, shift counter, number register, adder register, additional register, additional code register, to the inputs of the operation code decoder, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register, the third input of the block control unit is connected to the outputs of the operation code decoder, and the fourth input is connected to the outputs of the clock pulse generator, and the fifth input is connected to the first output of the control memory, the first output of the control unit is connected to the input of the control memory, the second output of the control unit is connected to the second input of the first switch, the third and the fourth inputs of which are connected, respectively, to the outputs of the address register and the command counter, and the address of the memory cell is removed from the second output, the third output of the control unit is connected to the second inputs of the command counter, shift counter, address register, number register, adder register, additional register , regis tra additional code, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the first input of the block of logical operations and control and is the input of clock pulses, the second, third, fourth and fifth outputs of the control memory unit are connected respectively to the third, fourth, fifth and to the sixth inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the second inputs of the block of logical operations and control and are the outputs of the control signals, read signals, recording signals, signals for setting devices to a zero state, the outputs of the number register, adder register, additional register, additional code register are connected to the second inputs of the third switch and to the fourth inputs of the second switch, the output of the shift counter is connected to the fifth inputs of the second about the switch, the first outputs of the third switch are connected, respectively, to the inputs of the adder and to the third inputs of the logical operations and control unit, the outputs of the adder are connected to the fourth inputs of the logical operations and control unit, the second outputs of the third switch are connected to the fifth inputs of the logical operations and control unit, which differs in that that it additionally contains a decoder, a block of OR elements, a block of AND elements, a corrector, and the first outputs of the logical operations and control block are connected to the first inputs of the corrector, the second outputs are connected to the sixth inputs of the second switch, the third outputs of the logical operations and control block are connected to the first the inputs of the I element block and the inputs of the decoder, the first group of outputs of which is connected to the second inputs of the I element block, the third input of which is connected to the third output of the control unit, and the output is connected to the second input of the corrector, the outputs of the corrector are connected to the seventh inputs of the second switch, the second group output ov of the decoder is connected to the inputs of the OR element block, the output of which is connected to the eighth input of the second switch.

The processor (Fig. 1) contains a control unit 1, an operating unit 2, an opcode decoder 3, a clock generator 4, a control unit 5, a first switch 6, a second switch 7, a third switch 8, a command counter 9, a shift counter 10, a register 11 addresses, register 12 numbers, register 13 adder, additional register 14, additional register 15, adder 16, block 17 of logical operations and control, first 18, second 19, third 20, fourth 21, fifth 22 inputs of block 17 of logical operations and control, first 23, second 24, third 25 outputs of block 17 of logical operations and control, control memory 26, inputs 27 of the exchange device, inputs 28 data from the memory device, output 29 to the exchange device, outputs 30 data to the storage device, output 31 addresses memory device, outputs 32 sync pulses, outputs 33 for control signals, outputs 34 for the read command, outputs 35 for write signals, outputs 36 for signals to set to zero, e decoder 37, block 38 of OR elements, block 39 of AND elements, corrector 40.

The block 17 of logical operations and control (Fig. 2) contains a block 41 of addition mod2, block 42 of logical addition, block 43 of logical multiplication, a functional circuit 44 for generating a correction when performing arithmetic operations, a functional circuit 45 for generating a correction when performing an OR operation, a functional circuit 46 for generating a correction when performing an AND operation, a functional circuit 47 for generating a correction when performing a shift operation, a delay element 48, a first block 49 of unequal elements, a second block 50 of unequal elements, a third block 51 of unequal elements, a first block 52 of OR elements, a second block 53 of elements OR, first coding block 54, second coding block 55, first AND block 56, second AND block 57.

The functional diagram 44 of the formation of the correction when performing arithmetic operations (Fig. 3) contains the first element 58 AND, the second element 59 AND, the third element 60 AND, the fourth element 61 AND, the fifth element 62 AND, the sixth element 63 AND, the first element 64 OR, second element 65 OR, third element 66 OR, fourth element 67 OR, fifth element 68 OR, sixth element 69 OR.

Functional diagram 47 for generating a correction when performing a shift operation.

The outputs 27 of the exchange device are connected to the first input of the control unit 5 and to the first input of the second switch 7, the second inputs 28 of which are connected to the outputs of the storage device, the first outputs of the second switch 7 are fed to the input 29 of the exchange device, the second outputs are fed to the input of the storage device, and the third outputs are connected, respectively, to the first inputs of the command counter 9, the shift counter 10, the number register 12, the adder register 13, the additional register 14, the additional code register 15, to the inputs of the operation code decoder 3, to the second inputs of the control unit 5, to the first input of the first switch 6, the first output of which is connected to the first input of the address register 11, the third input of the control unit 5 is connected to the outputs of the decoder 3 of the operation code, and the fourth input is connected to the outputs of the clock generator 4, and the fifth input is connected to the first output of the control memory 26, the first the output of the control unit 5 is connected to the input of the control memory 26, the second you the stroke of the control unit 5 is connected to the second input of the first switch 6, the third and fourth inputs of which are connected, respectively, to the outputs of the address register 11 and the command counter 9, and the memory cell address is removed from the second output 31, the third output of the control unit 5 is connected to the second inputs counter 9 commands, counter 10 shifts, register 11 address, register 12 number, register 13 adder, register 14 additional, register 15 additional code, to the first group of inputs of the third switch 8, to the third group of inputs of the second switch 7, to the first input 18 of the block 17 logical operations and control and is the input of sync pulses, the second, third, fourth and fifth outputs of the control memory unit are connected, respectively, to the third, fourth, fifth and sixth inputs of the command counter 9, shift counter 10, address register 11, number register 12, adder register 13 , register 14 additional, register 15 additional code, to the first group of inputs the third th switch 8, to the third group of inputs of the second switch 7, to the second inputs 19 of the block 17 of logical operations and control and are the outputs of control signals, read signals, write signals, signals to set devices to zero, register outputs 12, register 13 of the adder, additional register 14, additional code register 15 are connected to the second inputs of the third switch 8 and to the fourth inputs of the second switch 7, the output of the shift counter 10 is connected to the fifth inputs of the second switch 7, the first outputs of the third switch 8 are connected, respectively, to the inputs of the adder 16 and to the third inputs 20 of the block 17 of logical operations and control, the outputs of the adder 16 are connected to the fourth inputs 21 of the block 17 of logical operations and control, the second outputs of the third switch 8 are connected to the fifth inputs 22 of the block 17 of logical operations and control, characterized in that it additionally contains a decoder 37, block 38 OR elements, block 39 AND elements, corrector 4 0, and the first outputs of the block 17 of logical operations and control are connected to the first inputs of the equalizer 40, the second outputs are connected to the sixth inputs of the second switch 7, the third outputs of the block 17 of logical operations and control are connected to the first inputs of the block 30 of the AND elements and to the inputs of the decoder 37, the first group of outputs of which is connected to the second inputs of the block 39 of the elements And, the third input of which is connected to the third output of the control unit 5, and the output is connected to the second input of the equalizer 40, the outputs of the equalizer 40 are connected to the seventh inputs of the second switch 7, the second group of outputs of the decoder 37 is connected to the inputs of the OR element block 38, the output of which is connected to the eighth input of the second switch 7.

The processor is designed to process information coming from the random access memory to input 28.

To detect and correct errors in the random access memory, codes with the detection and correction of error bytes are used (in this case, the error byte means errors whose multiplicity does not exceed the number of bits b of the information block).

In this case, we have a code set

the value of the check digits r ₁ ^f r ₂ ^f ... r _b ^f , r ₁ ^g r ₂ ^g ........ r _b ^g , allow to form the value of the error syndrome in this case, the first part of the check digits r ₁ ^f r ₂ ^f … R _b ^f determines the error vector (erroneous bits in the information block), and the value of the second part of the check bits r ₁ ^g r ₂ ^g ........ r _b ^{g is} intended to determine the number of the erroneous block (byte) of information.

The number of bytes of information is determined by the formula: w = 2 ^b

Thus, the code set is transmitted in the form

The result of mod2 addition of the transmitted values of the check bits, r _i ^f , r _i ^g and check bits r _i ^fП , r _i ^gП formed with respect to the received information bits will give the value of the error syndrome, which includes two parts

The value of the error syndrome S ^f determines the error vector (erroneous bits in the information block), and the value of the error syndrome S ^g determines the number of the erroneous block (byte) of information.

The decoding strategy is based on the following provisions:

1. S ^f = 0; S ^g = 0. There are no errors.

2. S ^f = 0; S ^g ≠ 0. An error occurred in the check bits or an uncorrectable error in the information bytes.

3. S ^f ≠ 0; S ^g ≠ 0 (S ^g = 0). An error occurred in information bytes (one byte - corrected, two - detectable).

For the code (32.8), the value of the second part of the check bits is formed by checks:

r ₁ = x ₁ ⊕z ₁ ⊕а ₁ ⊕с ₁ ⊕e ₁ ⊕f ₁ ⊕g ₁ ⊕h ₁ ;

r ₂ = x ₂ ⊕z ₂ ⊕a ₂ ⊕c ₂ ⊕e ₂ ⊕f ₂ ⊕g ₂ ⊕h ₂ ;

r ₃ = x ₃ ⊕z ₃ ⊕а ₃ ⊕с ₃ ⊕е ₃ ⊕f ₃ ⊕g ₃ ⊕h ₃ ;

r ₄ = x ₁ ⊕ z ₃ ⊕ a ₂ ⊕ a ₃ ⊕ c ₂ ⊕ е ₁ ⊕ е ₃ ⊕ f ₁ ⊕ f ₂ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ;

r ₅ = x ₂ ⊕ x ₃ ⊕ z ₁ ⊕ a ₃ ⊕ c ₁ ⊕ c ₃ ⊕е ₁ ⊕е ₂ ⊕ f ₂ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ;

r ₆ = x ₃ ⊕ z ₂ ⊕ z ₃ ⊕ a ₁ ⊕ c ₁ ⊕ c ₂ ⊕ е ₂ ⊕ f ₁ ⊕ f ₃ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ;

r ₇ = x ₃ ⊕ x ₃ ⊕ a ₁ ⊕ a ₃ ⊕ c ₂ ⊕ e ₁ ⊕ f ₂ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ ;

r ₈ = x ₁ ⊕ x ₂ ⊕ z ₂ ⊕ a ₂ ⊕ a ₃ ⊕ c ₃ ⊕ e ₃ ⊕ f ₂ ⊕f ₃ ⊕g ₁ ⊕ g ₂ ⊕ g ₃ .

Table 1 shows the values of error syndromes of the code (32,8), which corrects multiple errors in the block of information and detects errors in arbitrary blocks of information.

The processor includes two main devices: control node 1 and operation node 2.

The control unit 1 coordinates the actions of the units of the operational unit 2 with each other and with other computer devices, and also performs a set of operations, including commands for accessing memory. It generates control signals in a certain time sequence, under the action of which the required actions are performed in the nodes of the operating unit 2.

Each such elementary action performed in the operating node 2 during one clock period is called a micro-operation.

Several micro-ops can be executed simultaneously at certain clock periods. Such a set of simultaneously executed micro-operations is called a microinstruction, and the entire set of microinstructions designed to solve a specific task is called a microprogram.

The total time interval during which the sampling, storage and transformation of one command into a set of control signals occurs is called the operating cycle of the control node 1.

Thus, the control unit 1 converts the command into an appropriate set of control signals and provides:

reading the command located in the next memory cell;

decoding of the operation code (command);

finding operands (numbers) at the specified address contained in the command;

ensure the issuance of control signals to the operating unit for performing the actions on them specified in the command operation code.

In this case, microprogram control unit 1 is used, in which microinstructions are stored in control memory 19.

In this case, words representing commands are stored in memory in sequentially numbered cells, which allows you to form the address of the next command by adding one to the address of the previous command, while the word consists of several parts: for example, an operation code indicating the type of operation and addresses of numbers, over which the corresponding operation should be performed.

The decoder 3 of the opcode according to the command selected from the main memory determines the number of the required firmware in the control memory 26.

The generator of 4 clock pulses is designed to generate clock and synchronizing pulses.

The counter 9 commands is designed to form the address of the memory cell of the next command, by natural sampling, i.e. adding one to its content.

Register 11 address is designed to form the address of the memory cell in the instructions of the conditional or unconditional jump with return.

The control unit 5 is designed to determine the address of the next micro-command in the control memory 20, generate the address of the next command (control the operation of the first switch 6), coordinate the work (issue sync pulses) of processor 1 devices.

The control memory 26 is a read-only memory and is intended for issuing (depending on the operation code) control signals (control signals, read signals, write signals, signals for setting to zero) to the functional units of the processor. In this case, the memory word contains information bits (for control signals) and control bits formed on the basis of the proposed coding method.

Operational unit 2 is designed to perform arithmetic and logical operations and includes (Fig. 1) shift counter 10, number register 12, adder register 13, additional register 14, additional code register 15, adder 16, logical operations and control unit 17 ...

The counter 10 shifts is designed to count the number of shifts when performing multiplication and division operations, the number of shifts of intermediate results and normalization.

Register 11 address is a memory register and is designed to store the address of the next command.

The register 12 of the number is a memory register and is intended for storing operands when performing arithmetic and logical operations (storing the multiplicand when performing a multiplication operation and a divisor when performing a division operation).

The register 13 of the adder (accumulator) is a shift register (to the right when performing a multiplication operation and to the left when performing a division operation), and is intended to store the divisible high-order bits of the multiplication result.

Note that when performing the division operation, the control unit 5 analyzes the value of the sign bit of the number register 12 and the adder register 13.

The additional register 14 is a shift register (to the right - when performing a multiplication operation and to the left - when performing a division operation), and is intended to store the multiplier and the least significant bits of the multiplication result when performing a multiplication operation and the result of division when performing a division operation).

Note that when performing the multiplication operation, the control unit 5 analyzes the value of the least significant bit of the additional register 14.

The complement register 15 is a memory register and is intended to store a negative two's complement number (when performing a subtraction and a division operation).

Block 17 logical operations and control (Fig. 2) is designed to detect and correct errors that occur when performing arithmetic and logical operations.

The adder 16 is a parallel n-bit adder and is designed to perform the operation of adding numbers, for example, two code sets

As a result of arithmetic addition of information bits and mod2 addition of control values, we obtain the result

Analysis of the result obtained allows us to conclude that the control values do not correspond to the result of the sum of information bits.

To form the required value of the check digits, an amendment formed with respect to the transfer function is added to the obtained value of the check digits by encoding it with the considered information coding method.

The functional diagram 44 of the formation of the amendment when performing arithmetic operations (Fig. 3) generates the function of transfers with respect to the terms under consideration

For the example under consideration, we have the transfer function

S _p = 011 111 111 011 100 111 110000.

The values of the digits of the carry function through the first block 52 of OR elements are fed to the input of the first coding block 54, from the outputs of which the values of the correction to the values of the check digits are removed when performing arithmetic operations.

For the obtained transfer function, the correction value is P _k = 10101110.

In the first block 49 of unequal elements, the bitwise addition mod2 of the values of the check digits of the addends is carried out. In the second block 50 unequal elements, the bitwise addition of the result of the sum of the values of the check digits with the values of the correction digits is carried out. As a result, we have the correct value of the check digits for the arithmetic addition operation. For our example, we get the value of the check digits

.

...

The second coding unit 55 encodes the result of the sum of the terms coming from the outputs of the adder 16.

The third block 51 unequalities is a bitwise comparison of the values of the check bits formed with respect to the received arithmetic sum and generated on the second block 50 unequal elements. The value of the error syndrome is removed from the outputs of the third block 51.

When shifting to the right, the functional circuit 47 for generating a correction when performing the shift operation generates a shift function based on the initial values of the information bits as follows

where z ₁ is the value of the transfer signal from another register, for example, to the high-order bit of the additional register from the low-order bit of the adder register when performing the multiplication operation.

The value of the bits of the function of shifts through the first block 52 of OR elements are fed to the input of the first block 54 of the coding, from the inputs of which the value of the correction to the check digits is removed when shifting to the right.

In the second block 50 of unequal elements, the bitwise addition of the correction values with the values of the check bits of the shifted information is carried out.

At the same time, the results of the shift of information bits, through the block 52 of the OR elements, are fed to the input of the second coding block 54. The results of the values of the check bits formed on the second block 50 of unequal elements and coming from the outputs of the second coding block 55 are compared bit by bit by the third block 51 of unequal elements, from the outputs of which the value of the error syndrome is taken.

For example, when shifting to the right and there is no transfer from another register of the code set

we get a binary set for the formation of the correction P

When coding this set using the proposed method by the first coding unit 54, the correction value will be P = 110 10111. Addition of mod2 by the second block of 50 non-equal elements of the original check bit value and the correction value will lead to the correct check bit value when the information bits are shifted to the right

Where S _P is the result obtained by shifting the original code set to the right.

The values of the correction symbols when shifting to the left are formed on the basis of the initial value of the information bits as follows

where z ₁ is the value of the signal for transferring the high-order bit of one register to the low-order bit of the shift register.

The formation of the error syndrome when shifting to the left is carried out in a similar way.

When performing the operation of logical addition, the value of the vector for calculating the correction to the check bits is carried out by the circuit 46 for generating the correction when performing the OR operation by performing the AND operation with respect to the bits of the addends of the same name and encoding the result obtained by the method in question.

So, for example, when performing the OR operation with respect to the information bits by the block 42 of OR elements and adding mod2 of the check bits by the first block 49 of unequal elements (Fig. 2) of the numbers A and B, we have the result

The functional diagram 45 of the formation of the correction when performing the OR operation performs the AND operation with respect to the information bits will give the vector value for calculating the correction

In this case, the first coding unit 54 will generate the correction value: P = 10000010.

As a result of addition mod2 by the second block of 50 unequal elements of the correction value and the values of the check digits coming from the first block of 49 unequal elements, we get the result: 10010100, i.e. we have the correct value of the check digits for the OR operation.

The results of the values of the check bits formed on the second block 50 of the unequal elements and coming from the outputs of the second coding block 55 are bitwise compared by the third block 51 of the unequal elements, from the outputs of which the value of the error syndrome is taken.

Similarly, an amendment is formed when performing logical multiplication, only when the correction vector is generated by the correction generation circuit 46 when the AND operation is performed, a bitwise OR operation is performed with respect to the same-named digits of the multiplier and the multiplier.

For the operations of logical addition mod2 by the mod2 addition unit 41, the formation of a correction to the check bits is not required.

So, for example, when performing the operation of addition mod2 of information bits by the block 41 of addition mod2 and check bits by the first block 49 of unequal elements (Fig. 2) of numbers A and B, we have the result

The check bit values generated by the second coding unit 55 with respect to the information bits obtained when performing arithmetic and logical operations are bitwise compared by the third unequal element block 51 with the transmitted check bit values, taking into account the correction.

In the absence of errors at its outputs, we have a zero signal value.

The work of the utility model begins with the arrival of the "Start" signal through the input group 27 of the inputs of the processor exchange device with peripheral units. On this command, block 5 issues a command to read the contents of the first memory cell from the control memory 26.

The first memory cell contains the "System Reset" command, which initializes the registers and blocks of the processor, "1" is written to the command counter 9, the control unit 1 issues micro-commands in the following sequence:

1) On the first clock cycle, the micro-command signals are fed to the read input of the command counter 9 and to the write input of the address register 11, while the contents of the command counter 9 are sent to the address register 11 (or through the first switch 6 to the address inputs of the memory device with natural sampling of commands directly from counter of 9 teams);

2) On the second cycle, one is added to the contents of the counter of 9 commands - the address of the next command is prepared;

1) On the third cycle, the microinstruction signals are fed to the read input of the address register 11 and to the read input of the contents of the memory cell at the specified address. In this case, the command stored in the first memory cell is written to register 12 of the number;

2) On the fourth clock cycle, the micro-command signals are fed to the input of reading the register 12, the input of the second switch 7 and to the input of the decoder 3 of the operation code, where they are decoded, after which the control unit 1 goes to the second stage of operation.

For example, consider the order of execution of one of the instructions written in register 12 after the first four clock cycles.

Let in the field of the operation code of the command of the contents of the register 12 numbers written the command of adding the contents of the register 13 of the adder with the number located in the memory device at the address indicated in the address field of the register 12 numbers (when using a unicast command).

In this case, the control node 1 issues the following micro-commands:

3) on the fifth clock cycle, the microinstruction signals are fed to the input of reading the register 12, to the input of the second switch 7, the first switch 6 and to the write input of the address register 11 (the address stored in the register 12 of the number is written to the address register 11, the contents of the register 12 is reset to zero);

4) On the sixth clock cycle, the microinstruction signals are fed to the read input of the address register 11, to the input of the first switch 6, to the read input of the memory device and to the write input of the number register 12 (the second summand is written from the memory device to the number register 12 (we assume that the first summand already in register 13 of the adder);

5) On the seventh clock cycle, the microinstruction signals are fed to the read input of the number register 12 and the adder register 13, while the arithmetic logic unit performs the addition operation and writes the result of the addition to the adder register 13 as follows.

The result of the sum from the output of the adder 16 is fed to the block 17 of logical operations and control (Fig. 2), then the device operates in accordance with the example of performing arithmetic operations given above

As a result of arithmetic addition of information bits and mod2 addition of control values and correction values, we get the result: S = 010000010011101101000110 101 11000.

In this case, the generated values of the check bits with respect to the operation obtained are compared with the transmitted values of the check bits by the third block 51 of unequal elements (Fig. 2). If there is no error at its outputs, we have zero signal values.

If an error occurs as a result of summation, for example, in the third bit of the sum of the information block -X, we get the result

S = 1 * 10 000010011101101000110 001 01001.

In this case, at the output of the third block 51 of unequal elements (Fig. 2), we obtain the value of the error syndrome:

100 10001.

The set of values of the bits of the error syndrome determines the address of the information byte having an error, while the values of the first three bits of the error syndrome are the error vector and determine the erroneous bit in the information byte. According to Table 1, the resulting error syndrome indicates an error in the third bit of the information byte-X.

Table 1. Values of error syndromes of the code (32,8), which corrects error bytes in a block of information and detects in arbitrary blocks of information

The values of the error vector are fed to the first inputs of the block 39 of the elements And. From the output of the decoder 37 to the second input of the block 39 of the elements And a signal is received indicating the address of the information byte having an error. The first inputs of the corrector 40 from the outputs 23 of the block 17 of logical operations and control receive the values of the information bits, and the second inputs of the corrector 40, when the sync pulse arrives at the third inputs of the block 39 of the AND elements, the values of the error vector are received. In the corrector 40, the erroneous information bits are corrected by mod2 bitwise addition of the values of the error vector with the information bits of the information byte having the error.

From the outputs of the corrector 40, the values of the information bits and the values of the control bits from the outputs 24 of the block 17 of logical operations and control are fed to the inputs of the second switch 7.

The processor functions in a similar way when performing logical operations.

When an uncorrectable error occurs, the signals from the outputs of the decoder 37 through the OR element block 38 and the second switch 7 enter the interrupt system, where the processor failure signal is generated.

8) On the eighth cycle, a micro-command "End of operations" is issued, the transition to the next operation is carried out, the control unit 5 is reset and gives permission to start the execution of the next command, the address of which is indicated in the counter 9 of commands.

Claims (1)

Fault-tolerant processor with error correction in the information byte, containing the control node, the operational node, the operation code decoder, the clock pulse generator, the control unit, the first switch, the second switch, the third switch, the command counter, the shift counter, the address register, the number register, the adder register , an additional register, an additional code register, an adder, a block of logical operations and control, including a logical addition block according to mod2, an inverting block, a logical addition block, a logical multiplication block, a functional diagram for generating a correction when performing arithmetic operations, a functional diagram for generating a correction when performing an operation OR, a functional diagram for generating a correction when performing an AND operation, a functional diagram for generating a correction when performing a shift operation, a delay element, a first block of unequal elements, a second block of unequal elements, a third block of unequal elements, a first block OR gates, second block of OR gates, coding block, first block of AND gates, second block of AND gates, AND gate, first, second, third, fourth, fifth inputs of logical operations and control block, first, second, third outputs of logical operations block and control, control memory, inputs from an exchange device, data inputs from a storage device, an output to an exchange device, data outputs to a storage device, an output of a storage device address, sync pulse outputs, outputs for control signals, outputs for a read command, outputs for write signals, outputs for signals of setting to zero, outputs of the exchange device are connected to the first input of the control unit and to the first input of the second switch, the second inputs of which are connected to the outputs of the memory device, the first outputs of the second switch go to the input of the exchange device, the second outputs go to the input of the memory device , and the third outputs are connected respectively to the first inputs I will give a command counter, a shift counter, a number register, an adder register, an additional register, an additional code register, to the inputs of the operation code decoder, to the second inputs of the control unit, to the first input of the first switch, the first output of which is connected to the first input of the address register, the third input the control unit is connected to the outputs of the operation code decoder, and the fourth input is connected to the outputs of the clock pulse generator, and the fifth input is connected to the first output of the control memory, the first output of the control unit is connected to the input of the control memory, the second output of the control unit is connected to the second input of the first switch, the third and fourth inputs of which are connected respectively to the outputs of the address register and the command counter, and from the second output the address of the memory cell is removed, the third output of the control unit is connected to the second inputs of the command counter, shift counter, address register, number register, adder register, register additional o, additional code register, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the first input of the logical operations and control unit and is the input of sync pulses, the second, third, fourth and fifth outputs of the control memory unit are connected respectively to the third, fourth the fifth and sixth inputs of the command counter, shift counter, address register, number register, adder register, additional register, additional code register, to the first group of inputs of the third switch, to the third group of inputs of the second switch, to the second inputs of the logical operations and control unit and are outputs of control signals, read signals, recording signals, signals for setting devices to zero state, the outputs of the number register, adder register, additional register, additional code register are connected to the second inputs of the third switch and to the fourth inputs of the second switch, the output of the shift counter is connected to the fifth inputs m of the second switch, the first outputs of the third switch are connected, respectively, to the inputs of the adder and to the third inputs of the logical operations and control unit, the outputs of the adder are connected to the fourth inputs of the logical operations and control unit, the second outputs of the third switch are connected to the fifth inputs of the logical operations and control unit, which differs in that it additionally contains a decoder, a block of OR elements, a block of AND elements, a corrector, and the first outputs of the block of logical operations and control are connected to the first inputs of the corrector, the second outputs are connected to the sixth inputs of the second switch, the third outputs of the block of logical operations and control are connected to the first inputs of the block of I elements and to the inputs of the decoder, the first group of outputs of which is connected to the second inputs of the block of I elements, the third input of which is connected to the third output of the control unit, and the output is connected to the second input of the corrector, the outputs of the corrector are connected to the seventh inputs of the second switch, the second group the outputs of the decoder are connected to the inputs of the OR element block, the output of which is connected to the eighth input of the second switch.

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