SU1478213A1 - Sine and cosine computer - Google Patents

Abstract

The invention relates to computing and can be used to compute sine and cosine functions. The aim of the invention is to increase productivity while maintaining a given accuracy. The device contains a control unit 1, an operation unit 2, a memory unit 3, multiplexers 4-9, trigger 10, element 11, and element NOT 12. The goal is achieved by introducing new elements and connections. 3 il.

Description

When calculating the function XX, if the argument of the cosX function is in the I or TV quadrant, logical zeros or a logical unit are set at the first control input of multiplexer 4 and the first input of the And 1 1 element. When passing to the second input element And 11 of a single control signal from the output 36 of the control unit 1, a zero signal is set at the second control input of the multiplexer 4.

In case the argument of the cosX function is negative, then the control inputs of multiplexer 4 are set to code 01 or 10. At the output of the control, the logical unit

When calculating the function ginX, to ensure that the sign of the function is memorized, a zero signal arrives at the second input of And 11 from output 36. In accordance with the table at the output of the first multiplexer 4, a zero signal is set for sinX 0, and a single dp sinX J.O, i.e. similar to the cosX function.

The signal from the output of multiplexer 4 is fed to the information input

the trigger 10 and the gate pulse from the output 17 translates it into the zero state (for cosX O, sinX 0) or into the single state

(for co8X 0,) 0

The next clock begins by referring to memory block 3 for constant A.

On the output 34 of the control unit 1 with

the second address output of block 37 of the firmware memory through the group of 41 multiplexers passes the address of the register of the address of the constants of the registers of the group 4) containing the address of the constant

e - The contents of the address register of the constants enter the first input of the arithmetic logic unit 46, pass through the register 50 and the first information output of the switch 53, is set at the output 14 of the memory block 3

By the inversion signals at the output 16 of the memory unit 3, a constant A is set, and the control signal is written to the register 51 of the operation unit 2.

In the same clock cycle in multiplication unit 55, the contents of registers 47 and 48 are multiplied and the value of product P is described in register 49.

;

Also in this

tact

V

the address of the constant A is formed

The arithmetic logic block 46 to the value of the address of the constant Af () adds one, the address of the constant A А is written to the address register of the constants of the registers 54 of the group.

The next step, the value of the constant, through the arithmetic logic unit 46 from the output 29 of the operation unit 2, via multiplexers 7-9 and 6, is fed to the input 24 of the operation unit 2 and is written to the register 48.

Then, in the same cycle, the value of P is recorded in the register 47 for which it is sent to it from the register 49 via the multiplexer 52 and the arithmetic logic unit 46,

In the next clock cycle, the next micro-command is performed in the same way as described: contacting memory block 3 for the value of the constant At and writing At to the register 51;

oo

similarly, increasing the address of the constant A j by one determines the address of the constant A and writes it to the register of the address of the constants of the group 54 registers; in the same clock cycle the registers 47 and 48 are multiplied together and the result, P is written in the third register 44.

In the next clock cycle, according to the next microinstruction, A 0 P, through multiplexer 52, enters the first input of the arithmetic logic unit 46 and adds to the constant value -A. The result of adding P + A is generated at the output 29 of the operation unit 2 and recorded through multiplexers 7-9 and 6 and the input 24 of the operation unit 2 into the register 48 of the operation unit 2o. Next, the microcommands of the last two cycles are cyclically lost until expression (((Р +) X х Р + А) Р + А) Р + At. The result is written to register 49.

The next clock cycle begins with reference to memory block 3 for the constant A of writing it to register 5i. The contents of register 48 are multiplied by the contents of register 47 and the result, as in the previous cases, is written to register 49

In the same tact, similarly to the formation of the next constant, the address of the next command is formed.

one

ten

15

20

thirty

40 45

47K L 18

go sport In the case of the output 34 of the control unit f, the address of the register of the group 54 allocated for the instruction counter is received.

In the next step, the contents of register 49 are forwarded to the first input of the arithmetic logic unit 46, added to the obtained result F (X) is formed at the fourth output 29 of the operating device 2.

The value of the function F (x) is shifted by one bit, that is, e0, according to the control signals from the output 36 of the control unit 1, the information from the second inputs of the multiplexers 6-9 is passed. At the same time, a zero signal is set at the output of the multiplexer 8, and information from 1 to 31 bits is set at the outputs of the remaining multiplexers. The value of F (X) shifted by one bit is written to one of the registers of group 54 at the address received from control block 1.

In the same clock cycle, from the outputs 36 a control signal is generated for the condition analysis that allows the passage of information about the sign of the function from the output of the trigger 10 through the multiplexer 39 to the installation input to the trigger 42, the Start address, the function firmware is selected so that in this cycle the address the next microcommand has an even value (trigger 42 is in the zero state)

In the event that a logic O (function P) is set at the output of the trigger 10, then the state of the trigger 42 does not change. This completes the calculation of the cosX function

25

and in the next clock cycle, a set of control signals necessary for calling up the next command word and its reception is formed at the changed address.

If the output of the trigger 10 is set to logical I (function 0), the trigger 42 goes into one state, thereby increasing the address of the microcommand by one.

In the next clock cycle, at this address, the outputs 17.35, 36, and 34, the outputs of the control block i, generate signals, according to which the value of the function F (X) appears at the first input of the arithmetic logic logic

Block D6, which injects the contents of the first input and adds one to the least significant bit. Tgvs function is assigned a negative value.

This is where the calculation of the function (for xX 0) ends

To calculate the sinX function, it is necessary to change the value of the thirtieth bit, the argument code, to the opposite when forming the reduced argument Xv. For this, when generating X with the control signal from the outputs 36 of the control unit 1, the second information

input multiplexer 5 “At the same time, the first information input of multiplexer 6 receives the inverted value of the thirtieth digit of the argument code.

R the rest of the calculation of the function sinX is similar to the calculation of the function cosX.

Claims (1)

Invention Formula A device for calculating sine and cosine functions, comprising an arithmetic logic unit, a smart block Signs of the sign of the function of the control unit corresponding to the bits of the third output of the control block. Connected to the control inputs of the third multiplexer and switch, the corresponding bits of the fourth output of the control block connected to the control inputs of the fourth, fifth, sixth and seventh multiplexers, outputs which are connected via bus to the information inputs of the first and second registers and registers of the group, the output of the sign of the result of the operation of the arithmetic-logic unit is connected to the input of the sign p As a result of the operation of the control unit, the input of the operation code of the control unit is connected to the output of the memory unit and to the information input of the fifth register, the output of which is connected to the first information input of the arithmetic logic unit, the device start input is connected to the setup inputs of registers one to five, the output of the first most significant bit of that register is connected to the first control input of the second multiplexer, from the first to the fourth control unit, two register-informational inputs of which under p a, a group of registers and a memory block, the bits of the first output of the control block are connected to the sample input of the memory block, to the synchronous inputs of the first and second registers and group registers, the bits of the output of the control block are connected to the bits of the input of the selection of register registers, bits The third control output of the control unit is connected to the control inputs of the multiplication unit and the arithmetic logic unit, characterized in that, in order to improve performance while maintaining the specified precision, it introduced seven multi-entry inputs of the fourth, n to-o plexors, switch, trigger, EI, element NOT and three registers, the corresponding bits of the fourth output of the control unit are connected to the first input of the I element, and to the control input of the first multiplexer, the corresponding bits of the first output of the control unit connected to the synchronous inputs of the third, fourth, and fifth registers and trigger, the information input, the installation input to I and the output of which are connected respectively to the output of the second multiplexer, the start input of the device 50 55 second and sixth multiplexers, the output of the second most significant bit of the arithmetic logic unit is connected to the second information inputs, the fourth and sixth multiplexers, the output of the first multiplexer is connected to the third information input of the fourth multiplexer, the logical input zero of the device is connected to the third information input of the sixth multiplexer and the second and the third information input of the fifth multiplexer, the output of the lower bits of the fifth register is connected to the first five Q are connected respectively to the inputs of logical zero, logical unit of logical unit and logical zero of the device, the output of the second most significant bit of the first register is connected to the second input of the AND element, the first information input of the first multiplexer and through the element NOT to the second information input of the first multiplexer, the output of the element And under the keys to the second control input of the second multiplexer, the output of the first high-order bit of the arithmetic logic unit is connected to the first input five second and sixth multiplexers, the output of the second most significant bit of the arithmetic logic unit is connected to the second information inputs, the fourth and sixth multiplexers, the output of the first multiplexer is connected to the third information input of the fourth multiplexer, the logical input zero of the device is connected to the third information input of the sixth multiplexer and the second and the third information input of the fifth multiplexer, the output of the lower bits of the fifth register is connected to the first the information input of the seventh multiplexer, the second and third informational ports of which are connected to the output of the lower bits of the arithmetic logic unit, the first and second outputs of the switch are connected respectively to the address and informational inputs of the memory unit, the outputs of the first and second registers are connected respectively to the first and second informational the inputs of the multiplication unit, the output of which is connected to in77 FIG. g the formation of the third ryogist- (pa whose output is connected to the first information input of the third multiplexer, the second information input of which is connected to the output of the group of registers connected to the information input of the switch. 34 Fig.z