SU1269145A1 - Microprocessor calculating device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of processing units of microprocessor sections. The purpose of the invention is to increase productivity. The device contains a register of commands 1, a decoder i of a command 2, block 3 of the formation of addresses of microinstructions, a buffer memory 7, an operational block 8, a generator 9 of clock pulses, three triggers 10, 11.12, two elements NOT 13, 14, two elements EXCLUSIVE OR 15.16 ,. two multiplexers 17.18, a decoder 19, four elements AND 20-23, two elements OR 24.25, a priority encoder 26, a register 27. This set of features allows the SL to achieve the purpose of the invention. 3 il.

Description

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The invention relates to computing and can be used in the construction of processing units of microprocessor sections.

The purpose of the invention is twisting. performance.

Figure 1 presents the structural diagram of the device; in FIG. 2, the format of the command; FIG. 3 shows graphical schemes of command execution algorithms.

The microprocessor computing device contains a register of 1 commands a decoder of 2 commands, a block of 3 generation of addresses of micro-instructions, a memory of 4 micro-instructions, a register of 5 micro-instructions with outputs 6 of a micro-type attribute, a buffer memory 7, an operational block 8, a generator of 9 sync pulses, the first 10, the third 11 and second 12 triggers, elements NOT 13 and 14, first; 15 and second 16 elements EXCLUSIVE STI, first 17 and SECOND 18 multiplexers, decoder 19, second 20, fourth 21, first 22 and third 23 elements And, second 24 and first 25 elements OR, encoder 26 priority, reg. 27, input 28 Operation codes, informational outputs 29, 30-digit output, and informational input 31,

The operation of the device is described in the example of executing add, subtract, shift arithmetic to the left in the register-register format (command format is shown in Fig. 2), the CPC field specifies the operation code, the A1 field the address (number) of the register containing the first operand, field A2 address (number) of the register containing the second operand,

In shift operations, the contents of the register, determined by the A2 field of the instruction, generate the number of binary bits to which the first operand must be combined.

In FIG. 3 and in the description, the following notation is taken: A1, A2 are the command fields defining the addresses of the first and second operands, respectively, (A1), (A2) are operands at the addresses A1 and A2, respectively, AC is the central battery processor elements ;: SignN - the sign of the number of the sign of the transfer of content modulo two; MK - microinstruction, SD - data bus,

Execution of commands for sharing -the reading in the form of register-register

occupies 6 MK: 1 MK - transfer of the second operand to the battery of the operating unit; 2 MK — reading the first operand from the buffer memory; 3 MK reading the first operand from the buffer memory and performing the required operation in the operating unit; 4 MK transfer the result to the first operand; 5 MK - formation of the address of the next command, 6 MK - selection of the next word, command of the command register

When executing the command addition, the device works as follows.

Before executing the command, the triggers 10-12 are in the zero state. The first microcommand operand selected from the buffer memory 7 at the address specified by the command field A2 is transmitted to the accumulator of the operation unit 8. In field 6 of this microcommand there is a code indicating that it is necessary to write. the inverse value of the sign bit in the trigger 11, This code from the first output of the field 6 of the register 5 enters the decoder 19, which produces a microoperation at the third output

SignN® trigger 11 - trigger 11.

By this micro-operation, the inverse value Sign (A2) through the elements HE 14, AND 21 and OR 24 enters the counting input of the trigger 11, which either remains in the zero state (with Sign (A2) 1) or is set to one (with Jsign (A2) 0).

Thus, after the first microcommand has been executed, trigger 11 holds the inverse of the sign of the second operand.

The second microcommand reads the first operand defined by the field; A1 commands, In field 6 of the micro-command is the code by which the decoder 19 generates a micro-operation at the first output

Sign A1-t trigger 11.

Thus, after the second micro instruction, the state of the trigger 10 indicates the sign of the first operand.

Claims (1)

The third microcommand operand selected from the buffer memory 7 at the address specified by the A1 command field is added to the operand stored in the battery of the operation unit, the result is placed into the accumulator. In the 6th field of this microcommand is the cfd by which the decoder 19 A micro-operation is performed at the corresponding output of the SignN® Trigger 11-w trigger 11. According to the micro-operation, the Sign value (A1) enters the corresponding output of the decoder 19 through the elements AND 20 and OR 24 to the counting input of the trigger 1 1, which remains in the same states (with Sign (A1) 0), Pibo takes the opposite value (with Sign (A1) 1). Thus, after the third microcommand, the state of trigger 11 indicates the matching of the signs of the ramps (the zero state of the trigger 11 indicates that the characters of the operands are different, the one is that the characters of the operands are the same), and the state of the trigger 10 corresponds to the sign of the first operand. According to the fourth microcommand, the contents of the battery of the operating unit 8 are transferred to the buffer memory 7 at the address specified by the command A1 field. According to the information at output 29 and the state of the triggers 10 and 11, the formation of the result sign is formed according to the following rules. If trigger 11 is in a single state, i.e. operands have the same sign, overflow is possible, which is determined by matching the result sign with the sign of the operand, the value of which is stored in trigger 10. This match is determined by the EXCLUSIVE OR 15 element, which, if the signals at its inputs do not match, generates a single level output signal through the elements AND 23 and OR 2 to the first input of the encoder 26 is prioritized. At the same time, the element NOT 13 forms a signal corresponding to zero information at the output 29. This signal is applied to the second cipher cipher ra 26 priority. The third and fourth inputs of the priority encoder 26 receive the inverted and direct value of the sign bit. When signals arrive at the inputs of the priority encoder 26, signals are generated at its outputs in the following order: Overflow on the first, Zero result on the second, Result more than zero on the fourth and Result less than zero on the third output. The fourth microinstruction in field 6 contains a code defining the formation of the following microoperations: transferring to the output of multiplexer 18 information from its second group of inputs, i.e. from the priority encoder 26; recording information in register 27. Thus, after the fourth microcommand has been executed, the result is one-. The radio is written in place of the source (first) operand in the buffer memory 7, and in register 27 there is an indication of the result of the operation. According to the fifth micro-command, the address of the next command is formed, and the sixth is the reading of the command from the main memory (not shown) to the command register 1 and resetting the triggers 10-12. Block 3 generates the start address of the MiKponogram corresponding to the newly received operation code, and the cycle of operation of the device is repeated. Performing a subtraction is different from performing addition only by the first microinstruction. In the first micro-operation, the value of the second operand defined by the A2 field of the instruction is transferred to the accumulator of block 8 in the additional code, and trigger 11 uses the elements 20 and OR 24 to record the direct value of the sign bit. The remaining microcommands are in common with the microprogram of the addition. When doing arithmetic; the first and second microcommands for the left shift of the register, determined by the A2 field of the command (the number of binary bits to which the first operand is to be shifted), is transmitted from the buffer memory 7 through the arithmetic logic node and the battery of the operation unit to one of the registers of the register memory This operation unit 8. According to the third microcommand, the content determined by the command field A1 (shifted number) is transferred from the buffer memory 7 to the accumulator of block 8, the value of the sign of the number stored in trigger 10 (analogous to but add firmware). According to the fourth microcommand, the contents of the battery of block 8 through the arithmetic logic unit of block 8 is shifted one digit to the left, the value of the pushed bit (number sign) through multiplexer 17 is stored in the trigger included in block 3. In this field 6 microcommands there is a code determining that the output transfer signal of the block 8 is transmitted to the output of the multiplexer 17. The fifth, sixth, seventh microcodes are a cyclic part of the micro program. After this firmware is executed, we move to the fourth microcommand of the addition microprogram, according to which the result of the operation is written to the place of the first operand, the result sign is formed and written from the encoder 26 to the register 27. The overflow sign is generated if the trigger 12 is in single state scientific research institute, t, e. if in the course of the shift a mismatch of the nominated bit is revealed to the sign of the number. When executing long commands (for example, processing numbers with a w-point, processing fields of variable length, etc.), as well as commands that are not associated with the arithmetic-logical processing of operands (input-output, control commands), the result indicator is formed according to the result of the analysis of various conditions. In this case, triggers 10-12 or other means whose analysis can be connected to the input of microprogram control unit 3 via multiplexer 17. required by micro code. An indication of the result is recorded in register 27 of 6 microcommands through multiplex 18. Formula of the invention A microprocessor-based computing device containing a command register, a command decoder, a unit for generating microcommand addresses, a microinstruction memory, a microinstruction register, a clock generator, a buffer, and an operational memory block 5, where the information input of the command register is the input of the operation code of the device, the input of the record of the command register is connected to the output of the sign of the beginning of the command of the microinstruction register, the output of which This is connected to the read / write control input of the buffer memory, the address input of which is connected to the first output of the command register, the second output of which is connected to the input of the command decoder, the output of which is connected to the first information input of the microinstruction address generation unit, the information output of which is connected to the address the input of the microinstructions memory, the output of which is connected to the informational, the input of the register of microinstructions, the output of the micro-operation code of which is soy ;: inna with the input of the operation code of the operation unit, the information The input of which is connected to the information input of the buffer memory and is the information input of the device, the address output of the micro-command register is connected to the second information input of the micro-command address generation unit, the synchronization input of which is connected to the synchronization inputs of the operating unit and the micro-register and the first output of the clock generator, the start input of which is connected to the output of the sign of the start of the micro-command register operation, the output of the sign of the re, the address modification code formate, and the address microinstructions connected to the transfer input of the operating unit, the output of which is connected to the first control input of the modification of the address address maker of the microinstructions, informational outputs of the operational unit are informational outputs of the device, characterized in that it contains three triggers, a decoder, two multiplexer, two elements EXCLUSIVE OR, four elements AND, two elements NOT, two elements OR, a priority encoder and a register, and the information output is The first bit of the operational unit is connected to the first information input of the first multiplexer and to the first input of the first element of the TURN-ON SCHW, the second input of which is connected to the output of the first trigger, to the first input of the second element EXCLUSIVE OR, and to the second information input of the first multiplexer, the third information input of which is connected with the first input of the first SHS element and with the output of the second trigger, the counting input of which is connected to the output of the first And, the second and second inputs of which are connected respectively to the output of the first EXCLUSIVE SHS element and to the first output of the decoder, the second output of which is connected to the synchronization input of the first trigger, whose information input is connected to the output of the sign memory of the RAM, And, with the input of the first and second elements NOT, with the first input of the priority encoder and with the second input of the second element EXCLUSIVE OR, the output of which is connected to the first input of the third element AND, the second input D which is connected to the output of the third trigger and to the fourth information input of the first multiplexer, the output of which is connected to the second control input of the address modification of the microcommand address generator, the control input of the multiplexer is connected to the first output of the microoperations type of microoperations register of the micro instructions, the second output of the microoperation type of which is connected to the input of the decoder, the third output of which is connected to the second input of the second element And, the output of which is connected to the first input of the second element IL, the second th entrance which is connected to the output of the fourth element I, the first input of which is connected to the fourth output of the deshifter, the fifth output of which is connected to the input of the register entry, the information input of which is connected to the output of the second multiplexer, the control input of which is connected to the third output of the microomand register type microoperation, the fourth output of the sign, the type of a micro-operation of which is connected to the first information input of the second multiplex, the second information input of which is connected to the output of the encoder pr The priority of the second input is connected with the output of the first element NOT and with the second input of the fourth element AND, the third and fourth inputs of the priority encoder are connected. respectively with the output of the second element NOT and with the output of the first element OR, the second input of which is connected to the output of the third element AND, the output of the second element OR is connected with the synchronization input of the third trigger, the counting input of which is connected to the second output of the clock generator, the output of the register is the output of the sign bit of the device. Phage. 2 (Start on j CiioMfHUf Sign (A2) i 2Hk (A1) Sifnf n - mputtfpff Jww (At) AC-AC SI f (A)) trigger li - mpatieii ff TsChMK AC- (At) Zv Ia Soetuemfie nfusHOKa peiy / luna from CO siemi npuafumeme Z7 3V4 (, Sign (Al) - rnpuaeftl i four" CdSut AC left on I bit d Remember f trigger BMU value StiJiaiHOto transfer. ± C9Sut AC taeSo on t bit G 6MN ipefHufetaMat aopte c eiifomeu komanzn i tf Reading omanzy on p tatrp con and j I f End) P1 content check Cifue speakers on t bit d SfifaSo. Ifj trigger it Seeming on SfodcdSuta to the right the value of the sign of apomplete in the microcontrol