SU1513443A1 - Data processing device - Google Patents

Abstract

The invention relates to the field of computing and can be used to build floating point processors. The aim of the invention is to expand the field of application by performing the operation of calculating the reciprocal of the square root and using the bus structure. The device for processing data contains a block of general purpose registers 1, first 2 and second 7 multiplexers, multiplication unit 3, arithmetic logic unit 4 mantissa, first 5 and second 6 buffer registers, private correction unit 8, left unit search node 9, unit 10 shear, approximate dividing unit 11, approximate root calculation unit 12, arithmetic unit 13 pods, microprogram control unit 14 with corresponding links. 18 il.

Description

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multiplexers, multiplication unit 3, arithmetic logic unit 4 mantis, first 5 and second 6 buffer registers, correction unit 8 private, node of the left unit search., shift unit 10.

an approximate division unit 11, an approximate computation root unit, 13 arithmetic unit of 13 orders, a microprogram control unit 14 with corresponding lips. 18 pcs.

The invention relates to computing and can be used in the construction of floating-point arithmetic processors.

The aim of the invention is to expand the field of application by performing the operation of calculating the reciprocal of the square root and using the structure.

FIG. 1 is a diagram of the device for data processing; in fig. 2 is a block multiplication circuit; in fig. 3 is a diagram of the arithmetic logic unit mantis; in fig. 4 - diagrams of the unit for searching for the left units; figure 5 is a diagram of the shift unit; Fig "6 is a block diagram of the correction of the private; in fig. 7 is a diagram of an arithmetic order block; in fig. 8 is a diagram of a firmware control block; in fig. 9 is a diagram of a state registration node; in fig. 10 - the structure of the word. in fig. 11 - microcommand structure; in fig. 12 is a diagram of a subtraction operation algorithm; in fig. 13 is a diagram of an apori-tma addition operation; in fig. 14 is a diagram of the operation algorithm for the legs; in fig. 15-17 diagram of the division operation algorithm; in fig. 18 is a diagram of an algorithm for computing the inverse of the root.

The data processing device (FIG. 1) contains a general purpose register unit 1, a first multiplexer 2, a multiplication unit 3, an arithmetic logic unit 4 mantissa, a first 5 and a second 6 buffer registers, a second multiplexer 7, a private correction unit 8, - left unit search node 9, shift unit 10, approximate dividing unit 11, approximate calculation unit 12, arithmetically 13 order units, microprogram control unit 14, first to thirteenth control outputs 15-27, respectively, microprogram control unit 14 , from the first on the fifth inputs 28-32 of the conditions of the microprogram control unit 14, respectively, the first A 33 and second B 34 bi-directional information inputs of the device, the output 35 of the multiplexer 2, the first 36 and the second 37 information outputs of the left unit search node 9, the first information input 38 of block 10 the shift, the input 39 specifies the shift value of the shift block 10, the input 40 of the device start, the input 41 of the operation code of the device, the clock input 42 of the device, the output 43 of the device’s operation end, the informational code 44 arif1 1 of the logical unit 4 mantissa, ion yield 45 microprogram control unit 14.

The block diagrams of blocks and nodes in FIGS. 2-9 show dd cases of operands in two formats — 32 (24 bits of the mantissa, 8 bits of order and 64 (56 bits of the mantissa, 8 bits of order) of the discharge.

Block 1 of the general purpose registers is not intended for recording, storing and reading information (byte-byte or in multiples of a byte) on two bidirectional AZS and G34 inputs.

Multiplexer 2 has triplex outputs. The multiplication unit 3 (FIG. 2) contains multipliers (46-1) 446-7, the inputs of the first multipliers of which are connected to the input 34 of the device, and the inputs of the second multipliers - with the output 35 of multiplexer 2, the outputs of the old and low bits of the multipliers (46-1) - (46-7) are the corresponding outputs of multiplication unit 3, and the unlocking input is connected to output 18 of microprogram control unit 14.

The arithmetic logic unit 4 mantissa (Fig. 3) for bit 64 contains four adders 47-50, elements Ш1И 51-53, demultiplexer 54, multiplexer 55, elements OR 56, outputs 57 comparing operands of adders-subtractors , element OR 58, group of signal outputs

the arithmetic logic unit A man-time, consisting of carry out outputs 59, most significant bit 60, rounding bit 61, zero equality 62 top sixteen output bits 44 and equality of operands 63, group of inputs of setting 4 mantissa mode consisting of inputs 64 (single / double), format 65 (floating / fixed), operation 66 and transfer 67, and the inputs of the twenty-four star bits of the informational inputs 33 and 34 are connected respectively to the first and second information inputs total a -inverter 50, the next eight (by precedence) inputs of the bits of information inputs 33 and 34 are connected respectively to the first and second information inputs of the adder-subtractor 49, the lower eight inputs of the bits of information inputs 33 and 34 are connected respectively, to the first and second | information inputs of the adder-subtractor 47, the remaining inputs of the bits of information inputs 33 and 34 are connected respectively to the first and second information inputs of the adder-subtractor 48, transfer outputs of the totalizer-subtractors 47, 48 and 49connected to the first inputs of the elements OR 51 52 and 53, respectively, the second inputs of which are connected respectively to the first, second and third outputs of the multiplexer 54 whose fourth output is connected to the transfer input of the adder-subtractor 47, the outputs of the elements OR 51, 52 and 53 are connected with the inputs of the transfers, respectively, the sum of the subtractors 50, 49 and 48, the outputs 57 of the comparison operands are connected to the inputs of the element OR 58, the outputs of the adders-subtractors 47-50 are connected to the information output 44 of block 4, the older sixteen outputs of which th element connected to inputs or 56, inputs 64-67 grzshpy bloka- 4 connected respectively to the control inputs of the demultiplexer 54, multiplexer 55, summatorov- subtractors 47-50 mu and to information input demultiplexer 54,

 Buffer registers 5 and 6 have a write signal input and tristable outputs.

Multiplexer 7 has two information inputs and a tristable output.

0

five

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five

0

five

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five

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and executes a shift of 8 bits left or transmitting information without shifting.

Node 9 search left unit (figure 4) contains eight elements OR (68-1) - (), two priority encoders 69 and 70 and multiplexer 71, the first - the eighth inputs of the information input 33 of the device connected to the inputs of the first and eighth elements OR (68-1) - (68-8), the outputs of which are connected to the information inputs of the first priority encoder 69, whose outputs are connected to the fourth, right and mecTONry (senior) outputs of output bits 36 of node 9 and to the first information input - multiplexer 71, the sending and the second information inputs to Secondly, the enable inputs of the priority encoders 69 and 70 are connected respectively to the inputs of the input bits of the mode 9 setting, the output 37 of which is connected to the outputs of multiplexer 71, the signal outputs of the priority encoders 69 and 70 are respectively the outputs of 72 and 73 bits of the signal output node 9 (the signal at outputs 72 and 73 corresponds to the absence of a single bit.), the information outputs of the second priority encoder 70 are connected to the three lower outputs of output bits 36 of node 9, and the information inputs of the encoder 70 dinene output 35 multiplexer 2.

The shift unit 10 (FIG. 5) is intended to perform logical left and right shifts of 0-63 bits and contains five shifters 74-78. The first shifter 74 realizes the shift to O, 1, 2, 3 bits to the right, the second shifter .75 - to O, 4, 8, 12 bits to the right, the third shifter 76 - to O, 16, 32, 48 bits of the right-to-right. Inputs 38 and 33 are respectively the first and SECOND information inputs, the output of the third shifter 76 is the output of the shift block 10, the input 38 is connected to the information input of the fourth shifter 77, and the inputs of the three lower digits of the input 38 are connected to the additional inputs of the bits of the first shifter 74 the outputs of the bits of the latter are connected to the inputs of the bits of the second shifter 75, the additional inputs of the bits of which are connected to twelve each of the outputs

The spacing of the fourth shifter 77 outputs of the bits of the fifth shifter 78, the outputs of the bits of the second shifter 5 are connected to the inputs of the bits of the third shifter 76, forty-eight additional inputs of the bits of which are connected to the outputs of the bits of the fifth shift of 78,

In the case of a right shift JQ, its implementation is carried out on the 74j pen with the second 75 and the third 76 shear bodies. The operand arrives at the input | 3eformat input of the first shifter 74. The signal from output 16 enters the control inputs 15 of the third state of the fourth 77 and fifth 78 shifters and prohibits the transmission through them of information to the additional inputs of the second 75 and third shifters of the shifters. 20

The left shift is completed through the right shift; the number of right shifts is an addition to the 64 number of left shifts. The operand enters input 38, and input 33 enters a zero value of 25. The signal from output 16 is fed to the control inputs of the third state of the fourth 77 and fifth 78 shifters and allows information through them to be transmitted to the additional inputs of the bits 30 ss of the second 75 and third 76 shifts, respectively. The inputs of the lower two bits of the number of shifts (input 39) are connected to the control inputs with the number of shifts of the first 74 and fourth 77 shifters, the inputs of the next two bits of the number of shifts are connected to the control inputs of the number of shifts of the second .75 and fifth 78 shifters, the inputs of the older ones two bits of the number of jg shifts are connected to the control inputs of the number of shifts of the third shift 76

The unit 11 approximate division can implement any fast method, - approximate division, for example, tabular. To the address inputs of the tables, the inputs of the higher-order bits of the dividend and the divider are pushed, and the output of the block, under the control of the signal from output 25, sets the value of the approximate quotient.

The approximate computing unit root 12 can implement any fast method for determining the approximate value of a square root (or a reciprocal root value), for example, a tabular method. To the address inputs of the tables connects the input of the group of senior bits.

35

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the operand, and at the outputs, under the control of the signal from output 26, the approximate square root (or the inverse root value) is set.

The private correction unit 8 (FIG. 6) contains a reversible binary counter 79 with memory, the outputs of which are connected to the inputs of the demultiplexer formed by the decoder 80 and eight bus drivers (81-1) (81-8), the outputs of the decoder 80 are connected to the control the inputs of the corresponding shaper 81, the information inputs of which are connected to the outputs of the counter 79, and the outputs are the corresponding outputs of the bits of block 8, the counting input of the counter 79, the resolution input and the information input, the decoder 80 are the inputs of the corresponding the social bits of the input task set the block 8,

The 13th order arithmetic unit (Fig. 7) contains a general-purpose register 82, adders 83 and 84, and multiplexer 85, an order register 86, a comparison circuit 87, outputs OR 88, outputs 89-92 times ™ p The signal output of the arithmetic unit is 13 orders of magnitude, the inputs 93-97 of the bits of the input of the arithmetic unit are 13 times, the input 94 is connected to the control inputs of totalizers 83 and 84, the transfer output of totalizer 83 is connected to the first control input of multiplexer 85 and is output 89 of block 13, d input of register 86 and 96 unit 13 are respectively connected to data input and resolution circuit 87 comparing with a constant output the least significant bit and a second TRT: ravl. The input of multiplexer 85 is connected respectively to output 92 and input 95 of unit 13, the first information output of general purpose registers 82 is connected to the first information input of the first adder-subtractor l 83 and the second information input of the second with a calculator-calculator 84, information input unit 13 is connected to the second information input - the output of general purpose registers 82, with the second information input of the subtractor 83, with the first information input cr. the subtractor 84 and a register of 86 orders; the output of the subtractor 83 is connected directly to and from

five

ten

20

25

shifting right by one bit, respectively, with the first and second information inputs of multiplexer 85, the output of which is connected to the information input of the register of 86 orders, the output of the result of the adder-subtractor 84 is connected to the third information input of the multiplexer 85, outputs of equality of the bits of the two operands of the first adder - subtractor 83 is connected to the inputs of the element OR 88, the output of which is connected to the output 91 of the block 13, the output of the multiplexer 85 is connected to the information output of the block 13, | 5 the input of the register mode is of 86 order oedinen with input unit 97 13, with the constant output of the circuit 87 is a comparator 90 the output unit 13.

The microprogram control unit 14 (FIG. 8) contains the micro-command address register 98, the micro-command memory node 99, the micro-command register 100, the state registration node 101, the trigger 102, the outputs 103-105, respectively, of the first and second control fields and the end of the register 100 microinstructions, output 106 of the three lower bits of the register of microcommand addresses 98, output 107 of the state registration node 101, output 108 of the transition address of the node 99 microcommand memory, information input 109 of the microcommand register 100, output 110 of the control of the node 99 memory of microinstructions, register 111 com The outputs, 112-114, respectively, of the transfer micro-orders and the polarity of the sign, the third control field of the register of 100 microcommands, the node 115 of the memory of the comavd, and the input 41 of the operation code of the device are connected to the information inputs of the register 111, the reference input of which together with the trigger reset input .102 is connected to the input 40 of the device. The output of the register 111 is connected to the input of the node. 115 of the command memory, the output of which is connected to the first information input of the register 98, the second information input of which is connected to the output 108 of the node 99, and the control input connected to the output 110 of the node 99, the high-order outputs and the three lower-order bits of the register 98 are connected respectively, with the inputs of the higher bits of node 99 and

thirty

35

40

50

101, entry with corresponding

registers 98, 100 and node 28-32 bpock 14 are connected to the incoming inputs of node 101.

The state registration node 101 (FIG. 9) contains eight triggers (116-1) - (116-8), eight elements (117-1) - (117-8), output 118, regist

119, four multiplexers 120-123 of the elements of the EXECUTIVE ORE 124 and 125 are two bus manufacturers 126 and 127, the first inputs of the elements AND 117 are connected to the corresponding bits of outputs 104 of register 100, and the second to the clock input 42 of the device, the outputs And 117 elements are connected to the clock inputs of the corresponding trigger 116, whose information inputs are connected to the inputs

31 and 32, outputs 72, 61, 60, 59, and to the output 118 of element 125, the output of trigger 116-1 is connected to the fourths by the Multiplex information input

120, trigger output 116-2 — with the information input of multiplexer 12 and the first input of element 124; output of the third trigger 116-3 — with the sixth information input of multiplex 122; trigger output 116-4 with five information input of multiplexer 121; output trigger 116-5 — with twist and second information inputs of multiplexers 122 and 123, respectively; trigger output 116-6 with the fourth information input of multiplexer 121, trigger output 116–7 with the second and third information inputs of multiplexers 1 and 123, respectively , as well as with an inbound form input Operator 126 trigger output 116-8 is connected to V, the eye of the multiplex information input; copy 121, inputs 62, 73, 89, 90, 91 and 92 are connected to the fifth, second, third, fourth fifth and sixth information inputs of the register, respectively. , the clock input of which is connected to the clock input 42 of the device, the first output (output of the first bit) of register 119 is connected to the third information input of the typelexer 120, the second output to third information input of multiplex 122, the third output to the second and

the input of the node 101, the outputs 107 of the node 101 of the co-formation multiplexer input

united with the inputs of the three lower bits of node 99, the output of which is connected by the input 109 of the register 100, the input 42 of the device is connected to the clock inputs

120, the fourth output - to the fifth volume information input of the multiplexer; the 12th fifth output - to the third information input of the multiplexer 121, and

five

ten

0

five

five

.

thirty

five

0

0

101, inputs with corresponding

registers 98, 100 and node 28-32 bpock 14 are connected to the incoming inputs of node 101.

The state registration node 101 (FIG. 9) contains eight triggers (116-1) - (116-8), eight elements AND (117-1) - (117-8), output 118, register

119, four multiplexers 120-123, elements of TORMS OF OPERATIONS OR 124 and 125, two imagers of buses 126 and 127, with the first inputs of the And 117 elements connected to the corresponding bits of the outputs 104 of the register 100, and the second to the clock input 42 of the device, the outputs of the elements And 117 is connected to the clock inputs of the corresponding triggers 116, whose information inputs are connected to the inputs

31 and 32, outputs 72, 61, 60, 59 and 63 and to output 118 of element 125, the output of trigger 116-1 is connected to the fourth information input of the Multiplexer

120, trigger output 116-2 - with information input of multiplexer 121 and first input of element 124, output of third trigger 116-3 - with sixth information input of multiplexer 122, trigger output 116-4 - with fifth information input of multiplexer 121, trigger output 116 -5 - with the fourth and second information inputs of multiplexers 122 and 123 respectively, the output of the trigger 116-6 with the fourth information input of the multiplexer 121, the output of the trigger 116-7 with the second and third information inputs of the multiplexers 122 and 123, respectively the input of the driver 126, the output of the trigger 116-8 is connected to the second; red information input of the multiplex; a copy 121, the inputs 62, 73, 89, 90, 91 and 92 are connected respectively to the first, second, third, fourth, fifth and sixth information inputs of the register 119, the clock input of which is connected to the clock input 42 of the device, the first output (output of the first bit) of register 119 is connected to the third information input of multiplexer 120, the second output to the third information input of multiplexer 122, the third output to the second information input mu tipleksora

120, the fourth output - to the fifth information input of multiplexer 122, the fifth output - to the third information input of multiplexer 121, and the neck -.

1513443 2

oh output - to the seventh information-field 27 with the following signs: 93 - to the control input of the multiplexer 122, the first register register 82; 94 - control information inputs of multiplexers with subtractors 83 and 84; 120-122 are connected to the outputs of bits 95 - control of multiplexer 85; output 106, and their control inputs - control circuit 87; 97 - with outputs of output bits 103, control register 86; the fields of the multiplexers 120-122 are connected with the control of the multiplexers 120, 121 to the outputs 107, the first information 122; field 104 — the mask field is the element-input of the multiplexer 123 connected to output | 117 and 117; a micro-order field 105 with stroke 113, which fills the inputs of the device's connection-operation; field 108 — fields with output 114, and the output of the next microcommand connection; the field to the input 67, the second inputs of the elements 110 are the control fields of the register 98; 124, the formers 126 and 127 of the connection field 112 are the control fields of the element with the outputs of the corresponding bits of the arrays 124, 126 and 127; field 113 — signal output 112, output of the transfer input connection element 124 for block 4; So to the first in: {the shaper 114 oduler is the control field of the multi- 127, the output of which is connected to the information plexor 123.

4.5 output gate of block 14, output All operands for any operation

driver bus 126 is connected to input-20 stores in the general assignment registers 38 of the shift block 10. either: signs and mantissas in the block, then the word state (Fig. 10) contains in register 82 of the block 13. The following field indications, configure the device ( Fig. 1) works with the corresponding inputs in the following way.

For floor 59 - output 25 is output to the input 41 of the device

nose; 60 is the high-order output; the operation code, which, under control 61, is the output of the round-off bit; The signal at input 40 (the signal for the input of the zero high word; 40 simultaneously resets the triggered sign of equality of the mantissier bit 102) is entered in the register 111 coDl field 72 - a sign of zero. Operation code on the outputs of this

your operand; 73 - the null-register sign determines the node address 115,

byte. The content of the corresponding memory cell of which is the initial address of the field 89 — the output of the microprogram pa- ratory. Initial address

sa; 90 is a sign of comparison; 91 - microcommands under clock control

sign of equality of order; 92 signals from input 42 and a signal from the output of the lowest bit of the result. yes 110 is written to register 98. Three

For one-bit fields: 31-low bits from register outputs 98

sign of the first operand; 32 —signs through multiplexers 120,

second operand; 118 - the result of Q121 and 122, respectively, to address

adding modulo two characters opera-inputs of the lower bits of the memory node 99

Dov. microinstructions, the most important remote commands (Fig. 11) consist of the codes of the most important fields: control field 15 of the registers of the register 98. After time, determined by multiplexer 2; floor 16 controlled by the read time of node 99, on either block 10; control field 17 second information inputs of the register unit 1; The control block-98 control field 18 arrives at the next micro- address. room 3; field 19 with signs: 64-commands from the output 108 of the node 99, Under control, the accuracy of the operand (single / double); output of the signal from the output 107, the field уп 65 — the format of the operand (fixed JQ equal signals from the outputs of the node 99 / floating); 66 — Sum-write control in register 100 by microcommitters 47–50; 67-Mand, and the address of the next microcommand is the transfer input; control field 20 in register 98. Control signals with register 5; output control field 21 of register 100 is implemented by mass register 6; control field 22 via the multiplexer 7; the floor 23 of the control signs of the conditions of the inputs 31, 32 and 118 of laziness by block 8; control field 24 in triggers 116. The remaining signs are node 9; The block condition control field 25 in each clock cycle is written 11j in the control block field 26; into the register 119. The outputs of the latter and

the flip-flops 116 are connected to the information inputs of the multiplexers 120- 122, the control inputs of which, defined by the outputs 103 of the register 100, allow branching in the microprogram according to three signs of conditions at the same time. The microinstruction corresponding to the end of the microprogram sets the trigger 102 to one with the help of a signal from the output t05, and the output 43 signals the end of the current microprogram and the readiness to execute the next command.

The device in the process of various arithmetic operations works as follows.

The microprogram of the subtraction operation is presented in FIG. 12 and contains micro-commands (MK) 128-152.

MK 128. From the registers, the mantissas of the X and Y operands are counted to the inputs of the AZZ and G34, respectively. The Yanaki 31 of the first X and 32 of the second Y operands and the result of 118 modulo two characters on the element 125 under the control of the enabling signals 104 through the elements 117 are fixed in the corresponding triggers 116 of the node 101 of the block 14. In block 13 the sign 89 controls the selection of the information input of the multiplexer 85 and under the control of micro-order 97 field 27, the result from the outputs of the multiplexer 85 is written to register 86. The result from the outputs of the multiplexer 85 also goes to the first inputs of the circuit 87, where

MK 132. Managed by floor 93

is compared with a constant and a sign is formed greater than 90, which is fixed from register 82, the constant is calculated, ruled in the corresponding trigger 116 is equal to one, which from the output of multiplexer 85 comes from the outputs 39 of block 13 to the inputs of the number of shifts of block 10. Under the poisoning field 20 The content of the buffer register 5 is fed to the input of the PSA to the information inputs of block 10, where the shift to the right is performed (under control of field 16), and the result from the outputs of block 10 by the input of micro orders of fields 20 and 21, jg do B34 is written in block 1 by address tive triggers 116 fixed result mantissa. Analysis of signs of transfer 59, 60

node 101 of block 14. In the case of equality of orders, the OR element 88 forms the sign 91, which is fixed, in the corresponding trigger 116. In block 4 (under the micro-instructions control of field 19), the difference of operands (X - Y) is calculated, which is written into the buffer registers 5 and 6 under control signs 59 and if 00, then transition to MK 133; if 10, then go to MK 136; if 11, then go to MK 135.

values of most significant bit. and 63 equality operands. Transition to -MK 129.

MK 129. Analysis of the conditions formed by the pre-previous microcommand 89, 91 and if 000, then the transition to MK 130; if 100, then the transition to MK

143; if 010, then go to MK 150; if ХХ1, then the transition to Ж 142 (X is an idleness-free state).

MK 130, From the block, counts the input to the ADF operand Y. In block 10, the operand Y is shifted to the right | by the number of bits defined by the 1st register 86, which from the outputs 36 of the register 86 through the adder 83 and the multiplexer 85 comes from you-. moves 39 block 13 in block 10 to the inputs of the number of shifts. The result of the shifted operand Y on the input of B34 is recorded under the control of floor 17 into one of the registers of the register group of block 1. The sign analysis completes if O, then go to MK 137; if 1, then the transition to MK 131.

MK 131. The mantissa of the operand X and the de-normalized mantissa of the operand Y are calculated (controlled by floor 17) from block 1 by the inputs of the APS and B34, respectively, and are fed to the inputs of block 4. The result of the sum from the outputs of block 4 (controlled by floor 19) is written to register 5 (running floor 20). The order of the operand X (controlled by floor 93) comes from register 82 to adders 83 and 84 of block 13, where it is increased by one (controlled by floor 94), the result is recorded through multiplexer 85 to register 86 (controlled by floor 97). The signs of transfer 59 of block 4 and 89 of block 13 are fixed in the corresponding triggers 116 of node 101 of block 14. Transition to MK 132 "

MK 132. Managed by floor 93

From register 82, the constant is calculated to be equal to one, which from the output of multiplexer 85 comes from the outputs 39 of block 13 to the inputs of the number of shifts of block 10. Under the poisoning of the field 20, the content of the buffer register 5 goes to the input of the AZZ to the information inputs of block 10, where the shift to the right is performed (under the control of field 16), and the result from the outputs of block 10 to input B34 is written to block 1 at the address of the resulting mantissa. Analysis

dd from register 82 is calculated the constant is equal to one, which from the output of the multiplexer 85 comes from the outputs 39 of the block 13 to the inputs of the number of shifts of the block 10. Under the poisoning, the field 20 containing 45 of the buffer register 5 goes to the input of the ABZ to the information inputs of the block 10, where the shift to the right is performed (under the control of field 16), and the result from the outputs of block 10 to input jg dB34 is written to block 1 at the address of the resulting mantissa. Analysis

55

signs 59 and if 00, then transition to MK 133; if 10, then go to MK 136; if 11, then go to MK 135.

MK 133. Under control of floor 20, the contents of buffer register 5 at the input of the ADF are recorded in block 1 (under control of floor 17) at the address of the resultant mantissa. Under the control of field 93, the order of operand X is written to the address of the resulting order in register 82 of block 13. The transition to MK 134.

MK 134. Under the control of field 112 from output 45 of generator 127 of node 101 of block 14, the sign value of operand X according to the corresponding bits of the input of the ADF record is written into the bits of the sign of the result register of block 1 (under control of floor 17). Set the trigger 102 block 14 in the unit. The end of the operation.

MK 135. In block 1 (under control of floor 17) and in register, 8 of block 13 (under control of floor 93), the units in all bits, i.e., are written to the addresses of the resulting mantissa and the resulting order. the maximum result value is recorded. Transition to MK 134.

MK 136. It is executed similarly to MK 134. Additionally, the order of the operand X is written to the register 82 of block 13 at the address of the resulting order (under the control of field 93).

MK 137. Under field 17 of block 1, the inputs of AZZ and B34, respectively, of the mantissa of the operand X. and the denormalized mantissa of the operand Y are read out. In block 4 (under the control of field 19), the mantis of the operand X and the denormalized mantissa of Y , the result under the control of fields 20 and 211 is written to buffer registers 5 and 6. Sign 60 d of block 28 outputs

45

4 is fixed in the corresponding triggered field 27 of the contents of register 86 of the state 116 of node 101 of block 14. Under control, field 93 in block 13 of operand X is recorded at the address of the resulting order in register 82. The transition to MC 138.

MK 138. Under the control of floor 20, the contents of register 5 at the input of the APS are fed to the first information inputs of node 9, where, under the control of floor 24, a binary code of the number of the left nonzero bit is formed at the outputs 36 j. In block 13, this code is written in one of the registers 82, and in adder 84 (under control; field 94) the complement to

64, the result through a multiplexer

85 is written to register 86. Sign.

72 from the outputs 29 of the node 9 is fixed

in register 119 of node 101 of block 14. It is recorded at the address of the output address of the register in register 82. The analysis of the sign is fulfilled if O, then the transition to MK 134; if 1, then go to MK 142. MK 142. Under control of floor 17, block 1 and register 82 of block 13 (by control of floor 27) write the mantissa, the sign and order of the result equal to zero to the result address. Installation in unit trigger 102 block 14, End operashchi.

MK 143 o It is performed similarly to MK 130o The difference is that the mantissa of the first operand X is received at the input of the AZZ from block 1. The analysis of the sign is canceled if O then the transition to MK 147; if 1, then the transition to MK 144o

Complete analysis of condition 60, fixed in MK 137: if O, then go to MK 139; if 1, then go to MK 134.

, MK 139. Under control of floor 21, the contents of buffer register 6 from the outputs go to the information inputs 38 of the shifter 77 and the additional inputs of the shifter 74 of the block 10. No information is received at the information inputs of the shifter 74 connected to the output of the APS, which corresponds to the zero operand ). The inputs 39 of block 10 from the outputs of the multiplayer 85 block 13 receives the code of the number of shifts to the right. Under field 16, block 10 performs a right-shift operation by the number of bits, which complements up to 64 left-shifts, and the result on input B34 is written (under field 17 control) into block 1 at the address of the resulting mantissa. Signs 72 formed in MK 138 are analyzed: if O, then go to MK 140; if 1, then go to MK 142.

MK 140. In block 113, under control of field 27, the order register and the binary code of the left nonzero bit of the result mantissa to the corresponding inputs of the adder-subtractor 83 are read out from the register 82, the difference from the outputs of the latter is written to the register 86. The transfer characteristic 89 of the adder 83 is fixed in corresponding trigger 116 of node 101 of block 14. Transition to MK 141.

MK 141. In block 13 under control

I eat floor 27 the contents of register 86

is written to the address of the pry dya result in the register 82. The analysis of the sign is completed if O, then the transition to MK 134; if 1, then go to MK 142. MK 142. Under control of floor 17, block 1 and register 82 of block 13 (under control of floor 27) write the mantissa, the sign and order of the result equal to zero to the result address. Installation in the trigger unit 102 block 14, End of the opera.

MK 143 o It is performed similarly to MK 130o The difference is that the mantissa of the first operand X is received at the input of the AZZ from block 1. The analysis of the sign is cleared if O, then the transition to MK 147; if 1, then the transition to MK 144o

17

MK 144. It is executed similarly to MK 131. The difference is that the mantissa of the secondary operand Y is read into the input of the AZZ from block 1, and to the inputs of adders-subtractors 83 and 84 it reads from the register 82 of block 13, from the order of the second operand Y. Transition to MK 145.

MK 145. The process is similar to MK 132. Analysis of signs 59 and 89 formed in MK 144: if 00, then go to MK 152; if 10, then go to MK 146; if 11, then go to MK 135.

MK 146. It is performed similarly to MK 136. The difference is that at the address of the result order in register 82 of block 13, the order of the second operand Y is written.

MK 147. Under the control of floor 17 from block 1, the mantissa of the second operand Y and the denormalized mantissa of operand X, respectively, are read into the inputs of the AZZ and B34. Under the control of field 19 in block 4, the difference of these codes is calculated and the result is written to the buffer registers 5 and 6 (under the control of fields 20 and 21). Transition to MK 148.

MK 148. The process is similar to MK 138о. Analysis of feature 60 obtained in MK 147: if O, then go to MK 149; if 1, then the transition to MK-139

MK 149. Under the control of field 112, the inverse value of the sign of the operand X from the output 45 of the bus imager 127 y - la 101 of block 14 at the input of the ABP is written to the bits of the sign of the result of the register of block 1 (directed by floor 17). Installation in unit trigger 102 of block 14. End of operation,

MK 150 Under the control of field 17 of the mantissa of the first operand X is recorded at the address of the mantissa of the result in block 1. Under control of the field of 27, the order of the first operand X is recorded at the address of the result in the register 82 of block 13, analysis of signs 118, 89 and 63, formed in MK 128: if 000, then go to MK 133; If 100, then go to MK 144; if 110, then go to MK 147; if 010, then go to MK 151; if 101, then go to MK 142 „

MK 151 o Under the control of floor 17 from block 1, the mantissas of the second Y and first X are read on the AZZ and B34 tires

-

1513443 8

operands respectively. Under the control of field 19 in block 4 is calculated

the mantis difference to the result is written into the buffer registers 5 and 6 (under the control of fields 20 and 21). Transition to MK 148 o

MK 152, Under control of floor 20, the contents of register 5 at the input of the APS are recorded at the address of the result mantissa in block 1 o. Under control of floor 27, the order of the second operand Y is recorded at the address of the result in register 82 of block 13, Transition to MK 134.

five

0

five

0

five

. The microprogram of the add operation is shown in FIG. 13, and contains micro-instructions 153-185.

0 MK 153o Complete the same way as MK 128o Transition to MK 154.

MK 154. It is fulfilled similarly to MK 129. Analysis of signs 89, 91 and 90. formed in MK 153: if - 5 or 000, then transition to MK 155; if 100, then go to MK 168; if 010, then go to MK 176; if XX1, then go to MK 167.,

MK 155. Execution is similar to 0 MK 130. Analysis of feature 118 formed in MK 153: if O, then go to MK 156; if 1, then go to MK 162 o

MK 156. Is similar to MK 131, Transition to MK 157,

MK 157 ,, is similar to MK 132o Analysis of signs 59 and 89 formed in MK 156: if 00, then go to MK 158; if 10, then go to MK 161; if XI, then the transition to the MK 160,

MK 158. It is fulfilled similarly to MK 133. The transition to MK 159.

MK 159. Executes similarly to MK 134. End of operation.

MK 160. Included is the same as MK 135, Transition to MK 159.

MK 161, similar to MK 136 ,, End of operation,

MK 162 is similar to MK 137 ,, Transition to MK 163.

MK 163o is similar to the MK. 138о Analysis of feature 60 formed in MK 162: if O, then go to MK 164; if 1, then go to MK 159,

MK 164, is fulfilled similarly to MK 139, Analysis of the sign 72 formed in MK 163: if O, then re

move to MK 165; if 1, then the transition MK 167.

MK 165 is implemented similarly to MK lAOo. Transition to MK 166.

MK 166. The process is similar to MK 141. Analysis of the characteristic 89 formed in MK 165: if O, then go to MK 159; if 1, then the transition to MK 167o

MK 167. Performed similarly to MK 142o. End of operation

MK 168o Carried out similarly to MK 143. Analysis of the sign 118 formed in MK 153: if O, then go to MK 169; if 1, then go to MK 173 „

MK 169 is fully similar to MK 144. The transition to MK 170.

MK 170o is similar to MK 145, Analysis of signs 59 and 89, formed in MK 169: if 00, then go to MK 172; if 10, then go to MK 171; if X1, then go to MK 159s

MK 171. Performed similarly to MK 146. End of operation.

MK 172. Same as MK 152. End of operation.

MK 173. Under the control of field 17 of block 1, the mantissa of the second operand Y and the denormalized mantissa of operand X, respectively, are read into the inputs of the AZZ and B34. Under the control of field 19 in block 4, the difference is calculated and the result is written to buffer registers 5 and 6 (under the control of micro-orders of fields 20 and 21). Transition to MK 174.

MK 174, is complete similarly to MK 148o. Analysis of feature 60 formed in MK 173: if O, then go to MK 164; if 1, then the transition to MK .175o

MK 175. Similar to MK 149 End of operation.

MK 176o Under the control of field 27, the order of the first operand X is recorded at the address of the order of the result in register 82 block 13. Analysis of signs 118, 89 and 63, c4 timed in MK 153: if OXX, then go to MK 177; if 100, then go to MK 179; if 101 then go to

By controlling the field, block 4 calculates the sum of the mantis and the result is written to register 5 (under the micro-order control of field 20). Under the control of field 27, the order of operand X in block 13 is increased by

ten

15

20

25

unit and recorded in register 86, Transition to MK 178.i

MK 178. It is fulfilled similarly to MK 132. Analysis of feature 89 formed in MK 177: if O, then go to MK 158; if 1, then the transition to the MK 160.

MK 179o In general is similar to MK 133 except that the transition to the next MK is performed by analyzing feature 60 formed in MK 153: if O, then go to MK 163; if 1, then go to MK 159.

MK-180o Under the control of floor 17 from block 1, the mantissas of the second Y and first X operands, respectively, are read into the inputs of the AZZ and B34. Under the control of field 19 in block 4, the difference of the mantis is calculated and the result is written to the buffer registers 5 and 6 (under the control of fields 20 and 21). 30 Transition to MK 181.

MK 181, Under the control of micro orders, field 20, the contents of buffer register 5 is transmitted to the input of the ABP and then recorded at the address of the result mantissa in block 1 under the compression of field 17 .. The analysis of sign 60 formed in U 180 is refined: O, then the transition to MK 182; if 1, then go to MK 175.

MK 182. In general, it is similar to MK 128, except that analysis of feature 60 does not perform with and the transition to MK 183 is made.

MK 183. It is fulfilled similarly to MK 139. The transition to MK 184.

MK 184o It is performed similarly to MK 140. The transition to MK 185.

MK 185 o Is executed in the same way as MK 141. Analysis of feature 89 formed in MK 184: if O, then go to MK 175; if 1, then go to MK 167 „

A block diagram of the execution of the operation of multiplying floating-point numbers

35

45

MK 172; if 110, then the transition to MK 180. 55 single precision (p 32) is represented by 177. Under control of floor 17 from block 1, the mantissas of the first X and second Y operands are combined at the inputs of the ADF and B34. Under

Lena in FIG. 14 and contains micro-commands MK 186-203.

MK 186. From block 1 under the control of floor 17 to the inputs of the AZZ and B34 counts,

51344320

By controlling the field, block 4 calculates the sum of the mantis and the result is written to register 5 (under the micro-order control of field 20). Under the control of field 27, the order of operand X in block 13 is increased by

ten

15

20

25

unit and recorded in register 86, Transition to MK 178.i

MK 178. It is fulfilled similarly to MK 132. Analysis of feature 89 formed in MK 177: if O, then go to MK 158; if 1, then the transition to the MK 160.

MK 179o In general is similar to MK 133 except that the transition to the next MK is performed by analyzing feature 60 formed in MK 153: if O, then go to MK 163; if 1, then go to MK 159.

MK-180o Under the control of floor 17 from block 1, the mantissas of the second Y and first X operands, respectively, are read into the inputs of the AZZ and B34. Under the control of floor 19 in block 4, computations -. The difference is the mantis and the result is written to the buffer registers 5 and 6 (under the control of fields 20 and 21). 30 Transition to MK 181.

MK 181, Under the control of micro orders, field 20, the contents of buffer register 5 is transmitted to the input of the ABP and then recorded at the address of the result mantissa in block 1 under the compression of field 17 .. The analysis of sign 60 formed in U 180 is refined: O, then the transition to MK 182; if 1, then go to MK 175.

MC 182. In general, it is performed in the same way as MC 128, except that the analysis of feature 60 is not performed and the transition is made to MC 183.

MK 183. It is fulfilled similarly to MK 139. The transition to MK 184.

MK 184o It is performed similarly to MK 140. The transition to MK 185.

MK 185 o Is executed in the same way as MK 141. Analysis of feature 89 formed in MK 184: if O, then go to MK 175; if 1, then go to MK 167 „

A block diagram of the execution of the operation of multiplying floating-point numbers

35

45

single precision (p 32)

Lena in FIG. 14 and contains micro-commands MK 186-203.

MK 186. From block 1 under the control of floor 17, the mantissa operands Y and X, respectively, are read into the inputs of the AZZ and B34. The mantissa of the operand X is recorded from the inputs of the multiplicand in block 3 under control of floor 18.. The lower (third) byte of the mantissa of the operand Y is transmitted to the inputs 35 of the multiplexer 2 (controlled by micro orders of fields 15 and 24), fed to the inputs of the multiplier of block 3 and under control of floor 18 is written into block 3 0 Under control of floor 27 and block 13 from register 82 - the sum of the orders is calculated from the order of the X and Y operands and in the adders 83 and 84. The result from the outputs of multiplexer 85 is written to register 86. Output 89 of transfer of adder 83 is fixed in the corresponding trigger.

15 seven doses to the right. The shifted result from the outputs of the block 10 is brought to the entrance of the B34 through the block 4 in the regis. Simultaneously with this, in the block 3 under the control of the field 18 is performed

116 node 101 block 14. In another trig-20 multiplication. Analysis is performed

Gere 116 fixes the result of 118 modulo two characters 31 of the first X and 32 second Y operands. In block 3, the multiplication is completed. Transition to MK 187.

MK 187o Under the control of floor 18 from the outputs of block 3, the inputs of AZZ and B34 are combined respectively the word of the senior and the word of the lower bits of the products calculated in the corresponding multipliers 46 of block 3. These two words are fed to the inputs of block 4, where under the control of the floor 19, their sum is computed, i.e. the product of the mantissa of the operand X to the low byte of the mantissa of the operand Y. The result from the outputs of block 4 is recorded in register B under the control of pr 20. The analysis of the sign 89 is performed. formed in MK 186: if O, then go to MK 188; if 1, then transition kMK203 ..

MK 188. Under the control of field 17 from block 1, the mantissa of the second operand Y is counted at the input of the ADF. Under the control of micro orders of fields 24 and 15, the second byte of the mantissa Y is transmitted through multiplexer 2 to its outputs and recorded from the inputs of the multiplier in block 3 (controlled by field 18) o The multiplication is performed in block 3. Simultaneously, in node 9 under the control of field 24, the output 73 of the priority encoder 70 forms a sign of the zero byte and is fixed in the corresponding register bit 119 of node 101 of block 14. Under control field 27 in the block 13 contents register 86 is recorded

25

thirty

sign 73, formed in

MK 188: if O, then go to MK 1

if 1, then go to MK 200 ..

MK 190. It is performed in general, but MK 187, except that the analysis of feature 89 is performed, and the result from outputs 44 of block 4 is recorded in register 6.

MK 191. Under the rule of field 18 in cabinet 4, the contents of registers 5 and 6 are summed up (under the control of Microcritical fields of fields 20, the result from outputs 44 of block 4 by direction of field 20 is recorded by a gist of 5 g. Transition to MK 192. MK 192. It is performed Generally speaking, the MK 188 is different. The difference is that the multiplier in block 3 is written from the output 35 of the multiplayer 2 startmey byte operand Y, read from the AZP input from block 1, in block 13 the transfer of the register 86 to the register 82 Transition to MK 193

MK 193, is similar to Analysis of feature 73 formed in MK 192: if O, then go to MK if 1, then go to MK 201.

MK 194 is about 1n similar to 5 ° MK 190. Go to MK 195.

MK 195o Under the control of fields 20, 21 and 22, the contents of the buffer registers 5 and 6 are fed to; the inputs of the LPZ and B34, respectively. With the power of the control field 19 in bl; 4, addition is completed. V Under the control of field 27 in block 13, a reduction of the order of the result and recording

35

40

45

55

to register 82 at the address of the result of the transition to MK 189.

MK 189. A register is read from register 82 (eight is the number of shifts not bytes) and through the adder 83 and multiplexer 85 is transmitted to the outputs 39 of block 13. Under floor 20 control, the contents of buffer register 5 through

the input of the APS arrives at the second information inputs of the block 10, where, under the control of the micro orders of the field 16 and the code at its inputs 39, the partial product shifts by eight times the dose to the right. The shifted result from the outputs of block 10 is entered at input B34 through block 4 into the register. Simultaneously with this, in block 3 under the control of the field 18 is performed

multiplication Analysis is performed

five

0

sign 73, formed in

MK 188: if O, then go to MK 190;

if 1, then go to MK 200 ..

MK 190. It is performed as a whole in the same way as MK 187, except that the analysis of feature 89 is not performed, and the result from outputs 44 of block 4 is written to register 6. The transition to W 191.

MK 191. Under unit 18 of block 4, block 4 performs the summation of the contents of registers 5 and 6 (under the control of Microcritical fields 20,). The result from outputs 44 of block 4 under control of field 20 is recorded in register 5 g. Transition to MK 192. MK 192. This is generally the same as MK 188. The difference is that the multiplier in block 3 is recorded from the output 35 of the multiplexer 2 old byte operand Y, read from the input of the ADF from block 1 In addition, in block 13, the contents of register 86 are not transferred to register 82. The transition to MK 193,

MK 193, is similar to MK 189. Analysis of the sign 73 formed in MK 192: if O, then go to MK 194: if 1, then go to MK 201.

MK 194 is about the same as MK 190. The transition to MK 195.

MK 195o Under the control of fields 20, 21 and 22, the contents of buffer registers 5 and 6 are fed to; the inputs of the LPZ and B34, respectively. Using the control field 19 in the block; 4, addition is completed. V Under control of field 27 in block 13, the reduction by one order of the result is fulfilled and its recording

five

0

five

five

to register 86. Signs 60, 61 and sign 89 of the transfer output of the adder 83 are fixed in the corresponding triggers 116 of node 101 of block 14. The transition to MK 196..

Under the control of field 21, the register 6 is fed to the first information inputs 38 of block 10, in which the field 16 controls the shift one bit to the left. The result from outputs 10 to input B34 through block 4 is written to. register 6. The analysis of signs 60 and 89 formed in MK 195 is complete: if 00, then go to MK 198; if 10, then go to MK 197; if XI, then go to MK 202.

MK 197o Under control of floor 20, the contents of register 5 at the input of the ADF are posted to the first inputs of block 4, to the transfer input 67 of which comes from the output of multiplexer 123 of node 101 of block 14. sign 61 value generated in MK 195. The result from block 4 is written below control floor 20 in the register 5.. Transition to MK 199o

MK 198 o Under the control of field 21, the contents of register 6 at input B34 are posted to the second inputs of block 4, to input 67 of which transfer comes from the output of multiplexer 123 of node 101 of block 14, the value of attribute 61 formed in MK 195. The result from block 4 is written - running floor 20 into register 5. Under control floor 27 in block 13, the contents of register 86 are written to the address order of the result in register 82. The transition to MK 199.

MK 199, Under control, the field containing the register 5 is sent to the AZZ input through block 10 (with a shift of eight bits to the right) to. the input B34 and then is recorded using the control field 17 at the address of the mantissa of the result in block 1; Installation in block 10 of trigger 14. Block 14. End of operation.

MK 200. Under control of floor 20, the contents of register 5 at the entrance of the ADF are transferred through block 10 (shifted eight bits to the right) to the input of B34, then through block 4 are sent to the inputs of register 5 and written to it. Transition to MK 192.

MK 201. It is realized similarly to MK 200. The difference is that

from the outputs of block 4, the result, except for register 5., is recorded in register 6 (under control of floor 21). Signs. 60 and 61 are fixed in the corresponding triggers 116 of node 101 of block 14. Under floor control, the order of the result in block 13 is reduced by one, and the result is written

in the register 86. The transition to the MK 196.

MK 202. Under the control of fields 17 and 27, the addresses of the mantissa and the order of the result, respectively, in block 1 and register 82 of block 13 are written to zero values of the operands. The trigger 102 of unit 14 is set to one. The end of the operation.

MK 203. Under the control of fields 17 and 27 at the addresses of the mantissa and order

the result, respectively, in block 1 and register 82 of block 13, the values of the units in all bits are recorded. Setting the trigger 102 block 14 in the unit. The end of the operation.

The block diagram of the algorithm for dividing single-precision numbers is presented in FIGS. 15-17 and contains micro-commands MK 204-289.

MK 204o Running floor 17

the mantissas of the X and YO operands of the Mantissa of the operand Y are output from the output of the B34 to the inputs of the multiplicand and written to block 3, and also to the second information inputs of block 4, under the control of floor 19 in block 4 of voln The calculation of the difference in the mantissa, in the corresponding triggers 116 of the node of the block 14, the signs 59 of the transfer and 63 comparisons are fixed. Groups of higher bits of operand X and operand Y are fed to the inputs of block 11, under control of field 25 in this block 11, a test quotient is counted (eight bits) and then recorded (under control of field 23) into block 8 and from the multiplier inputs under the control of field 18) in block 3, Under the control of field 27, block 13 calculates the difference of the order (HRV-PU) and the result is written to register 86. In accordance with the corresponding triggers 116 of node 101 of block 14, signs 89 are fixed

and 118 Transition to MK 205.

MK 205 Under control of field .18 b, block 3 completes the multiplication of the mantissa of the divider Y by the trial quotient. Running floor 17 out

block 1 to the input of the ADF is mapped the mantissa Y, which through block 10 (under the control of field 16) is shifted by eight bits to the right (using up: equal to the two inputs 39) is transmitted to the input B34 and then recorded at the first address one of the registers of block 1. From the outputs 29 of the node 9 in the corresponding trigger 116 of the node 101 of the block Q 14, the sign 72 is fixed - the zero operand. Signs 63, 59, and 89 formed in MK 204 are analyzed: if XOO, then go to MK 206; if X01, then go to MK 209j 15 if 010, then go to MK 211; if 110, then go to MK 282; if 011, then go to MK 284; if 111, then go to MK 285.

U 206 o Under the control of field 17. 20 from block 1, the mantissa, operand X is transmitted from block 1, poured through block 10 with a shift by one bit to the right (controlled by the code on inputs 39) and input B34 is written 25 at the second address into the block 1. Performs an analysis of the characteristic 72, formed in MK 205; if O, then go to MK 289; if 1, then go to NC 207.

MK 207. Under the control of floor 27 jg in block 13, the contents of register 86 are incremented by one and in the corresponding trigger 116 of node 101 of block 14, sign 89 is fixed. Under control of floor 17 of block 1, the contents of the register with the second register are read from block 1 from block 1 to block 13. the address and the mascissa divider Y. The starters of the bits of the AZZ and B34 inputs go to the inputs of block 11, from the outputs of which (under control of floor 25) the robust quotient is sent and under control of floor 23, the block 8 is written, and also as multiply into block For Transition to MK 208,:,

MK 208o Under control of field 18, block 3 is completed. multiplication of factors Under control of field 17, the register of block 1 with the BTOpbiM address is written to jg the address of the operand. The analysis of the sign 89 formed in (K 207: if O, then go to MK 211; eSee 1, then go to MK 287.

 MK 209 is equivalent to K 207. The transition to MK 210.

MK 210. It is implemented similarly to K 208 and, in addition, the sign 89 is analyzed, formed in MK

35

55

Q 5

0 5

g,

g

five

five

209: if O, then go to MK 211; if 1, then go to MK 284.

MK 211. Under the control of field 18 from the outputs of block 3, the highest bits of the product arrive at the first information inputs of block 4, and the lower bits enter the second information inputs of the block, 4, where the control of field 19 fulfills their addition. Result from outputs 44 Block 4 is written to register 6 (under control of floor 21). Under the control of field 13, the contents of register 86 are written to the address of the order of results in register 82. The analysis of sign 72 formed in MK 205 is complete: if O, then go to MK 212; if 1, then go to MK 289.

MK 212. Under the control of field 17 from block 1, the mantissa X is read into the input of the ADF. Under the control of field 19 in block 4, the difference between the 1st antisess X and the contents of register 6 is calculated. The result from outputs 44 of block 4 is written to registers .5 and 6 In the corresponding triggers of node 101 of block 14, fic- tions (signs 59, 63, and 62. - Transition to MK 213.

MK 213. Under the control of floor 17, the register contents with the first address of block 1 to the input of Б34 are counted. The contents of register 5 are written to the ADF input and written to the register address with the second address in block 1. Under floor 19 control in block 4, the subtraction operation is performed and the result from step 44 is recorded in register 5. t Fixes are 63 and 62. The analysis of signs 59, 63 and 62 formed in MK 212 is complete: if 000, then go to MK 214: if 001, then go to MK 241; if 01X, then go to MA 238; if 1XX, then go to MK 242.

MK 214. Under control of field 23 in block 8, an increase in the unit of trial quotient is performed. From block 1 to input B34, the contents of the register with the first address are read. At the entrance of the ADP, the contents of register 5 oi are recorded at the third address in block 1. Under field control, block 4 is subtracted and the result from output 44 is recorded in registration table 5. Signs 59, 63 and 62 are recorded. signs 59, 63 and 62, formed in MK 213: if 000, then transition.

; MK 215; if 001, then go to MK; 240;. if OIXj to go to MK 238; if 1XX, then go to MK 259.; MK 215. Under control of field 23 IB block 8, an increase of | is performed; unit test private. From block 11, the contents of the register with the first address are read into input B34. The contents of register 5 are counted at the input of the ADF under control of floor 19 in block 4; The subtraction is fulfilled and the result from outputs 44 is written to register 6. Character 59 is recorded. Analysis of signs 59, 63 and 62 formed in MC 214 is fulfilled; if 000, then go to MK 216; if 001, then go to MK 217; if 01X, then go to MK 238; if 1XX, - then: go to MK 261.

MK 216o The content of block 8 is sent to the input of the ADF and then written to the high byte of the mantissa of the result in block 1. The contents of register 6 through multiplexer 7 (shifted by eight bits to the left) are poured in I on input B34 and then recorded in |. Register 6, Qoln analysis of feature 59 formed in MK 215; if O, then go to MK 245; if 1, then go to MK 246.

MK 217. In general, it is performed in the same way as MK 216. The transition to MK 218 without analyzing the conditions.

MK 218. In block 8, the zero value is written. The contents of register 6 through multiplexer 7 (with a shift of eight bits to the left) and through block 4 are written to register 5. The transition to MK 219.

i

MK 219. At the entrance of the APS, the contents of register 5 arrive, and the input of B34 from block 1 is found in the mantissa U. In block 4, the subtraction is completed and the result is written to register 5. The signs 59, 63 and 62 are fixed. The transition to MK 220.

MK 220. Under control of field 23, in block 8, an increase of counter 79 is completed. Under control of field 19, in block 4, subtraction-mantissa W is removed from register 5, and the result from outputs 44

ten

231; if 01X, then go to MK 237; if 1XX, then go to MK 230.

MK 221. Under control of field 23, block 8 contents are poured at the entrance of the ABP and then recorded in the second most significant byte of the mantissa of the result in block 1. Analysis of sign 59 is completed, formed in MK 220: if O, then go to MK 245;

15

20

thirty

if 1, then go to MK 222.

MK 222. The higher bits of the contents of register 5 at the entrance of the AZZ arrive at the first information inputs of block 11, its second information inputs post at input B34 of the higher bits of the mantissa Y from block 1. From block 11 a test quotient is read, the record is written to block 8 and from the inputs of the multiplier in block 3. Go to MK 223.

MK 223 o It is performed similarly to MK 210. Unconditional transition to MK 224.

MK 224. The word of the senior and the word of the younger bits (composed of the products of various multipliers 46) from the outputs of block 3 to the inputs of the APS and B34, respectively, goes to the inputs of block 4. In block 4, the addition is completed and the result from outputs 44 is written to Register 6. Transition to MK 225.

MK 225o In block 4, the subtraction of the contents of register 6 from the total register 5 is completed and the result is recorded in registers 5 and 6, signs 59, 63 and 62 are fixed. Transition to MK 226.

MK 226. Similar to MK 213. Analysis of signs 59, 63 and 62, formed in MK 225: if 000, then go to MK 227; if 001, then go to MK 239; if 01X, then go to MK 239; if 1XX, then go to MK 278.

MK 227. Similarly. 45 MK 214. Analysis of signs 59, 63, and 62, formed in MK 226: if 000, then go to MK 228; if 001, then go to MK 239; if 01Х, then go to MK 239; if 1XX, then 50 transition to MK 277.

MK 228. It is fulfilled similarly to F 215o. Analysis of signs 59, 63 and 62, formed in MK 227: e35

40

whether 000, then transition to MK 229; if 001 is recorded in register 5. 55 is fixed, then the transition to MK 239; if OIX, then sign 59. Complete analysis of the transition to MK 239; if 1XX, then remarks 59 .. 63 and 62, the move to MK 277 is formed,

1ShH in MK 219: if 000, then the transition MK 229s Under control of floor 23 to MK 221; if 001, then the transition to the MC contents of block 8 is sent over

0

231; if 01X, then go to MK 237; if 1XX, then go to MK 230.

MK 221. Under control of field 23, block 8 contents are poured at the entrance of the ABP and then recorded in the second most significant byte of the mantissa of the result in block 1. Analysis of sign 59 is completed, formed in MK 220: if O, then go to MK 245;

five

0

0

if 1, then go to MK 222.

MK 222. The higher bits of the contents of register 5 at the entrance of the AZZ arrive at the first information inputs of block 11, its second information inputs post at input B34 of the higher bits of the mantissa Y from block 1. From block 11 a test quotient is read, the record is written to block 8 and from the inputs of the multiplier in block 3. Go to MK 223.

MK 223 o It is carried out similarly to MK 210. Unconditional transition to MK 224.

MK 224. The word of the senior and the word of the younger bits (composed of the products of various multipliers 46) from the outputs of block 3 to the inputs of the APS and B34, respectively, goes to the inputs of block 4. In block 4, the addition is completed and the result from outputs 44 is written to Register 6. Transition to MK 225.

MK 225o In block 4, the subtraction of the contents of register 6 from the total register 5 is completed and the result is recorded in registers 5 and 6, signs 59, 63 and 62 are fixed. Transition to MK 226.

MK 226. Similar to MK 213. Analysis of signs 59, 63 and 62, formed in MK 225: if 000, then go to MK 227; if 001, then go to MK 239; if 01X, then go to MK 239; if 1XX, then go to MK 278.

MK 227. Similarly. 45 MK 214. Analysis of signs 59, 63, and 62, formed in MK 226: if 000, then go to MK 228; if 001, then go to MK 239; if 01Х, then go to MK 239; if 1XX, then 50 transition to MK 277.

MK 228. It is fulfilled similarly to F 215o. Analysis of signs 59, 63 and 62, formed in MK 227: EC5

0

whether 000, then transition to MK 229; if 001, 55 then go to MK 239; if OIX, then go to MK 239; if 1XX, then go to MK 277,

The input of the ADF is then recorded into the low byte of the mantissa of the result in block 1. The analysis of feature 59, cfb mirovannym in MK 228: if O, then go to MK 245; if 1, then go to MK 288.

MK 230. At the entrance of the AZZ to block 1 at the address of the second byte of the mantissa of the result under control of field 17, the zero operand is written. The contents of the register with the second address from block 1 are forwarded to input B34 through block 4 and written to register 5. The transition to MC 222.

MK 231 o Carry out similarly to W

217. The difference is that the contents of block 8 are recorded in the second byte of the mantissa of the result in block 1. Go to MK 232.

MK 232. Same as MK

218. Transition to MK 233.

MK 233o is complete as MK

219. Transition to MK 234.

MK 234, similar to MK

220. Analysis of feature 59, formed in MK 233: if O, then go to MK 235; if 1, then go to MK

236.

MK 235 Similar to MK 229.

MK 236. Under the control of floor 17 at the address of the lower byte of the mantissa of the result, a zero value is written to the block. Setting the trigger 102 block 14 in the unit. The end of the operation

MK 237 o The contents of block 8 at the input of the ADF are recorded at the address of the second byte of the mantissa of the result in block 1 Installing trigger 102 of block 14 into a unit. The end of the operation.

MK 238. The content of block 8 is sent to the input of the ADF and then written to the address of the third (most significant) byte of the mantissa of the result in block 1. Installing a trigger. 102 block 14: one. The end of the operation.

. MK 239 о The content of block 8 is interleaved at the input of the ABP and then recorded at the address of the baby byte of the result mantissa in block 1. Installing the trigger 102 of block 14 into the unit End of operation.

MK 240o Under health, field 17 from block 1, the contents of the register with the third address are read, sent to the ADF input through block 4 and then

0

five

0

.

Q

five

write to register 6. Transition to MC 217.

MK 241. Under the control of field 17, block 1 reads the contents of the register with the second address, sends it to the ADF input through block 4, and then writes it to register 6. The transition to Ж 217.

MK 242o The content of the counter 79 of block 8 is reduced by one. At the inputs of the AZZ and B34 from block 1 read-. The contents of the registers with the first and second addresses, respectively. In block 4, the addition is performed and the result of the sum from the outputs 44 is recorded in pegister 5 and 6. Signs 59, 63 and 62 are fixed. The transition to MK 243.

W 243 ° The content of the counter 79 of block 8 is reduced by one. At the entrance of the ADF from block 1, the register is read at the first address, and the register at the second address is sent to block 1 at input B34 and the contents of register 6 are written. At block 4, the addition is canceled and the result of the sum from the outputs 44 is written into register 6. Fixed signs 59, 63 and 62. The signs of signs 59, 63 and 62 formed in Ж 242 are canceled: if OXX, then go to MK 244; if 100, then the transition to Ж 267; if 101, then go to MK 266; if 11X, then go to MK 265.

MC 244. Performed similarly to MC 217. Analysis of signs 59, 63 and 62, formed in MC 243; if OXX, then go to MK 245; if 100, then go to MK 246; if 101, then go to MK 218; if 11X, then go to MK 238,

MK 245. - The error sign is set and the trigger 102 of the block 14. End of operation.

W 246. It is performed similarly to MK 222. The transition to W 247.

MK 247. It turns out similarly to F 223. The transition to F 248.

MK 248. Similarly, .J 224. The transition to MK 249.,

G 249. The procedure is similar to G 225. The transition to G 250.

MC 250. Similar to MC 226. Feature Analysis 59, 63. and 62, formed in Ж 249: ed-000, then the transition to MK 251; if 001, then go to MK 258; if 01X,

3115

then the transition to MK 237; if 1XX, then go to MK 269.

MC 251. It is performed in the same way as MC 227. Analysis of signs 59, 63, and 62 formed in MC 250: if 000, then go to MC 252; if 001, then go to MK 257; if 01Х, then go to MK 237; if 1XX, then go to MK 262.

MK 252. It is performed similarly to MK 228. Analysis of signs 59, 63 and 62 formed in MK 251: if 000, then go to MK 253; if 001, then go to MK 254; if 01Х, then go to MK 237; if 1XX, then go to MK 264.

MK 253. In general, it is similar to MK 216. The difference is that the contents of block 8 are passed to the AZP input and then written to the address of the second byte of the result mantissa in block 1. An analysis of the sign 59 formed in MK 252 is performed: if O , then the transition to MK 245; if 1, then go to MK 222s

MK 255. Similar to MK 232. Transition to MK 256.

MK 254. It is carried out similarly to MK 231. The transition to MK 255.

MK 256. Similar to MK, 233. Transition to MK 228.

MK 257. The contents of the block are forwarded to the input of the ABP and then written to block 1 at the address of the second byte of the mantissa of the result. The contents of the register at the third address from block 1 are forwarded to input B34 and through block 4 and then written to register 6. The transition to MC 232.

MK 258. In general, it is done in the same way as MK 257. The difference is that the input B34 from block 1

The contents of the register are assigned to this address. Transition to MK 232.

MK 259. Reducing the contents of the counter 79 block 8 per unit. From block 1, the contents of the register are read at the second address at the input of B34 and through block 4 are recorded in register 6. Go to MK 260.

MK 260. It is performed similarly to W 216. The transition to W 246.

MK 261. In general, it is similar to MK 259. The difference is that the input of B34 from block 1 reads the contents of the register at the third address, the Switch to MK 260.

3

32

, MK 262. Performs similarly to MK 259. The transition to MK 263.

MK 263. It is performed similarly to MK 253. The transition to MK 222.

MK 264. It is performed similarly to MK 261. JC MK 263 transition.

MK 265. The content of the counter 79 of block 8 is increased by one. Transition to MK 238.

MK 266. The content of the counter 79 of block 8 is increased by one. From block 1, the contents of the register are read to the input of the ABZ by a third address, which, through block 4, is written to register 6. Go to MK 217.

MK 267. Executes similarly to MK 266. The transition to MK 268.

MK 268. It is fulfilled similarly to MK 216. The transition to MK 246.

MK 269. Executes similarly to MK 242. The transition to MK 270.

MK 270. The process is similar to MK 243. Analysis of signs 59, 63 and 62 formed in MK 269: if OXX, then go to MK 271; if 100, then go to MK 272; if 101, then go to MK 274; if 11X, then go to MK 276.

MK 271. In general, it is done in the same way as MK 244. The difference is that the contents of block 8 are sent to the AZP input and written to block 1 at the address of the second byte of the result mantissa. Complete recognition analysis

cow 59, 63

n 62, formed in MK 270: if OXH, then go to MK 245; if 100, then go to MK 222; if 101, then go to MK 255; if 11X, then go to MK 237.

MK 272. Performs similarly to MK 266. The transition to MK 273.

MK 273. It is performed similarly to MK 263. The transition to MK 222.

MK 274. It is performed similarly to MK 266. Transition to MK 275.

MK 275. It is performed similarly to MK 263. Transition to MK 255.

MK 276. Is similar to MK 265. The transition to MK 237.

MK 277. Supportable counter 79

block 8 is reduced Transition to MK 239.

per unit.

MK 278. It is performed similarly to MK 242. Transition to MK 279.

MK 279. It is fulfilled similarly to MK 243. Analysis of the sign 59 formed in MK 278: if O, then

transition to MK 280; if 1, then go to MK 281..

MK 280. Is similar to MK 271. Analysis of feature 59 formed in MK 279: if O, then go to MK 245; if 1, then go to MK 239.

MK 281. Is similar to MK 265. The transition to MK 239.

MK 382. In block 13, the contents of register 86 are incremented by one. In block 1, a constant (10,000,000) is written at the address of the high byte of the mantissa of the result. Transition to MK 283.

MK 283. The contents of register 86 are recorded at the address of the result order in register 82 of block 13. In block 1, at the address of two lower bytes of the result mantis, zero operations are written. The trigger 102 of block 14 is set to one. End of operation.

; MK 284. In register 82 of block 13 at the address of the result result is written

zero operand. In block 1, the zero operand is written to the mantissa address of the result. Setting the trigger 102 block 14 in the unit. The end of the operation.

MK 285. In block 13, the contents of register 86 are incremented by one. A transfer attribute 89 is fixed. In block 1, the stantant (10,000,000) is written to the address of the high byte of the man-tisses of the result. 102 block 14. End of operation. Analysis of the sign 89 formed in MK 285: if O, then go to MK 288; if 1, then go to MK 284.

MK 287. In register 82 of block 13, at the address of the result order, a value is written, all bits of which are equal to one. At the address of the result mantissa, in block 1, a value is written, all bits of which are equal

unit. Installation in

unit

trigger 102 block 14. tion.

MK 288. Installation in the trigger block 102 14. tion.

unit

MK 289. Installation in the trigger Division by zero and trigger 102 of the block 14. End of operation.

The block diagram of the algorithm for calculating the 1 / UX function for single precision of the floating-point format is shown in FIG. 18 and contains micro-commands MK 290-331.

. MK 290. Under control of floor 17 from block 1 from input B34, the mantissa of operand X is pushed, the group of higher bits is fed to the information inputs of block 12. The value of the test root (eight bits) from block 12 postz. It goes to the inputs of block 3. The order of the PC operand X in block 13 reads from register 82 and is written to register 86. Sign 92 (the value of the least significant bit is fixed) and the sign 32 of the operand are recorded. Transition to MK 291.

MK 291. In block 13, the contents of register 86 increased by 1 units per unit 11

five

thirty

35

40

and the sign 89 is fixed. From block 1 on the input: one of B34 reads the mantissa of the operand X and records the multiplicand from the inputs of the block 3. Block 3. Analysis of signs 92 and 32 formed in MK 290: if 00, go to MK 328; if 10, then go to MK 292; if XI, then go to MK 329.

MK 292. From block 1, the mantissa X is read at the input of the ADF, sent through block 10 (shifted by one bit to the right) to the input of B34 and written to the registers of block 1 at the first address and from the inputs of the multiplicand to block 3, and also goes to information inputs of the block 12. The trial root value from the outputs of block 12 is fed to the inputs of the multiplier of block 3. Cycle ie analysis of the sign 89 formed in MK 291: if O, then go to MK 293; if 1, then go to MK331.

MK 293. In Lock 3, multiplication of the operands is performed. The contents of the register with the first address are recorded in block 1 at the mantissa address of operand X. The transition to the MK 294.

MK 294. The high and low bits of block 3 are received respectively on the first and second inputs of block 4. In the last, addition is completed, and the result from outputs 44 is written to register 6. Transition to MK 295 ..

50

55

MK 295. The contents of register 6 are fed to the inputs of the multiplier multiplier and are recorded in block 3. The transition to MK 296.

MK 296. In block 3, the multiplication of operands is complete. Transition to MK 297.

MK 297, is implemented in general, similarly to MK 294. The difference is that the result from outputs 44 of block 4 is written to register 5. The transition to MK 298.

MK 298. An operation is performed in the block (register 5-1) and the result from outputs 44 is written to register 5. The transition to MK 299.

MK 299. The contents of register 5 are forwarded to the input of the AZZ and through the block -. U (shifted one bit to the right) to the input of B34 and then through block 4 is written into register 6, the Transition to the MK 300.

The MK 300. In block 4, the unit is executed (1 - register 6) and the result from outputs 44 is recorded in register 6. The transition to MK 301.

MK 301, the contents of register 6 are transmitted to input B3.4 and are recorded in block 3 from the inputs of the multiply. The transition to MK 302.

MK 302. The multiplication of operands into block 3 is fulfilled. From node 101 of block 14, the contents of trigger 116-2 controlled by field 112 through elements 124, 127 from output 45 are transferred to the AZP input and written to sign bits of block 1. Go to MK 303

MK 303. Performed similarly to MK 297. The transition to MK 304.

MK 304, From block 1 to input B34, the mantissa of operand X is read and written from the inputs of the multiplicand to block 3. The contents of register 5 are transferred to the ADF input and written to the register with the first address of the registers of block 1, and the second byte of this number is transmitted through Multiple Plexor 2 at the inputs of the multiplier and recorded in block 3. Transition to MK305

MK 305. Performed similarly to MK 302. Transition to MK 306.

MK 306. Performed similarly to MK 296. The transition to MK 307.

MK 307. The high byte of the contents of the register with the first address of the registers of block 1 from the entrance of the AZZ through multiplexer 2 is fed to the inputs of the multiplier

0

five

0

five

about

and is written in block 3. Go to MK 308..

MK 308. In block 3, the multiplication of the operands is performed. The contents of register 5 are transmitted to input B34 via block 10 (shifted eight bits to the right) to input B34 and then recorded to register 6 from block 4. Transition To MK 309.

MK 309 It is implemented similarly to G 303. The transition to MK 310.

MK 310. In block 4, the operation is performed (register 5 + register 6)) and 5. The result from outputs 44 is written to register 6o. The transition to MK 311.

MK 311. The contents of register 6 are transmitted at the input of B34 and written from the inputs of the multiplicand to block 3. The second most significant byte of the contents of the register, with the first address is found, from block 1 to the input, the ADF and through multiplexer 2 is recorded from the inputs 35 multiplier in block 3. Go to MK 312.

MK 312. Performed similarly to MK 296. The transition to MK 313.

The MK 31 is implemented similarly to the MIC297. Transition to MK 314.

MK 314. The second most significant byte of the register contents is read from block 1 to the input of the ABP and, via multiplexer 2, is written from the inputs -35 multiplier to block 3. The transition to MK 315.

MK 315. It is performed similarly to W 308. Go to MK 316.

MK 316. It is performed in the same way as G 297. Go to MK 317.

MK 317. In block 4, an operation is performed (register 5 + register 6) and the result from outputs 44 is written to register 5. The transition to MK 318.

MK 318. It is implemented similarly to MK 298. The transition to MK 319.

MK 319, Performed similarly to MK 299. The transition to MK 320.

MK 320. Performed similarly to W 300, Transition to MK 321.

MK 321 About Vsoln ETs similarly to F 311 “Transition to MK 322,

MK 322. Performed similarly to MK 296. The transition to MK 323.

MK 323. Be similar to W 297, Transition to MK 324,

MK 324. Similarly. W 307. Transition to MK 325,

MK 325. Performed similarly to g; 308, Transition to MK 326,

45

50

55

MK 326. Fulfilled similarly to W 297. The transition to MK 327 ..

MK.327. In block 4, the operation is completed (register 5 + register 6) and the result from outputs 44 is written to register 5. The contents of the register, 86 in block 13 are poured through adder 83, multiplexer 85 (shifted by one bit to the right) and writes down Register 86. Transition to MK 328.

MK 328. The contents of register 5 are poured at the entrance of the ABP and recorded at the address of the result mantissa in block 1. The contents of register 86 in block 13 are recorded at the address of the result result in register 82.

pe-

Installation in unit of the trigger 102 of the block 14. End of operation.

MK 329. In block 3, the operand multiplication is completed. The order of the HRP in block 13 of the register 82 is poured through szl 1mator 83, multiplexer 85 (with a shift by one bit

in) and recorded in register 86. The feed is increased by 32 micromanagement to the MC 294.y.

MK 330. Setting the sign of the Zero operand. Installation in unit of the trigger 102 of the block 14. End of operation.

MK 331e The overall performance is similar to MK.293. In addition, under the control of field 27, a code is written to the register 86 of the block 13, which contain units to the MK 294.

The floating point subtraction and addition operations for double format numbers (p 64) are executed by the analog formula.

thirty

all bits

A data processing device containing a block of general registers for values, two multiplexers, a multiplication unit, an ari-logical mantissa block, two buffer registers J. a left unit search node, an offset unit, an order arithmetic unit, and a firmware control unit, with inputs the start of operation, the operation code and the clock input of the device

a flow chart diagram of the algorithms (Fig. 12, connected to the corresponding inputs

13). The difference lies in the values of bits 64, 65 of the control field 19.

The operation of multiplying 64-bit one microprogrammed control unit, the signal output of which is the output of the operation of the device and the information output of the rifmetico-log

rand with a floating comma of an et-dd block mantissa unit is connected to another similarly to the operation of multiplying 32-bit floating-point operands ..

The multiplication of the multiplicand is performed by seven groups of (byte) bits of the multiplier. The partial product of the multiplier by the first (low) byte of the multiplier is accomplished with the help of MK 186-191 (Fig. 14), by the second, T15, fourth, fifth and sixth - similar to the multiplication by the second byte of the multiplier in the flowchart of the algorithm presented in FIG. 14, using MK 192-195 for each of

bows, on the seventh byte of the multiplier - similar to multiplication by the third byte of the multiplier using the MK 196-199. In this way, the computation time for the 64-bit operands is increased by 16 microcommands.

The division operation of the 64-bit floating point operands is performed by an algorithm similar to that shown in FIG. 15-17. The seven bytes of quotients are calculated: the seventh (most significant) bytes is determined similarly to the third byte using

MK-204-215; the second, third, fourth, fifth and sixth bytes define

c similar to the second byte using MK 246-253 (in the case of a positive error) or NK 267-271 (in the case of a 20% error, the determination of the trial quotient); the first byte is similar to the first byte using the MK 242-244. The time to determine the quotient for a 64-bit opera Formula of the invention

A data processing device comprising a general purpose register unit, two multiplexers, a multiplication unit, an ari-logical mantissa block, two buffer registers, a left unit search node, a shift unit, an order arithmetic unit, and a firmware control unit, and the start inputs, the operation code and the clock input of the device of the firmware control unit, the signal output of which is the output of the device operation end, the information output of the rhyme and logic information inputs of the first and second signals ernyh registers, a first bidirectional data input coupled to the USG roystva information

 50 inputs of the first multiplexer, the output of the second buffer register is connected to the first information input of the second multiplexer, the high and low bits of the multiplier co55 are one with the bits of the first and second information inputs of the arithmetic logic unit of the left unit with: ..39 i5

(Dinen with the information input of an arithmetic 1 | 1ethetical block of orders, the information-ijtHOHHbift output of which is connected to the shift control unit shift magnitude, from the first to the eighth control outputs of the control firmware unit are connected to the input razreshni first multiplexer, with the input of the setting of the shift block shift direction, with the input of the “Adding the state of the general purpose registers block, with the resolution input) the multiplication locus, with the group of the arithmetic logic-mathissa-block inputs, with the input of the job mode per from the first to the fifth inputs of the conditions of the microprogram control unit are connected to the signal unit of the mantissa logic-logic unit, with the signal output of the left unit search node, The signal output of the arithmetic block of orders, with the inputs of the sign bits of the first and second, bidirectional information inputs of the device, characterized in that, in order to expand the application area Due to the implementation of the calculation of the reciprocal of the square root and the use of the bus structure, it contains a private unit for approximate dividing unit and a unit for the approximate root unit, with the first bi-directional information input of the device connected to the first information input / output unit of the general-purpose registers the input node of the left unit search, with the first informational input of the arithmetic logic unit mantis, with the output of the first buffer register and with you the course of the correction block private, the input fpynribi senior bits of the first information bidirectional input 3 0

and the device is connected to the first informational input of the approximate division unit and to the information output of the firmware control unit, the output of the second buffer register is connected ,. with a shift of eight bits to the left, with the second information input of the second multiplexer, as well as with the first information input of the shift unit, the second information input of which is connected to the first bi-directional information input of the device, the second information bi-directional input of which is connected to the second information input-output block of general purpose registers, with the second information input of the arithmetic logic unit

mantis, with. the input of the first multiplier of the multiplication unit, with the output of the Second multiplexer and with the output of the shift block, the input of the group of higher bits of the second bidirectional information input of the device is connected to the information input of the approximate calculation block root and the second information input of the block: - approximate division, the output of the first multiplexer is connected the input of the second multiplier of the multiplication unit, with the second information input of the search node of the left unit, with the information input of the correction block private, and

also with the outputs of the approximate dividing unit and the approximate calculation unit of the root, the second information output of the left unit search node is connected to the control input of the primary

multiplexer, from ninth to

The thirteenth ton of etching outputs of the firmware control block are connected respectively to the input of setting the mode of the private correction block, to the input of setting the mode of the search unit of the left unit, to the inputs of the resolution of blocks — approximate division and approximate calculation of the root, to the input of setting the mode of the arithmetic block of orders.

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Compiled by A, Klyuev Editor I. Gorna Tehred L.OliynykKorrektor 0. Kravtsova

Order 6080/48

Circulation 668

VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5

FIG. 18

Subscription

Claims (1)

rmula of the invention A data processing device comprising a general purpose register block, two multiplexers, a multiplication block, a mantiss arithmetic logic block, two buffer registers, a left unit search unit, a shift block, an arithmetic order block and a microprogram control block, the operation start inputs and the operation code and the clock input of the device is connected to the corresponding inputs of the microprogram control unit, the signal output of which is the output of the end of the device, the information output of the arithmetic-logoformation the inputs of the first and second buffer registers, the first bi-directional information input of the device is connected to the information input of the first multiplexer, the output of the second buffer register is connected to the first information input of the second multiplexer, the outputs of the upper and lower bits of the multiplication unit are connected to the inputs of the bits of the first and second left unit search information input unit arithmetic-logic unit mantissas, the first data output co-one with ^39,151 data input ap of the phmetical order block, the information output of which is connected to the input of the shift value of the fdw block, the first to eighth control outputs of the microprogram control block are connected respectively to the input of the resolution of the first multiplexer, c) the input of the job of the shift direction of the shift block, , with the input of the job of the mode of the block of general registers, with the permission input of the 5th multiplication block, with the group of inputs of the job of the mode of arithmetic-logical-15? about the mantissa block, with the input of the job of the mode of the first buffer register, with in in the course of setting the second buffer register mode and with the control input of the second multiplexer, from the first to fifth inputs 20 conditions of the microprogram control block are connected respectively to the group of signal outputs of the arithmetic-logical block mantiss, with the signal output of the search unit of the left 25 units, with a signal output • arithmetic unit of orders, with inputs of sign bits of the first and second, bidirectional information inputs of the device, t l and 3Q, characterized in that, in order to expand the scope of application due to the operation of calculating the inverse ^ square root value and using the bus structure, it contains a partial correction unit, an approximate division unit and an approximate root calculation unit, the first bi-directional information input of the device being connected to the first information input / output of the general purpose register block, to the first information the input of the search unit of the left unit, with the first information input of the arithmetic-logical block of the mantissa, with the output of the first buffer register and with you; by the course of the private correction block, the input of the High-order group of the first information bi-directional input! f3 ⁴⁰ and the device is connected to the first information input of the approximate division block and to the information output of the microprogram control unit, the output of the second buffer register is connected .; with a shift of eight bits to the left, with a second information input of the second multiplexer, as well as with the first information input of the shift unit, the second information input of which is connected to the first bi-directional information input of the device, the second information bi-directional input of which is connected to the second information input-output of the register block of the common destination, with the second information input of the arithmetic-logical unit mantiss, s. the input of the first factor of the multiplication block, with the output of the Second multiplexer and with the output of the shift block, the input of the group of high bits of the second bidirectional information input of the device is connected to the information input of the block of approximate root calculation and with the second information input of the block of approximate division, the output of the first multiplexer is connected to the input of the second factor of the multiplication block, with the second information input of the left unit search node, with the information input of the private correction block, as well as with the outputs of As an approximate division and an approximate root calculation block, the second information output of the left search unit is connected to the control input of the first multiplexer; from the ninth to thirteenth, the control outputs of the microprogramme control unit are connected respectively to the input of the mode of the correction block private, with the input setting the mode of the search unit of the left unit, with inputs for resolving blocks of approximate division and approximate calculation of the root, with the input of the mode setting of the arithmetic unit of orders.