SU842814A1 - Microprogramme control device - Google Patents

Description

(54) FIRMWARE CONTROL DEVICE

the outputs of the sign of the address offset are connected to the corresponding first and second inputs of the epement block. 2I-OR-NOT, the output of which is connected to the second input of the 2I-OR element block, the third input of which is the device input, the fourth, fifth and sixth inputs of the ZI-OR element block, the fourth and fifth inputs of the 2I-OR block block , the third and fourth inputs of the block of elements 2I-OR-NOT, the second inputs of the first and second elements AND are connected to the corresponding output of the decoder of micro-instructions. In addition, the command unpacking block contains the registers of the zero and unit masks, AND, OR elements, the first input of the command unpacking block is connected to the first input of the AND element, the second input of which is connected to the output of the zero mask register, and the output connected to the first input of The OR, whose output is connected to the output of the command decompression unit, and the second input to the output of the unit mask register, whose information input is connected to the information input of the zero mask register, is the second input of the command unpacking unit.

The drawing shows a functional diagram of the device.

The scheme contains a block 1 pgshi, register 2 micro-commands / accumulating adder 3, register 4 commands, blocks of elements 2И-OR and ZI-OR 5 and b, respectively, block 7 unpacking first and second elements AND 8 and 9, respectively, block 10 elements 2И -OR-NOT, descrambler 11 micro-commands Block 7 of unpacking commands consists of registers 12 and 13 of the zero and unit masks, respectively, of the elements AND 14 and OR 15.

The device works as follows.i

In the initial state, before executing the next microprogram, the corresponding command is entered into register 4, information is loaded into the register 12 of the zero mask of memory block 1, with which in the command register 4 the operational code must be selected, which may include the format code , opcode / various signs of modification. In addition, a register 13 of a single mask is loaded from memory 1, with which address constants are entered into one code read from register 4 of commands.

The execution of the microprogram starts the q formation of the iiutpeca cell in the memory block 1, which contains the address of the first microcommand in the used microprogram. To this end, the register bits of 4 commands 7 disguised with the element

and 14, the contents of the zero mask register 12 are replaced on the OR 15 element by address constants from the register 13 of the unit mask. As a result, the output of the AND 9 element turns out to be the formed address of the cell in which the initial address of the microprogram, consisting of the operation code, taken directly from the command, and the address center, is stored. After the transition to the beginning of the microprogrammer, in the course of its implementation, it can perform three types of transitions: natural, associated with an increase in the content of the accumulating adder by +1, unconditional and conditional.

Consider doing the last two.

In the unconditional transition, the address is read directly from the output of memory block 1, from where it is entered through the control signal in blocks 5 and 6 of the 2И-OR and ZI-OR into the accumulating adder 3, from the output of which And 8 by the signal from enters memory block 1. The contents of the selected cell are recorded in the 2 micro-register register. Since the element 9 and the signal 61 is closed, the information from the output of the element 8 does not arrive at the output of the command unpacking unit.

f

When performing a conditional transition, either a natural transition is performed, in which the contents of accumulative adder 3 is incremented by one, or a transition is made to A1 or A2. In the latter case, the addresses A1 or A2 from the register of 2 micro-commands through the block 6 of the elements ZI-OR or on the control signal e or f enters the lower bits of the accumulating adder 3, into the higher rp of which from the output of the block 5 el (vymya 2I- OR is set to a permanent code 0000 or 1111, depending on the sign of the address offset, which is formed on the first or third outputs of the register 2 microcommands "Adding a constant code to the higher bits of the address is caused by the fact that to make the transition to +16 addresses relative to the current address in case of displacements, sufficient to add the contents of the adder 3 A1 (A2), and if negative - must dopoliitelno of contents on the adder 3 Subtract 16.

The generated address from the output of the accumulator accumulator 3, via the AND element 8, via the signal c, is fed to the input of the memory block 1. The control of the blocks of elements 2I-YI-NOT, 2I-OR, and Z-Ida is carried out by the decoder 11 Microcommands.

The formation of the initial address of the microprogram by maskings performed in the command decompression block allows the initial addresses of microcommands to be placed in an arbitrary memory area. In addition, the position and length of the operating fields in commands may be arbitrarily changed. In this case, hardware reconfiguration is not necessary, but it is only necessary to write to the memory block the microprogram of the search and extraction of these fields. At the same time, a nonsharp dynamically changing sample point when generating the jump addresses, due to the use of the accumulator accumulator as the address register, allows linking of the neighboring zones S to the memory block without using additional unconditional jump micro instructions.

This expansion of functional capabilities makes it possible to simply program the implementation of the device by various command systems, as well as to reduce the number of micro-commands in the microprograms.

Claims (2)

1. A microprogrammed control unit containing a memory block whose output is connected to the information input of the microcomputer register Hip, whose information output is connected to the input of the micro-command decoder, the command register, blocks of elements and ZI-OR, which, in order to increase the functionality due to the implementation of the firmware execution of commands with an arbitrary structure, it contains accumulating 11 (the adder, the command unpacking unit, the block of elements 2I-OR-NOT, the elements AND, and the outputs of the blocks of elements 2I- IL and ZI-OR are connected respectively to the first and second inputs of the accumulating adder, the output of which is connected to the first input of the first element I, the output of which is connected with the address input of the memory unit and with the output of the second element I, the first input of which is connected to the output of the command unpacking unit, the first input of which is connected to the output of the command register, the second input of the command unpacking unit is connected to the output of the memory unit and to the first inputs of the blocks of elements 2И - OR and ZI-OR, the second and third inputs of the last are connected respectively to the first and second outputs of the register of micro-commands, the first and second outputs of the sign of the address offset of which are connected respectively to the first and second inputs of the block elements 2I-OR-NOT, the output of which is connected to the second input of the block of elements 2I-OR, the third input of which is the input of the device, the fourth, fifth and sixth inputs of the block of elements ZI-OR, the fourth and fifth inputs of the block of elements 2I-OR , the third and fourth inputs of the block of elements 2I-OR-NOT, the second inputs of the first and second elements AND are connected to the corresponding output of the decoder of micro-instructions. 2. Device nbrii 1, characterized in that the command unpacking unit contains zero and unit registers, masks, AND, OR elements, the first input of the command unpacking unit connected to the first input of the AND element, the second input of which is connected to the output of the zero mask register, and the output of the AND element is connected to the first input of the OR element, the output of which is connected to the output of the command decompression unit, and the second input to the output of the unit mask register, whose information input is connected to the information input of the zero mask register and is the second input block unpacking commands. Sources of information taken into account in the examination 1. Author's certificate of the USSR 387366, cl. G 06 F 15/16, 1972. 2. Authors certificate of the USSR 342380, cl. G 06 T 9/00, 1968 (prototype),